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From: Borislav Petkov <bp@alien8.de>
To: Ross Zwisler <ross.zwisler@linux.intel.com>
Cc: linux-kernel@vger.kernel.org,
	H Peter Anvin <h.peter.anvin@intel.com>,
	Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH v3 2/2] x86: Add support for the clwb instruction
Date: Wed, 28 Jan 2015 11:58:52 +0100	[thread overview]
Message-ID: <20150128105852.GF12929@pd.tnic> (raw)
In-Reply-To: <1422377631-8986-3-git-send-email-ross.zwisler@linux.intel.com>

On Tue, Jan 27, 2015 at 09:53:51AM -0700, Ross Zwisler wrote:
> Add support for the new clwb (cache line write back) instruction.  This
> instruction was announced in the document "Intel Architecture
> Instruction Set Extensions Programming Reference" with reference number
> 319433-022.

...

> After this function completes the data pointed to by vaddr is has been
> accepted to memory and will be durable if the vaddr points to
> persistent memory.
> 
> Regarding the details of how the alternatives assembly is set up, we
> need one additional byte at the beginning of the clflush so that we can
> flip it into a clflushopt by changing that byte into a 0x66 prefix.  Two
> options are to either insert a 1 byte ASM_NOP1, or to add a 1 byte
> NOP_DS_PREFIX.  Both have no functional effect with the plain clflush,
> but I've been told that executing a clflush + prefix should be faster
> than executing a clflush + NOP.
> 
> We had to hard code the assembly for clwb because, lacking the ability
> to assemble the clwb instruction itself, the next closest thing is to
> have an xsaveopt instruction with a 0x66 prefix.  Unfortunately xsaveopt
> itself is also relatively new, and isn't included by all the GCC
> versions that the kernel needs to support.
> 
> Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
> Cc: H Peter Anvin <h.peter.anvin@intel.com>
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Borislav Petkov <bp@alien8.de>

Acked-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

  reply	other threads:[~2015-01-28 20:25 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-27 16:53 [PATCH v3 0/2] add support for new persistent memory instructions Ross Zwisler
2015-01-27 16:53 ` [PATCH v3 1/2] x86: Add support for the pcommit instruction Ross Zwisler
2015-01-28 10:58   ` Borislav Petkov
2015-01-28 17:10   ` Elliott, Robert (Server Storage)
2015-01-28 17:21     ` Borislav Petkov
2015-01-28 17:27       ` Ross Zwisler
2015-02-11 22:24   ` H. Peter Anvin
2015-02-19  0:29   ` [tip:x86/asm] " tip-bot for Ross Zwisler
2015-02-19  1:15     ` Ingo Molnar
2015-02-19 17:21       ` Ross Zwisler
2015-02-19 17:33         ` Borislav Petkov
2015-02-19 17:41           ` Ross Zwisler
2015-01-27 16:53 ` [PATCH v3 2/2] x86: Add support for the clwb instruction Ross Zwisler
2015-01-28 10:58   ` Borislav Petkov [this message]
2015-02-11 22:25   ` H. Peter Anvin
2015-02-19  0:29   ` [tip:x86/asm] " tip-bot for Ross Zwisler
2015-04-02 20:31     ` Ross Zwisler
2015-04-03  5:04       ` Ingo Molnar
2015-04-03  5:10   ` [tip:x86/asm] x86/asm: Add support for the CLWB instruction tip-bot for Ross Zwisler
2015-02-05 16:24 ` [PATCH v3 0/2] add support for new persistent memory instructions Ross Zwisler

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