LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
* [PATCH 2/2] ARM: l2c: Maintain CPU endianness for early resume function
@ 2015-01-20 12:36 Dmitry Osipenko
  2015-03-11 10:18 ` Thierry Reding
  0 siblings, 1 reply; 4+ messages in thread
From: Dmitry Osipenko @ 2015-01-20 12:36 UTC (permalink / raw)
  To: digetx, Russell King
  Cc: Ben Dooks, Bob Mottram, linux-tegra, linux-arm-kernel, linux-kernel

In big endian CPU mode l2x0_saved_regs structure stores registers values in BE
format. In order to maintain BE CPU mode, these values and immediate constants
must be converted back to LE format before writing them to cache controller.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/mm/l2c-l2x0-resume.S | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S
index fda415e..9f99c7e 100644
--- a/arch/arm/mm/l2c-l2x0-resume.S
+++ b/arch/arm/mm/l2c-l2x0-resume.S
@@ -30,6 +30,15 @@ ENTRY(l2c310_early_resume)
 	teq	r1, #0
 	reteq	lr
 
+	@ Reverse for big endian kernel
+ARM_BE8(rev	r2, r2)
+ARM_BE8(rev	r3, r3)
+ARM_BE8(rev	r4, r4)
+ARM_BE8(rev	r5, r5)
+ARM_BE8(rev	r6, r6)
+ARM_BE8(rev	r7, r7)
+ARM_BE8(rev	r8, r8)
+
 	@ The prefetch and power control registers are revision dependent
 	@ and can be written whether or not the L2 cache is enabled
 	ldr	r0, [r1, #L2X0_CACHE_ID]
@@ -51,6 +60,7 @@ ENTRY(l2c310_early_resume)
 
 	str	r2, [r1, #L2X0_AUX_CTRL]
 	mov	r9, #L2X0_CTRL_EN
+ARM_BE8(rev	r9, r9)
 	str	r9, [r1, #L2X0_CTRL]
 	ret	lr
 ENDPROC(l2c310_early_resume)
-- 
2.2.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/2] ARM: l2c: Maintain CPU endianness for early resume function
  2015-01-20 12:36 [PATCH 2/2] ARM: l2c: Maintain CPU endianness for early resume function Dmitry Osipenko
@ 2015-03-11 10:18 ` Thierry Reding
  2015-03-11 13:12   ` Russell King - ARM Linux
  2015-03-15 19:06   ` Dmitry Osipenko
  0 siblings, 2 replies; 4+ messages in thread
From: Thierry Reding @ 2015-03-11 10:18 UTC (permalink / raw)
  To: Russell King, Dmitry Osipenko, linux-tegra, Ben Dooks,
	linux-arm-kernel, Bob Mottram, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 2015 bytes --]

On Tue, Jan 20, 2015 at 03:36:55PM +0300, Dmitry Osipenko wrote:
> In big endian CPU mode l2x0_saved_regs structure stores registers values in BE
> format. In order to maintain BE CPU mode, these values and immediate constants
> must be converted back to LE format before writing them to cache controller.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  arch/arm/mm/l2c-l2x0-resume.S | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Hi Russell,

Did you get a chance yet to review this patch? It's a dependency for
enabling big-endian support on Tegra. As such, I wonder if you would be
willing to ack it, so that I can take it through the Tegra tree along
with the rest of the patches.

If you prefer to take it through the ARM tree, that's fine, too. In that
case would you be able to provide a stable branch that I can merge into
the Tegra tree to resolve the dependency?

Thanks,
Thierry

> diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S
> index fda415e..9f99c7e 100644
> --- a/arch/arm/mm/l2c-l2x0-resume.S
> +++ b/arch/arm/mm/l2c-l2x0-resume.S
> @@ -30,6 +30,15 @@ ENTRY(l2c310_early_resume)
>  	teq	r1, #0
>  	reteq	lr
>  
> +	@ Reverse for big endian kernel
> +ARM_BE8(rev	r2, r2)
> +ARM_BE8(rev	r3, r3)
> +ARM_BE8(rev	r4, r4)
> +ARM_BE8(rev	r5, r5)
> +ARM_BE8(rev	r6, r6)
> +ARM_BE8(rev	r7, r7)
> +ARM_BE8(rev	r8, r8)
> +
>  	@ The prefetch and power control registers are revision dependent
>  	@ and can be written whether or not the L2 cache is enabled
>  	ldr	r0, [r1, #L2X0_CACHE_ID]
> @@ -51,6 +60,7 @@ ENTRY(l2c310_early_resume)
>  
>  	str	r2, [r1, #L2X0_AUX_CTRL]
>  	mov	r9, #L2X0_CTRL_EN
> +ARM_BE8(rev	r9, r9)
>  	str	r9, [r1, #L2X0_CTRL]
>  	ret	lr
>  ENDPROC(l2c310_early_resume)
> -- 
> 2.2.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[-- Attachment #2: Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/2] ARM: l2c: Maintain CPU endianness for early resume function
  2015-03-11 10:18 ` Thierry Reding
@ 2015-03-11 13:12   ` Russell King - ARM Linux
  2015-03-15 19:06   ` Dmitry Osipenko
  1 sibling, 0 replies; 4+ messages in thread
From: Russell King - ARM Linux @ 2015-03-11 13:12 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Dmitry Osipenko, linux-tegra, Ben Dooks, linux-arm-kernel,
	Bob Mottram, linux-kernel

On Wed, Mar 11, 2015 at 11:18:46AM +0100, Thierry Reding wrote:
> On Tue, Jan 20, 2015 at 03:36:55PM +0300, Dmitry Osipenko wrote:
> > In big endian CPU mode l2x0_saved_regs structure stores registers values in BE
> > format. In order to maintain BE CPU mode, these values and immediate constants
> > must be converted back to LE format before writing them to cache controller.
> > 
> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> > ---
> >  arch/arm/mm/l2c-l2x0-resume.S | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> 
> Hi Russell,
> 
> Did you get a chance yet to review this patch? It's a dependency for
> enabling big-endian support on Tegra. As such, I wonder if you would be
> willing to ack it, so that I can take it through the Tegra tree along
> with the rest of the patches.

Yes, it's fallen through the cracks.

Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>

Thanks.

-- 
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/2] ARM: l2c: Maintain CPU endianness for early resume function
  2015-03-11 10:18 ` Thierry Reding
  2015-03-11 13:12   ` Russell King - ARM Linux
@ 2015-03-15 19:06   ` Dmitry Osipenko
  1 sibling, 0 replies; 4+ messages in thread
From: Dmitry Osipenko @ 2015-03-15 19:06 UTC (permalink / raw)
  To: Thierry Reding, Russell King, linux-tegra, Ben Dooks,
	linux-arm-kernel, Bob Mottram, linux-kernel

11.03.2015 13:18, Thierry Reding пишет:
> On Tue, Jan 20, 2015 at 03:36:55PM +0300, Dmitry Osipenko wrote:
>> In big endian CPU mode l2x0_saved_regs structure stores registers values in BE
>> format. In order to maintain BE CPU mode, these values and immediate constants
>> must be converted back to LE format before writing them to cache controller.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>>   arch/arm/mm/l2c-l2x0-resume.S | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>
> Hi Russell,
>
> Did you get a chance yet to review this patch? It's a dependency for
> enabling big-endian support on Tegra. As such, I wonder if you would be
> willing to ack it, so that I can take it through the Tegra tree along
> with the rest of the patches.
>
> If you prefer to take it through the ARM tree, that's fine, too. In that
> case would you be able to provide a stable branch that I can merge into
> the Tegra tree to resolve the dependency?
>
> Thanks,
> Thierry
>
>> diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S
>> index fda415e..9f99c7e 100644
>> --- a/arch/arm/mm/l2c-l2x0-resume.S
>> +++ b/arch/arm/mm/l2c-l2x0-resume.S
>> @@ -30,6 +30,15 @@ ENTRY(l2c310_early_resume)
>>   	teq	r1, #0
>>   	reteq	lr
>>
>> +	@ Reverse for big endian kernel
>> +ARM_BE8(rev	r2, r2)
>> +ARM_BE8(rev	r3, r3)
>> +ARM_BE8(rev	r4, r4)
>> +ARM_BE8(rev	r5, r5)
>> +ARM_BE8(rev	r6, r6)
>> +ARM_BE8(rev	r7, r7)
>> +ARM_BE8(rev	r8, r8)
>> +
>>   	@ The prefetch and power control registers are revision dependent
>>   	@ and can be written whether or not the L2 cache is enabled
>>   	ldr	r0, [r1, #L2X0_CACHE_ID]
>> @@ -51,6 +60,7 @@ ENTRY(l2c310_early_resume)
>>
>>   	str	r2, [r1, #L2X0_AUX_CTRL]
>>   	mov	r9, #L2X0_CTRL_EN
>> +ARM_BE8(rev	r9, r9)
>>   	str	r9, [r1, #L2X0_CTRL]
>>   	ret	lr
>>   ENDPROC(l2c310_early_resume)
>> --
>> 2.2.1
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

This patch missed register reverse for "ldr". Please hold it, I'll send v3.

-- 
Dmitry

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2015-03-15 19:06 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-20 12:36 [PATCH 2/2] ARM: l2c: Maintain CPU endianness for early resume function Dmitry Osipenko
2015-03-11 10:18 ` Thierry Reding
2015-03-11 13:12   ` Russell King - ARM Linux
2015-03-15 19:06   ` Dmitry Osipenko

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).