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From: Stephen Rothwell <sfr@canb.auug.org.au>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
	Paul Burton <paul.burton@imgtec.com>
Subject: linux-next: manual merge of the mips tree with Linus' tree
Date: Thu, 1 Oct 2015 11:13:19 +1000	[thread overview]
Message-ID: <20151001111319.52dd5f94@canb.auug.org.au> (raw)

Hi Ralf,

Today's linux-next merge of the mips tree got a conflict in:

  arch/mips/include/asm/mips-cm.h

between commit:

  7573b94e08ae ("MIPS: CM: Provide a function to map from CPU to VP ID.")

from Linus' tree and commit:

  3d04e4b34962 ("MIPS: Enable L2 prefetching for CM >= 2.5")

from the mips tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au

diff --cc arch/mips/include/asm/mips-cm.h
index 1f1927ab4269,36530fd8a9bf..000000000000
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@@ -194,7 -194,8 +194,9 @@@ BUILD_CM_RW(reg3_mask,		MIPS_CM_GCB_OF
  BUILD_CM_R_(gic_status,		MIPS_CM_GCB_OFS + 0xd0)
  BUILD_CM_R_(cpc_status,		MIPS_CM_GCB_OFS + 0xf0)
  BUILD_CM_RW(l2_config,		MIPS_CM_GCB_OFS + 0x130)
 +BUILD_CM_RW(sys_config2,	MIPS_CM_GCB_OFS + 0x150)
+ BUILD_CM_RW(l2_pft_control,	MIPS_CM_GCB_OFS + 0x300)
+ BUILD_CM_RW(l2_pft_control_b,	MIPS_CM_GCB_OFS + 0x308)
  
  /* Core Local & Core Other register accessor functions */
  BUILD_CM_Cx_RW(reset_release,	0x00)
@@@ -317,10 -319,20 +320,24 @@@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80
  #define CM_GCR_L2_CONFIG_ASSOC_SHF		0
  #define CM_GCR_L2_CONFIG_ASSOC_MSK		(_ULCAST_(0xff) << 0)
  
 +/* GCR_SYS_CONFIG2 register fields */
 +#define CM_GCR_SYS_CONFIG2_MAXVPW_SHF		0
 +#define CM_GCR_SYS_CONFIG2_MAXVPW_MSK		(_ULCAST_(0xf) << 0)
 +
+ /* GCR_L2_PFT_CONTROL register fields */
+ #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_SHF	12
+ #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK	(_ULCAST_(0xfffff) << 12)
+ #define CM_GCR_L2_PFT_CONTROL_PFTEN_SHF		8
+ #define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK		(_ULCAST_(0x1) << 8)
+ #define CM_GCR_L2_PFT_CONTROL_NPFT_SHF		0
+ #define CM_GCR_L2_PFT_CONTROL_NPFT_MSK		(_ULCAST_(0xff) << 0)
+ 
+ /* GCR_L2_PFT_CONTROL_B register fields */
+ #define CM_GCR_L2_PFT_CONTROL_B_CEN_SHF		8
+ #define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK		(_ULCAST_(0x1) << 8)
+ #define CM_GCR_L2_PFT_CONTROL_B_PORTID_SHF	0
+ #define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK	(_ULCAST_(0xff) << 0)
+ 
  /* GCR_Cx_COHERENCE register fields */
  #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF	0
  #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK	(_ULCAST_(0xff) << 0)

             reply	other threads:[~2015-10-01  1:13 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-01  1:13 Stephen Rothwell [this message]
  -- strict thread matches above, loose matches on Subject: below --
2020-05-25  0:05 Stephen Rothwell
2019-09-18 11:33 Mark Brown
2019-08-11 23:19 Stephen Rothwell
2019-08-07  0:25 Stephen Rothwell
2019-08-07  7:42 ` Arnd Bergmann
2019-05-12 23:47 Stephen Rothwell
2018-08-23 22:37 Stephen Rothwell
2017-07-11  0:04 Stephen Rothwell
2017-01-03  0:26 Stephen Rothwell
2016-01-24 22:25 Stephen Rothwell
2016-01-25  7:42 ` Ralf Baechle
2015-02-22  0:22 Stephen Rothwell
2015-02-22  0:15 Stephen Rothwell
2015-02-13  0:11 Stephen Rothwell
2015-02-13 10:28 ` Ralf Baechle
2014-06-03  0:50 Stephen Rothwell
2012-10-04  0:35 Stephen Rothwell
2012-10-01  3:58 Stephen Rothwell
2011-11-07  0:04 Stephen Rothwell
2011-11-07  0:04 Stephen Rothwell
2011-11-07 10:18 ` Ralf Baechle
2009-12-14 23:20 Stephen Rothwell
2009-12-15  7:26 ` Michal Simek
2009-12-15 19:27   ` Ralf Baechle
2009-08-18  8:23 Stephen Rothwell

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