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* [PATCH v6 00/11] Sunxi: Add SMP support on A83T
@ 2018-04-16 21:50 Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
                   ` (11 more replies)
  0 siblings, 12 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Hello everyone,

This is a V6 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files:
6c7dd080ba4b ("ARM: Allow this header to be included by assembly files")

This new series refactors the shmobile code to use the function introduced
in this series: "secure_cntvoff_init".
Geert Uytterhoeven and Simon Horman, could you review and test this series
on Renesas boards? Thank you very much!

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes since v5:
    - Remove my patch 01 and use the patch of Doug Berger to be able to
    include the cpu-type header on assembly files.
    - Rename smp_init_cntvoff function into secure_cntvoff_init according
    to Marc Zyngier's review.
    - According to Chen-Yu and Maxime's reviews, remove the patch that was
    moving structures. Instead of using an index to retrieve which
    architecture we are having, use a global variable.
    - Merge the 2 patches that move assembly code from C to assembly file.
    - Use a sun8i field instead of sun9i to know on which architecture we
    are using because many modifications/additions of the code are for
    sun8i-a83t.
    - Rework the patch "add is_sun8i field" to add only this field in this
    patch. The part of the patch that was starting to handle the differences
    between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
    support of sun8i-a83t.
    - Add a new patch that refactor the shmobile code to use the new function
    secure_cntvoff_init introduced in this series.

Changes since v4:
    - Rebased my series according to new Chen-Yu series:
       "ARM: sunxi: Clean and improvements for multi-cluster SMP"
       https://lkml.org/lkml/2018/3/8/886
    - Updated my series according to Marc Zyngier's reviews to add CNTVOFF
    initialization's function into ARM's common part. Thanks to that, other
    platforms such as Renesa can use this function.
    - For boot CPU, create a new machine to handle the CNTVOFF initialization
    using "init_early" callback.
Changes since v3:
    - Take into account Maxime's reviews:
	- split the first patch into 4 new patches: add sun9i device tree
	parsing, rename some variables, add a83t support and finally,
	add hotplug support.
	- Move the code of previous patch 07 (to disable CPU0 disabling)
	into hotplug support patch (see patch 04)
	- Remove the patch that added PRCM register because it is already
	available. Because of that, update the device tree parsing to use
	"sun8i-a83t-r-ccu".
	- Use a variable to know which SoC we currently have
    - Take into account Chen-Yu's reviews: create two iounmap functions
    to release the resources of the device tree parsing.
    - Take into account Marc's review: Update the code to initialize CNTVOFF
    register. As there is already assembly code in the driver, I decided
    to create an assembly file not to mix assembly and C code.
    For that, I create 3 new patches: move the current assembly code that
    handles the cluster cache enabling into a file, move the cpu_resume entry
    in this file and finally, add a new assembly entry to initialize the timer
    offset for boot CPU and secondary CPUs.

Changes since v2:
    - Rebased my modifications according to new Chen Yu's patch series
    that adds SMP support for sun9i-a80 (without MCPM).
    - Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
    and PRCM registers for more visibility.
    - The hotplug of CPU0 is currently not working (even after trying what
    Allwinner's code is doing) so remove the possibility of disabling
    this CPU. Created a new patch for it.

Changes since v1:
    - Add Chen Yu's patch in my series (see path 01)
    - Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
    Create two functions to separate the DT parsing of sun9i-a80 and
    sun8i-a83t.
    - Thanks to Maxime's review: order device tree's nodes according
    to physical addresses, remove unused label and fix registers' sizes.
    Update the commit log and commit title of my last patch (see
    patch 05).

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: sun9i: smp: Add is_sun8i field
  ARM: sun8i: smp: Add support for A83T
  ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
  ARM: shmobile: Convert file to use cntvoff

 arch/arm/boot/dts/sun8i-a83t.dtsi        |  59 ++++++++
 arch/arm/common/Makefile                 |   1 +
 arch/arm/common/secure_cntvoff.S         |  31 ++++
 arch/arm/include/asm/secure_cntvoff.h    |   8 ++
 arch/arm/mach-shmobile/common.h          |   1 -
 arch/arm/mach-shmobile/headsmp-apmu.S    |  22 +--
 arch/arm/mach-shmobile/setup-rcar-gen2.c |   3 +-
 arch/arm/mach-sunxi/Makefile             |   4 +-
 arch/arm/mach-sunxi/headsmp.S            |  81 +++++++++++
 arch/arm/mach-sunxi/mc_smp.c             | 240 +++++++++++++++++++------------
 arch/arm/mach-sunxi/sunxi.c              |  20 ++-
 11 files changed, 349 insertions(+), 121 deletions(-)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-17  3:12   ` Chen-Yu Tsai
                     ` (2 more replies)
  2018-04-16 21:50 ` [PATCH v6 02/11] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
                   ` (10 subsequent siblings)
  11 siblings, 3 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/Makefile  |  4 +--
 arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
 3 files changed, 85 insertions(+), 81 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..7f45071ae74a 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,3 @@
-CFLAGS_mc_smp.o	+= -march=armv7-a
-
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 000000000000..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ * Mylène Josserand <mylene.josserand@bootlin.com>
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/cputype.h>
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+	.arch	armv7-a
+	/*
+	 * Enable cluster-level coherency, in preparation for turning on the MMU.
+	 *
+	 * Also enable regional clock gating and L2 data latency settings for
+	 * Cortex-A15. These settings are from the vendor kernel.
+	 */
+	mrc	p15, 0, r1, c0, c0, 0
+	movw	r2, #(ARM_CPU_PART_MASK & 0xffff)
+	movt	r2, #(ARM_CPU_PART_MASK >> 16)
+	and	r1, r1, r2
+	movw	r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
+	movt	r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+	cmp	r1, r2
+	bne	not_a15
+
+	/* The following is Cortex-A15 specific */
+
+	/* ACTLR2: Enable CPU regional clock gates */
+	mrc p15, 1, r1, c15, c0, 4
+	orr r1, r1, #(0x1 << 31)
+	mcr p15, 1, r1, c15, c0, 4
+
+	/* L2ACTLR */
+	mrc p15, 1, r1, c15, c0, 0
+	/* Enable L2, GIC, and Timer regional clock gates */
+	orr r1, r1, #(0x1 << 26)
+	/* Disable clean/evict from being pushed to external */
+	orr r1, r1, #(0x1<<3)
+	mcr p15, 1, r1, c15, c0, 0
+
+	/* L2CTRL: L2 data RAM latency */
+	mrc p15, 1, r1, c9, c0, 2
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #(0x3 << 0)
+	mcr p15, 1, r1, c9, c0, 2
+
+	/* End of Cortex-A15 specific setup */
+	not_a15:
+
+	/* Get value of sunxi_mc_smp_first_comer */
+	adr	r1, first
+	ldr	r0, [r1]
+	ldr	r0, [r1, r0]
+
+	/* Skip cci_enable_port_for_self if not first comer */
+	cmp	r0, #0
+	bxeq	lr
+	b	cci_enable_port_for_self
+
+	.align 2
+	first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+	bl	sunxi_mc_smp_cluster_cache_enable
+	b	secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+	bl	sunxi_mc_smp_cluster_cache_enable
+	b	cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
 	struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-	asm volatile (
-		"mrc	p15, 0, r1, c0, c0, 0\n"
-		"movw	r2, #" __stringify(ARM_CPU_PART_MASK & 0xffff) "\n"
-		"movt	r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-		"and	r1, r1, r2\n"
-		"movw	r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0xffff) "\n"
-		"movt	r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
-		"cmp	r1, r2\n"
-		"bne	not_a15\n"
-
-		/* The following is Cortex-A15 specific */
-
-		/* ACTLR2: Enable CPU regional clock gates */
-		"mrc p15, 1, r1, c15, c0, 4\n"
-		"orr r1, r1, #(0x1<<31)\n"
-		"mcr p15, 1, r1, c15, c0, 4\n"
-
-		/* L2ACTLR */
-		"mrc p15, 1, r1, c15, c0, 0\n"
-		/* Enable L2, GIC, and Timer regional clock gates */
-		"orr r1, r1, #(0x1<<26)\n"
-		/* Disable clean/evict from being pushed to external */
-		"orr r1, r1, #(0x1<<3)\n"
-		"mcr p15, 1, r1, c15, c0, 0\n"
-
-		/* L2CTRL: L2 data RAM latency */
-		"mrc p15, 1, r1, c9, c0, 2\n"
-		"bic r1, r1, #(0x7<<0)\n"
-		"orr r1, r1, #(0x3<<0)\n"
-		"mcr p15, 1, r1, c9, c0, 2\n"
-
-		/* End of Cortex-A15 specific setup */
-		"not_a15:\n"
-
-		/* Get value of sunxi_mc_smp_first_comer */
-		"adr	r1, first\n"
-		"ldr	r0, [r1]\n"
-		"ldr	r0, [r1, r0]\n"
-
-		/* Skip cci_enable_port_for_self if not first comer */
-		"cmp	r0, #0\n"
-		"bxeq	lr\n"
-		"b	cci_enable_port_for_self\n"
-
-		".align 2\n"
-		"first: .word sunxi_mc_smp_first_comer - .\n"
-	);
-}
-
-static void __naked sunxi_mc_smp_secondary_startup(void)
-{
-	asm volatile(
-		"bl	sunxi_mc_smp_cluster_cache_enable\n"
-		"b	secondary_startup"
-		/* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
-		:: "i" (sunxi_mc_smp_cluster_cache_enable)
-	);
-}
+int sunxi_mc_smp_first_comer;
 
 static DEFINE_SPINLOCK(boot_lock);
 
@@ -637,16 +573,6 @@ static bool __init sunxi_mc_smp_cpu_table_init(void)
  */
 typedef typeof(cpu_reset) phys_reset_t;
 
-static void __init __naked sunxi_mc_smp_resume(void)
-{
-	asm volatile(
-		"bl	sunxi_mc_smp_cluster_cache_enable\n"
-		"b	cpu_resume"
-		/* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
-		:: "i" (sunxi_mc_smp_cluster_cache_enable)
-	);
-}
-
 static int __init nocache_trampoline(unsigned long __unused)
 {
 	phys_reset_t phys_reset;
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 02/11] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
                   ` (9 subsequent siblings)
  11 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 568307639be8..32992afa0b12 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
 			};
 		};
 
+		cpucfg@1700000 {
+			compatible = "allwinner,sun8i-a83t-cpucfg";
+			reg = <0x01700000 0x400>;
+		};
+
 		syscon: syscon@1c00000 {
 			compatible = "allwinner,sun8i-a83t-system-controller",
 				"syscon";
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 02/11] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-17  3:13   ` Chen-Yu Tsai
  2018-04-16 21:50 ` [PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
                   ` (8 subsequent siblings)
  11 siblings, 1 reply; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 32992afa0b12..7974eaba57a7 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -933,6 +933,11 @@
 			#reset-cells = <1>;
 		};
 
+		r_cpucfg@1f01c00 {
+			compatible = "allwinner,sun8i-a83t-r-cpucfg";
+			reg = <0x1f01c00 0x400>;
+		};
+
 		r_pio: pinctrl@1f02c00 {
 			compatible = "allwinner,sun8i-a83t-r-pinctrl";
 			reg = <0x01f02c00 0x400>;
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (2 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
                   ` (7 subsequent siblings)
  11 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7974eaba57a7..42539267e329 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <0>;
 		};
 
@@ -73,6 +74,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <1>;
 		};
 
@@ -80,6 +82,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <2>;
 		};
 
@@ -87,6 +90,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <3>;
 		};
 
@@ -96,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x100>;
 		};
 
@@ -103,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x101>;
 		};
 
@@ -110,6 +116,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x102>;
 		};
 
@@ -117,6 +124,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x103>;
 		};
 	};
@@ -354,6 +362,39 @@
 			reg = <0x01700000 0x400>;
 		};
 
+		cci@1790000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x01790000 0x10000>;
+			ranges = <0x0 0x01790000 0x10000>;
+
+			cci_control0: slave-if@4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control1: slave-if@5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		syscon: syscon@1c00000 {
 			compatible = "allwinner,sun8i-a83t-system-controller",
 				"syscon";
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (3 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-18  9:30   ` Geert Uytterhoeven
  2018-04-16 21:50 ` [PATCH v6 06/11] ARM: sunxi: " Mylène Josserand
                   ` (6 subsequent siblings)
  11 siblings, 1 reply; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/common/Makefile              |  1 +
 arch/arm/common/secure_cntvoff.S      | 31 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/secure_cntvoff.h |  8 ++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
 obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
+obj-$(CONFIG_SMP)		+= secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 CFLAGS_REMOVE_mcpm_entry.o	= -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index 000000000000..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(secure_cntvoff_init)
+	.arch	armv7-a
+	/*
+	 * CNTVOFF has to be initialized either from non-secure Hypervisor
+	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+	 * then it should be handled by the secure code
+	 */
+	cps	#MON_MODE
+	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
+	orr	r0, r1, #1
+	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
+	isb
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
+	isb
+	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
+	isb
+	cps	#SVC_MODE
+	ret	lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index 000000000000..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 06/11] ARM: sunxi: Add initialization of CNTVOFF
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (4 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
                   ` (5 subsequent siblings)
  11 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add the initialization of CNTVOFF for sun8i-a83t.

For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because of that, this function can't be called in SMP's early_initcall
function which is called after timer's init.

For secondary CPUs, add this function into secondary_startup
assembly entry.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/headsmp.S |  1 +
 arch/arm/mach-sunxi/sunxi.c   | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
index 37dc772701f3..32d76be98541 100644
--- a/arch/arm/mach-sunxi/headsmp.S
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
 
 ENTRY(sunxi_mc_smp_secondary_startup)
 	bl	sunxi_mc_smp_cluster_cache_enable
+	bl	secure_cntvoff_init
 	b	secondary_startup
 ENDPROC(sunxi_mc_smp_secondary_startup)
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..ddc439f6269b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/mach/arch.h>
+#include <asm/secure_cntvoff.h>
 
 static const char * const sunxi_board_dt_compat[] = {
 	"allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
 	"allwinner,sun8i-a23",
 	"allwinner,sun8i-a33",
-	"allwinner,sun8i-a83t",
 	"allwinner,sun8i-h2-plus",
 	"allwinner,sun8i-h3",
 	"allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
 	.dt_compat	= sun8i_board_dt_compat,
 MACHINE_END
 
+void __init sun8i_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+	secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_cntvoff_board_dt_compat[] = {
+	"allwinner,sun8i-a83t",
+	NULL,
+};
+
+DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")
+	.init_early	= sun8i_cntvoff_init,
+	.init_time	= sun6i_timer_init,
+	.dt_compat	= sun8i_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
 	"allwinner,sun9i-a80",
 	NULL,
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (5 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 06/11] ARM: sunxi: " Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-17  8:21   ` Sergei Shtylyov
  2018-04-16 21:50 ` [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field Mylène Josserand
                   ` (4 subsequent siblings)
  11 siblings, 1 reply; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

To prepare the support for sun8i-a83t, rename the variable name
that handles the power-off of clusters because it is different from
sun9i-a80 to sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)	BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL	0xf
 #define PRCM_PWROFF_GATING_REG(c)	(0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER	BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I	BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n)	BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)	(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG		0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
 	/* clear cluster power gate */
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
 	/* gate cluster power */
 	pr_debug("%s: gate cluster power\n", __func__);
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+	reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (6 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-17  7:52   ` Maxime Ripard
  2018-04-16 21:50 ` [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T Mylène Josserand
                   ` (3 subsequent siblings)
  11 siblings, 1 reply; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/mc_smp.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..9d57ea27dacc 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static int is_sun8i;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
 	const char *enable_method;
 	int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+	int is_sun8i;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -664,6 +666,7 @@ static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
 	{
 		.enable_method	= "allwinner,sun9i-a80-smp",
 		.get_smp_nodes	= sun9i_a80_get_smp_nodes,
+		.is_sun8i	= false,
 	},
 };
 
@@ -697,6 +700,8 @@ static int __init sunxi_mc_smp_init(void)
 			break;
 	}
 
+	is_sun8i = sunxi_mc_smp_data[i].is_sun8i;
+
 	of_node_put(node);
 	if (ret)
 		return -ENODEV;
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (7 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-17 11:20   ` Maxime Ripard
  2018-04-16 21:50 ` [PATCH v6 10/11] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
                   ` (2 subsequent siblings)
  11 siblings, 1 reply; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/mc_smp.c | 151 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 136 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 9d57ea27dacc..1ed2ab3a13b5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST	BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)	BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n)	BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL	(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)		(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)	BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL	0xf
 #define PRCM_PWROFF_GATING_REG(c)	(0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I	BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I	BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n)	BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)	(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG		0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)	(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)	BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG		0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC0	0xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC1	0x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
 	reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+	if (is_sun8i) {
+		/* assert cpu power-on reset */
+		reg  = readl(r_cpucfg_base +
+			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+		writel(reg, r_cpucfg_base +
+		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* Cortex-A7: hold L1 reset disable signal low */
 	if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
 		reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
 	/* open power switch */
 	sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+	/* Handle A83T bit swap */
+	if (is_sun8i) {
+		if (cpu == 0)
+			cpu = 4;
+	}
+
 	/* clear processor power gate */
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
+	/* Handle A83T bit swap */
+	if (is_sun8i) {
+		if (cpu == 4)
+			cpu = 0;
+	}
+
 	/* de-assert processor power-on reset */
 	reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 	reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+	if (is_sun8i) {
+		reg  = readl(r_cpucfg_base +
+			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+		writel(reg, r_cpucfg_base +
+		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* de-assert all processor resets */
 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
 	reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 	if (cluster >= SUNXI_NR_CLUSTERS)
 		return -EINVAL;
 
+	/* For A83T, assert cluster cores resets */
+	if (is_sun8i) {
+		reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+		reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;   /* Core Reset    */
+		writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* assert ACINACTM */
 	reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
 	reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
@@ -226,6 +274,16 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 	reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+	/* assert cluster cores resets */
+	if (is_sun8i) {
+		reg  = readl(r_cpucfg_base +
+			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
+		writel(reg, r_cpucfg_base +
+		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* assert cluster resets */
 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
 	reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
@@ -256,7 +314,10 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
 	/* clear cluster power gate */
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
+	if (is_sun8i)
+		reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
+	else
+		reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
@@ -453,7 +514,10 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
 	/* gate cluster power */
 	pr_debug("%s: gate cluster power\n", __func__);
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
+	if (is_sun8i)
+		reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
+	else
+		reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
@@ -535,8 +599,12 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
 	return !ret;
 }
 
-static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
+static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
 {
+	/* CPU0 hotplug not handled for sun8i-a83t */
+	if (is_sun8i)
+		if (cpu == 0)
+			return false;
 	return true;
 }
 #endif
@@ -619,6 +687,7 @@ struct sunxi_mc_smp_nodes {
 	struct device_node *prcm_node;
 	struct device_node *cpucfg_node;
 	struct device_node *sram_node;
+	struct device_node *r_cpucfg_node;
 };
 
 /* This structure holds SoC-specific bits tied to an enable-method string. */
@@ -633,6 +702,7 @@ static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
 	of_node_put(nodes->prcm_node);
 	of_node_put(nodes->cpucfg_node);
 	of_node_put(nodes->sram_node);
+	of_node_put(nodes->r_cpucfg_node);
 	memset(nodes, 0, sizeof(*nodes));
 }
 
@@ -662,12 +732,43 @@ static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
 	return 0;
 }
 
+static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
+{
+	nodes->prcm_node = of_find_compatible_node(NULL, NULL,
+						   "allwinner,sun8i-a83t-r-ccu");
+	if (!nodes->prcm_node) {
+		pr_err("%s: PRCM not available\n", __func__);
+		return -ENODEV;
+	}
+
+	nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
+						     "allwinner,sun8i-a83t-cpucfg");
+	if (!nodes->cpucfg_node) {
+		pr_err("%s: CPUCFG not available\n", __func__);
+		return -ENODEV;
+	}
+
+	nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
+						       "allwinner,sun8i-a83t-r-cpucfg");
+	if (!nodes->r_cpucfg_node) {
+		pr_err("%s: RCPUCFG not available\n", __func__);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
 static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
 	{
 		.enable_method	= "allwinner,sun9i-a80-smp",
 		.get_smp_nodes	= sun9i_a80_get_smp_nodes,
 		.is_sun8i	= false,
 	},
+	{
+		.enable_method	= "allwinner,sun8i-a83t-smp",
+		.get_smp_nodes	= sun8i_a83t_get_smp_nodes,
+		.is_sun8i	= true,
+	},
 };
 
 static int __init sunxi_mc_smp_init(void)
@@ -675,6 +776,7 @@ static int __init sunxi_mc_smp_init(void)
 	struct sunxi_mc_smp_nodes nodes = { 0 };
 	struct device_node *node;
 	struct resource res;
+	void __iomem *addr;
 	int i, ret;
 
 	/*
@@ -739,12 +841,23 @@ static int __init sunxi_mc_smp_init(void)
 		goto err_unmap_prcm;
 	}
 
-	sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
-						"sunxi-mc-smp");
-	if (IS_ERR(sram_b_smp_base)) {
-		ret = PTR_ERR(sram_b_smp_base);
-		pr_err("%s: failed to map secure SRAM\n", __func__);
-		goto err_unmap_release_cpucfg;
+	if (is_sun8i) {
+		r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
+						      0, "sunxi-mc-smp");
+		if (IS_ERR(r_cpucfg_base)) {
+			ret = PTR_ERR(r_cpucfg_base);
+			pr_err("%s: failed to map R-CPUCFG registers\n",
+			       __func__);
+			goto err_unmap_release_cpucfg;
+		}
+	} else {
+		sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
+							"sunxi-mc-smp");
+		if (IS_ERR(sram_b_smp_base)) {
+			ret = PTR_ERR(sram_b_smp_base);
+			pr_err("%s: failed to map secure SRAM\n", __func__);
+			goto err_unmap_release_cpucfg;
+		}
 	}
 
 	/* Configure CCI-400 for boot cluster */
@@ -752,15 +865,18 @@ static int __init sunxi_mc_smp_init(void)
 	if (ret) {
 		pr_err("%s: failed to configure boot cluster: %d\n",
 		       __func__, ret);
-		goto err_unmap_release_secure_sram;
+		goto err_unmap_release_sram_rcpucfg;
 	}
 
 	/* We don't need the device nodes anymore */
 	sunxi_mc_smp_put_nodes(&nodes);
 
 	/* Set the hardware entry point address */
-	writel(__pa_symbol(sunxi_mc_smp_secondary_startup),
-	       prcm_base + PRCM_CPU_SOFT_ENTRY_REG);
+	if (is_sun8i)
+		addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
+	else
+		addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
+	writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
 
 	/* Actually enable multi cluster SMP */
 	smp_set_ops(&sunxi_mc_smp_smp_ops);
@@ -769,9 +885,14 @@ static int __init sunxi_mc_smp_init(void)
 
 	return 0;
 
-err_unmap_release_secure_sram:
-	iounmap(sram_b_smp_base);
-	of_address_to_resource(nodes.sram_node, 0, &res);
+err_unmap_release_sram_rcpucfg:
+	if (is_sun8i) {
+		iounmap(r_cpucfg_base);
+		of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
+	} else {
+		iounmap(sram_b_smp_base);
+		of_address_to_resource(nodes.sram_node, 0, &res);
+	}
 	release_mem_region(res.start, resource_size(&res));
 err_unmap_release_cpucfg:
 	iounmap(cpucfg_base);
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 10/11] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (8 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-16 21:50 ` [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
  2018-04-17  2:15 ` [PATCH v6 00/11] Sunxi: Add SMP support on A83T Ondřej Jirman
  11 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 42539267e329..c9b60047b0b8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0>;
 		};
 
@@ -75,6 +76,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <1>;
 		};
 
@@ -83,6 +85,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <2>;
 		};
 
@@ -91,6 +94,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <3>;
 		};
 
@@ -101,6 +105,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x100>;
 		};
 
@@ -109,6 +114,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x101>;
 		};
 
@@ -117,6 +123,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x102>;
 		};
 
@@ -125,6 +132,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x103>;
 		};
 	};
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (9 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 10/11] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
@ 2018-04-16 21:50 ` Mylène Josserand
  2018-04-18  9:36   ` Geert Uytterhoeven
  2018-04-17  2:15 ` [PATCH v6 00/11] Sunxi: Add SMP support on A83T Ondřej Jirman
  11 siblings, 1 reply; 36+ messages in thread
From: Mylène Josserand @ 2018-04-16 21:50 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-shmobile/common.h          |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S    | 22 +---------------------
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index a8fa4f7e1f60..b77ad5b56895 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-ENTRY(shmobile_init_cntvoff)
-	/*
-	 * CNTVOFF has to be initialized either from non-secure Hypervisor
-	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-	 * then it should be handled by the secure code
-	 */
-	cps	#MON_MODE
-	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
-	orr	r0, r1, #1
-	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
-	instr_sync
-	mov	r0, #0
-	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
-	instr_sync
-	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
-	instr_sync
-	cps	#SVC_MODE
-	ret	lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-	bl	shmobile_init_cntvoff
+	bl	secure_cntvoff_init
 	b	secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
+#include <asm/secure_cntvoff.h>
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
 	void __iomem *base;
 	u32 freq;
 
-	shmobile_init_cntvoff();
+	secure_cntvoff_init();
 
 	if (of_machine_is_compatible("renesas,r8a7745") ||
 	    of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 00/11] Sunxi: Add SMP support on A83T
  2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (10 preceding siblings ...)
  2018-04-16 21:50 ` [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
@ 2018-04-17  2:15 ` Ondřej Jirman
  2018-04-18  5:50   ` Mylène Josserand
  11 siblings, 1 reply; 36+ messages in thread
From: Ondřej Jirman @ 2018-04-17  2:15 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm, devicetree, quentin.schulz,
	linux-kernel, linux-renesas-soc, clabbe.montjoie,
	thomas.petazzoni, linux-arm-kernel

Hello Mylène,

Please also add this:

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
        bool
        depends on SMP
-   default MACH_SUN9I
+ default MACH_SUN9I || MACH_SUN8I
        select ARM_CCI400_PORT_CTRL
        select ARM_CPU_SUSPEND

Because otherwise when I'm building kernel just for sun8i and I don't have sun9i
enabled, this new SMP code for A83T (which is sun8i) will not be built.

thank you,
  Ondrej

On Mon, Apr 16, 2018 at 11:50:21PM +0200, Mylène Josserand wrote:
> Hello everyone,
> 
> This is a V6 of my series that adds SMP support for Allwinner sun8i-a83t.
> Based on sunxi's tree, sunxi/for-next branch.
> Depends on a patch from Doug Berger that allows to include the "cpu-type"
> header on assembly files:
> 6c7dd080ba4b ("ARM: Allow this header to be included by assembly files")
> 
> This new series refactors the shmobile code to use the function introduced
> in this series: "secure_cntvoff_init".
> Geert Uytterhoeven and Simon Horman, could you review and test this series
> on Renesas boards? Thank you very much!
> 
> If you have any remarks/questions, let me know.
> Thank you in advance,
> Mylène
> 
> Changes since v5:
>     - Remove my patch 01 and use the patch of Doug Berger to be able to
>     include the cpu-type header on assembly files.
>     - Rename smp_init_cntvoff function into secure_cntvoff_init according
>     to Marc Zyngier's review.
>     - According to Chen-Yu and Maxime's reviews, remove the patch that was
>     moving structures. Instead of using an index to retrieve which
>     architecture we are having, use a global variable.
>     - Merge the 2 patches that move assembly code from C to assembly file.
>     - Use a sun8i field instead of sun9i to know on which architecture we
>     are using because many modifications/additions of the code are for
>     sun8i-a83t.
>     - Rework the patch "add is_sun8i field" to add only this field in this
>     patch. The part of the patch that was starting to handle the differences
>     between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
>     support of sun8i-a83t.
>     - Add a new patch that refactor the shmobile code to use the new function
>     secure_cntvoff_init introduced in this series.
> 
> Changes since v4:
>     - Rebased my series according to new Chen-Yu series:
>        "ARM: sunxi: Clean and improvements for multi-cluster SMP"
>        https://lkml.org/lkml/2018/3/8/886
>     - Updated my series according to Marc Zyngier's reviews to add CNTVOFF
>     initialization's function into ARM's common part. Thanks to that, other
>     platforms such as Renesa can use this function.
>     - For boot CPU, create a new machine to handle the CNTVOFF initialization
>     using "init_early" callback.
> Changes since v3:
>     - Take into account Maxime's reviews:
> 	- split the first patch into 4 new patches: add sun9i device tree
> 	parsing, rename some variables, add a83t support and finally,
> 	add hotplug support.
> 	- Move the code of previous patch 07 (to disable CPU0 disabling)
> 	into hotplug support patch (see patch 04)
> 	- Remove the patch that added PRCM register because it is already
> 	available. Because of that, update the device tree parsing to use
> 	"sun8i-a83t-r-ccu".
> 	- Use a variable to know which SoC we currently have
>     - Take into account Chen-Yu's reviews: create two iounmap functions
>     to release the resources of the device tree parsing.
>     - Take into account Marc's review: Update the code to initialize CNTVOFF
>     register. As there is already assembly code in the driver, I decided
>     to create an assembly file not to mix assembly and C code.
>     For that, I create 3 new patches: move the current assembly code that
>     handles the cluster cache enabling into a file, move the cpu_resume entry
>     in this file and finally, add a new assembly entry to initialize the timer
>     offset for boot CPU and secondary CPUs.
> 
> Changes since v2:
>     - Rebased my modifications according to new Chen Yu's patch series
>     that adds SMP support for sun9i-a80 (without MCPM).
>     - Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
>     and PRCM registers for more visibility.
>     - The hotplug of CPU0 is currently not working (even after trying what
>     Allwinner's code is doing) so remove the possibility of disabling
>     this CPU. Created a new patch for it.
> 
> Changes since v1:
>     - Add Chen Yu's patch in my series (see path 01)
>     - Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
>     Create two functions to separate the DT parsing of sun9i-a80 and
>     sun8i-a83t.
>     - Thanks to Maxime's review: order device tree's nodes according
>     to physical addresses, remove unused label and fix registers' sizes.
>     Update the commit log and commit title of my last patch (see
>     patch 05).
> 
> Mylène Josserand (11):
>   ARM: sunxi: smp: Move assembly code into a file
>   ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
>   ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
>   ARM: dts: sun8i: a83t: Add CCI-400 node
>   ARM: smp: Add initialization of CNTVOFF
>   ARM: sunxi: Add initialization of CNTVOFF
>   ARM: sun9i: smp: Rename clusters's power-off
>   ARM: sun9i: smp: Add is_sun8i field
>   ARM: sun8i: smp: Add support for A83T
>   ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
>   ARM: shmobile: Convert file to use cntvoff
> 
>  arch/arm/boot/dts/sun8i-a83t.dtsi        |  59 ++++++++
>  arch/arm/common/Makefile                 |   1 +
>  arch/arm/common/secure_cntvoff.S         |  31 ++++
>  arch/arm/include/asm/secure_cntvoff.h    |   8 ++
>  arch/arm/mach-shmobile/common.h          |   1 -
>  arch/arm/mach-shmobile/headsmp-apmu.S    |  22 +--
>  arch/arm/mach-shmobile/setup-rcar-gen2.c |   3 +-
>  arch/arm/mach-sunxi/Makefile             |   4 +-
>  arch/arm/mach-sunxi/headsmp.S            |  81 +++++++++++
>  arch/arm/mach-sunxi/mc_smp.c             | 240 +++++++++++++++++++------------
>  arch/arm/mach-sunxi/sunxi.c              |  20 ++-
>  11 files changed, 349 insertions(+), 121 deletions(-)
>  create mode 100644 arch/arm/common/secure_cntvoff.S
>  create mode 100644 arch/arm/include/asm/secure_cntvoff.h
>  create mode 100644 arch/arm/mach-sunxi/headsmp.S
> 
> -- 
> 2.11.0
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
@ 2018-04-17  3:12   ` Chen-Yu Tsai
  2018-04-17 11:17     ` Maxime Ripard
  2018-04-17  6:36   ` kbuild test robot
  2018-04-17 10:46   ` kbuild test robot
  2 siblings, 1 reply; 36+ messages in thread
From: Chen-Yu Tsai @ 2018-04-17  3:12 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: Russell King, Maxime Ripard, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
<mylene.josserand@bootlin.com> wrote:
> Move the assembly code for cluster cache enabling and resuming
> into an assembly file instead of having it directly in C code.
>
> Remove the CFLAGS because we are using the ARM directive "arch"
> instead.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> ---
>  arch/arm/mach-sunxi/Makefile  |  4 +--
>  arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
>  3 files changed, 85 insertions(+), 81 deletions(-)
>  create mode 100644 arch/arm/mach-sunxi/headsmp.S

I'm still not convinced about this whole "move ASM to separate
file" thing, especially now that you aren't actually adding any
sunxi-specific ASM code beyond a simple function call.

Could you drop this for now?

ChenYu

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  2018-04-16 21:50 ` [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
@ 2018-04-17  3:13   ` Chen-Yu Tsai
  0 siblings, 0 replies; 36+ messages in thread
From: Chen-Yu Tsai @ 2018-04-17  3:13 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: Russell King, Maxime Ripard, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
<mylene.josserand@bootlin.com> wrote:
> The R_CPUCFG is a collection of registers needed for SMP bringup
> on clusters and cluster's reset.
> For the moment, documentation about this register is found in
> Allwinner's code only.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
  2018-04-17  3:12   ` Chen-Yu Tsai
@ 2018-04-17  6:36   ` kbuild test robot
  2018-04-17 10:46   ` kbuild test robot
  2 siblings, 0 replies; 36+ messages in thread
From: kbuild test robot @ 2018-04-17  6:36 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: kbuild-all, linux, maxime.ripard, wens, marc.zyngier,
	mark.rutland, robh+dt, horms, geert, magnus.damm,
	linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

[-- Attachment #1: Type: text/plain, Size: 21007 bytes --]

Hi Mylène,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on arm-soc/for-next]
[also build test ERROR on v4.17-rc1 next-20180416]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Myl-ne-Josserand/Sunxi-Add-SMP-support-on-A83T/20180417-113911
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git for-next
config: arm-sunxi_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   include/asm-generic/bitops/sched.h:14: Error: junk at end of line, first unrecognized character is `{'
   include/asm-generic/bitops/sched.h:20: Error: bad instruction `if (b[0])'
   include/asm-generic/bitops/sched.h:21: Error: bad instruction `return __ffs(b[0])'
   include/asm-generic/bitops/sched.h:22: Error: bad instruction `if (b[1])'
   include/asm-generic/bitops/sched.h:23: Error: bad instruction `return __ffs(b[1])+32'
   include/asm-generic/bitops/sched.h:24: Error: bad instruction `if (b[2])'
   include/asm-generic/bitops/sched.h:25: Error: bad instruction `return __ffs(b[2])+64'
   include/asm-generic/bitops/sched.h:26: Error: bad instruction `return __ffs(b[3])+96'
   include/asm-generic/bitops/sched.h:30: Error: junk at end of line, first unrecognized character is `}'
   include/asm-generic/bitops/arch_hweight.h:7: Error: bad instruction `static inline unsigned int __arch_hweight32(unsigned int w)'
   include/asm-generic/bitops/arch_hweight.h:8: Error: junk at end of line, first unrecognized character is `{'
   include/asm-generic/bitops/arch_hweight.h:9: Error: bad instruction `return __sw_hweight32(w)'
   include/asm-generic/bitops/arch_hweight.h:10: Error: junk at end of line, first unrecognized character is `}'
   include/asm-generic/bitops/arch_hweight.h:12: Error: bad instruction `static inline unsigned int __arch_hweight16(unsigned int w)'
   include/asm-generic/bitops/arch_hweight.h:13: Error: junk at end of line, first unrecognized character is `{'
   include/asm-generic/bitops/arch_hweight.h:14: Error: bad instruction `return __sw_hweight16(w)'
   include/asm-generic/bitops/arch_hweight.h:15: Error: junk at end of line, first unrecognized character is `}'
   include/asm-generic/bitops/arch_hweight.h:17: Error: bad instruction `static inline unsigned int __arch_hweight8(unsigned int w)'
   include/asm-generic/bitops/arch_hweight.h:18: Error: junk at end of line, first unrecognized character is `{'
   include/asm-generic/bitops/arch_hweight.h:19: Error: bad instruction `return __sw_hweight8(w)'
   include/asm-generic/bitops/arch_hweight.h:20: Error: junk at end of line, first unrecognized character is `}'
   include/asm-generic/bitops/arch_hweight.h:22: Error: bad instruction `static inline unsigned long __arch_hweight64(__u64 w)'
   include/asm-generic/bitops/arch_hweight.h:23: Error: junk at end of line, first unrecognized character is `{'
   include/asm-generic/bitops/arch_hweight.h:24: Error: bad instruction `return __sw_hweight64(w)'
   include/asm-generic/bitops/arch_hweight.h:25: Error: junk at end of line, first unrecognized character is `}'
   include/asm-generic/bitops/find.h:30: Error: bad instruction `extern unsigned long find_next_and_bit(const unsigned long*addr1,'
   include/asm-generic/bitops/find.h:31: Error: bad instruction `const unsigned long*addr2,unsigned long size,'
   include/asm-generic/bitops/find.h:32: Error: bad instruction `unsigned long offset)'
   arch/arm/include/asm/swab.h:23: Error: bad instruction `static inline __u32 __arch_swahb32(__u32 x)'
   arch/arm/include/asm/swab.h:24: Error: junk at end of line, first unrecognized character is `{'
   arch/arm/include/asm/swab.h:25: Error: bad instruction `__asm__ ("rev16 %0, %1":"=r"(x):"r"(x))'
   arch/arm/include/asm/swab.h:26: Error: bad instruction `return x'
   arch/arm/include/asm/swab.h:27: Error: junk at end of line, first unrecognized character is `}'
   arch/arm/include/asm/swab.h:31: Error: bad instruction `static inline __u32 __arch_swab32(__u32 x)'
   arch/arm/include/asm/swab.h:32: Error: junk at end of line, first unrecognized character is `{'
   arch/arm/include/asm/swab.h:33: Error: bad instruction `__asm__ ("rev %0, %1":"=r"(x):"r"(x))'
   arch/arm/include/asm/swab.h:34: Error: bad instruction `return x'
   arch/arm/include/asm/swab.h:35: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:47: Error: bad instruction `static inline __u16 __fswab16(__u16 val)'
   include/uapi/linux/swab.h:48: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:50: Error: bad instruction `return ((__u16)__arch_swahb32(val))'
   include/uapi/linux/swab.h:54: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:56: Error: bad instruction `static inline __u32 __fswab32(__u32 val)'
   include/uapi/linux/swab.h:57: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:59: Error: bad instruction `return __arch_swab32(val)'
   include/uapi/linux/swab.h:63: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:65: Error: bad instruction `static inline __u64 __fswab64(__u64 val)'
   include/uapi/linux/swab.h:66: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:70: Error: bad instruction `__u32 h=val>>32'
   include/uapi/linux/swab.h:71: Error: bad instruction `__u32 l=val&((1ULL<<32)-1)'
   include/uapi/linux/swab.h:72: Error: bad instruction `return (((__u64)__fswab32(l))<<32)|((__u64)(__fswab32(h)))'
   include/uapi/linux/swab.h:76: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:78: Error: bad instruction `static inline __u32 __fswahw32(__u32 val)'
   include/uapi/linux/swab.h:79: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:83: Error: bad instruction `return ((__u32)((((__u32)(val)&(__u32)0x0000ffffUL)<<16)|(((__u32)(val)&(__u32)0xffff0000UL)>>16)))'
   include/uapi/linux/swab.h:85: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:87: Error: bad instruction `static inline __u32 __fswahb32(__u32 val)'
   include/uapi/linux/swab.h:88: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:90: Error: bad instruction `return __arch_swahb32(val)'
   include/uapi/linux/swab.h:94: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:161: Error: bad instruction `static inline __u16 __swab16p(const __u16*p)'
   include/uapi/linux/swab.h:162: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:166: Error: bad instruction `return (__builtin_constant_p((__u16)(*p))?((__u16)((((__u16)(*p)&(__u16)0x00ffU)<<8)|(((__u16)(*p)&(__u16)0xff00U)>>8))):__fswab16(*p))'
   include/uapi/linux/swab.h:168: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:174: Error: bad instruction `static inline __u32 __swab32p(const __u32*p)'
   include/uapi/linux/swab.h:175: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:179: Error: bad instruction `return (__builtin_constant_p((__u32)(*p))?((__u32)((((__u32)(*p)&(__u32)0x000000ffUL)<<24)|(((__u32)(*p)&(__u32)0x0000ff00UL)<<8)|(((__u32)(*p)&(__u32)0x00ff0000UL)>>8)|(((__u32)(*p)&(__u32)0xff000000UL)>>24))):__fswab32(*p))'
   include/uapi/linux/swab.h:181: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:187: Error: bad instruction `static inline __u64 __swab64p(const __u64*p)'
   include/uapi/linux/swab.h:188: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:192: Error: bad instruction `return (__builtin_constant_p((__u64)(*p))?((__u64)((((__u64)(*p)&(__u64)0x00000000000000ffULL)<<56)|(((__u64)(*p)&(__u64)0x000000000000ff00ULL)<<40)|(((__u64)(*p)&(__u64)0x0000000000ff0000ULL)<<24)|(((__u64)(*p)&(__u64)0x00000000ff000000ULL)<<8)|(((__u64)(*p)&(__u64)0x000000ff00000000ULL)>>8)|(((__u64)(*p)&(__u64)0x0000ff0000000000ULL)>>24)|(((__u64)(*p)&(__u64)0x00ff000000000000ULL)>>40)|(((__u64)(*p)&(__u64)0xff00000000000000ULL)>>56))):__fswab64(*p))'
   include/uapi/linux/swab.h:194: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:202: Error: bad instruction `static inline __u32 __swahw32p(const __u32*p)'
   include/uapi/linux/swab.h:203: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:207: Error: bad instruction `return (__builtin_constant_p((__u32)(*p))?((__u32)((((__u32)(*p)&(__u32)0x0000ffffUL)<<16)|(((__u32)(*p)&(__u32)0xffff0000UL)>>16))):__fswahw32(*p))'
   include/uapi/linux/swab.h:209: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:217: Error: bad instruction `static inline __u32 __swahb32p(const __u32*p)'
   include/uapi/linux/swab.h:218: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:222: Error: bad instruction `return (__builtin_constant_p((__u32)(*p))?((__u32)((((__u32)(*p)&(__u32)0x00ff00ffUL)<<8)|(((__u32)(*p)&(__u32)0xff00ff00UL)>>8))):__fswahb32(*p))'
   include/uapi/linux/swab.h:224: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:230: Error: bad instruction `static inline void __swab16s(__u16*p)'
   include/uapi/linux/swab.h:231: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:235: Error: junk at end of line, first unrecognized character is `*'
   include/uapi/linux/swab.h:237: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:242: Error: bad instruction `static inline void __swab32s(__u32*p)'
   include/uapi/linux/swab.h:243: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:247: Error: junk at end of line, first unrecognized character is `*'
   include/uapi/linux/swab.h:249: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:255: Error: bad instruction `static inline void __swab64s(__u64*p)'
   include/uapi/linux/swab.h:256: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:260: Error: junk at end of line, first unrecognized character is `*'
   include/uapi/linux/swab.h:262: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:270: Error: bad instruction `static inline void __swahw32s(__u32*p)'
   include/uapi/linux/swab.h:271: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:275: Error: junk at end of line, first unrecognized character is `*'
   include/uapi/linux/swab.h:277: Error: junk at end of line, first unrecognized character is `}'
   include/uapi/linux/swab.h:285: Error: bad instruction `static inline void __swahb32s(__u32*p)'
   include/uapi/linux/swab.h:286: Error: junk at end of line, first unrecognized character is `{'
   include/uapi/linux/swab.h:290: Error: junk at end of line, first unrecognized character is `*'
   include/uapi/linux/swab.h:292: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:44: Error: bad instruction `static inline __le64 __cpu_to_le64p(const __u64*p)'
>> include/uapi/linux/byteorder/little_endian.h:45: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:46: Error: bad instruction `return (__force __le64)*p'
   include/uapi/linux/byteorder/little_endian.h:47: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:48: Error: bad instruction `static inline __u64 __le64_to_cpup(const __le64*p)'
   include/uapi/linux/byteorder/little_endian.h:49: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:50: Error: bad instruction `return (__force __u64)*p'
   include/uapi/linux/byteorder/little_endian.h:51: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:52: Error: bad instruction `static inline __le32 __cpu_to_le32p(const __u32*p)'
   include/uapi/linux/byteorder/little_endian.h:53: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:54: Error: bad instruction `return (__force __le32)*p'
   include/uapi/linux/byteorder/little_endian.h:55: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:56: Error: bad instruction `static inline __u32 __le32_to_cpup(const __le32*p)'
   include/uapi/linux/byteorder/little_endian.h:57: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:58: Error: bad instruction `return (__force __u32)*p'
   include/uapi/linux/byteorder/little_endian.h:59: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:60: Error: bad instruction `static inline __le16 __cpu_to_le16p(const __u16*p)'
   include/uapi/linux/byteorder/little_endian.h:61: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:62: Error: bad instruction `return (__force __le16)*p'
   include/uapi/linux/byteorder/little_endian.h:63: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:64: Error: bad instruction `static inline __u16 __le16_to_cpup(const __le16*p)'
   include/uapi/linux/byteorder/little_endian.h:65: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:66: Error: bad instruction `return (__force __u16)*p'
   include/uapi/linux/byteorder/little_endian.h:67: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:68: Error: bad instruction `static inline __be64 __cpu_to_be64p(const __u64*p)'
   include/uapi/linux/byteorder/little_endian.h:69: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:70: Error: bad instruction `return (__force __be64)__swab64p(p)'
   include/uapi/linux/byteorder/little_endian.h:71: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:72: Error: bad instruction `static inline __u64 __be64_to_cpup(const __be64*p)'
   include/uapi/linux/byteorder/little_endian.h:73: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:74: Error: bad instruction `return __swab64p((__u64*)p)'
   include/uapi/linux/byteorder/little_endian.h:75: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:76: Error: bad instruction `static inline __be32 __cpu_to_be32p(const __u32*p)'
   include/uapi/linux/byteorder/little_endian.h:77: Error: junk at end of line, first unrecognized character is `{'
>> include/uapi/linux/byteorder/little_endian.h:78: Error: bad instruction `return (__force __be32)__swab32p(p)'
   include/uapi/linux/byteorder/little_endian.h:79: Error: junk at end of line, first unrecognized character is `}'
>> include/uapi/linux/byteorder/little_endian.h:80: Error: bad instruction `static inline __u32 __be32_to_cpup(const __be32*p)'
   include/uapi/linux/byteorder/little_endian.h:81: Error: junk at end of line, first unrecognized character is `{'

vim +44 include/uapi/linux/byteorder/little_endian.h

5921e6f8 David Howells  2012-10-13   43  
bc27fb68 Denys Vlasenko 2016-03-17  @44  static __always_inline __le64 __cpu_to_le64p(const __u64 *p)
5921e6f8 David Howells  2012-10-13  @45  {
5921e6f8 David Howells  2012-10-13  @46  	return (__force __le64)*p;
5921e6f8 David Howells  2012-10-13  @47  }
bc27fb68 Denys Vlasenko 2016-03-17  @48  static __always_inline __u64 __le64_to_cpup(const __le64 *p)
5921e6f8 David Howells  2012-10-13  @49  {
5921e6f8 David Howells  2012-10-13  @50  	return (__force __u64)*p;
5921e6f8 David Howells  2012-10-13  @51  }
bc27fb68 Denys Vlasenko 2016-03-17  @52  static __always_inline __le32 __cpu_to_le32p(const __u32 *p)
5921e6f8 David Howells  2012-10-13  @53  {
5921e6f8 David Howells  2012-10-13  @54  	return (__force __le32)*p;
5921e6f8 David Howells  2012-10-13  @55  }
bc27fb68 Denys Vlasenko 2016-03-17  @56  static __always_inline __u32 __le32_to_cpup(const __le32 *p)
5921e6f8 David Howells  2012-10-13  @57  {
5921e6f8 David Howells  2012-10-13  @58  	return (__force __u32)*p;
5921e6f8 David Howells  2012-10-13  @59  }
bc27fb68 Denys Vlasenko 2016-03-17  @60  static __always_inline __le16 __cpu_to_le16p(const __u16 *p)
5921e6f8 David Howells  2012-10-13  @61  {
5921e6f8 David Howells  2012-10-13  @62  	return (__force __le16)*p;
5921e6f8 David Howells  2012-10-13  @63  }
bc27fb68 Denys Vlasenko 2016-03-17  @64  static __always_inline __u16 __le16_to_cpup(const __le16 *p)
5921e6f8 David Howells  2012-10-13  @65  {
5921e6f8 David Howells  2012-10-13  @66  	return (__force __u16)*p;
5921e6f8 David Howells  2012-10-13  @67  }
bc27fb68 Denys Vlasenko 2016-03-17  @68  static __always_inline __be64 __cpu_to_be64p(const __u64 *p)
5921e6f8 David Howells  2012-10-13  @69  {
5921e6f8 David Howells  2012-10-13  @70  	return (__force __be64)__swab64p(p);
5921e6f8 David Howells  2012-10-13  @71  }
bc27fb68 Denys Vlasenko 2016-03-17  @72  static __always_inline __u64 __be64_to_cpup(const __be64 *p)
5921e6f8 David Howells  2012-10-13  @73  {
5921e6f8 David Howells  2012-10-13  @74  	return __swab64p((__u64 *)p);
5921e6f8 David Howells  2012-10-13  @75  }
bc27fb68 Denys Vlasenko 2016-03-17  @76  static __always_inline __be32 __cpu_to_be32p(const __u32 *p)
5921e6f8 David Howells  2012-10-13  @77  {
5921e6f8 David Howells  2012-10-13  @78  	return (__force __be32)__swab32p(p);
5921e6f8 David Howells  2012-10-13  @79  }
bc27fb68 Denys Vlasenko 2016-03-17  @80  static __always_inline __u32 __be32_to_cpup(const __be32 *p)
5921e6f8 David Howells  2012-10-13  @81  {
5921e6f8 David Howells  2012-10-13  @82  	return __swab32p((__u32 *)p);
5921e6f8 David Howells  2012-10-13   83  }
bc27fb68 Denys Vlasenko 2016-03-17  @84  static __always_inline __be16 __cpu_to_be16p(const __u16 *p)
5921e6f8 David Howells  2012-10-13   85  {
5921e6f8 David Howells  2012-10-13  @86  	return (__force __be16)__swab16p(p);
5921e6f8 David Howells  2012-10-13   87  }
bc27fb68 Denys Vlasenko 2016-03-17  @88  static __always_inline __u16 __be16_to_cpup(const __be16 *p)
5921e6f8 David Howells  2012-10-13   89  {
5921e6f8 David Howells  2012-10-13  @90  	return __swab16p((__u16 *)p);
5921e6f8 David Howells  2012-10-13   91  }
5921e6f8 David Howells  2012-10-13   92  #define __cpu_to_le64s(x) do { (void)(x); } while (0)
5921e6f8 David Howells  2012-10-13   93  #define __le64_to_cpus(x) do { (void)(x); } while (0)
5921e6f8 David Howells  2012-10-13   94  #define __cpu_to_le32s(x) do { (void)(x); } while (0)
5921e6f8 David Howells  2012-10-13   95  #define __le32_to_cpus(x) do { (void)(x); } while (0)
5921e6f8 David Howells  2012-10-13   96  #define __cpu_to_le16s(x) do { (void)(x); } while (0)
5921e6f8 David Howells  2012-10-13   97  #define __le16_to_cpus(x) do { (void)(x); } while (0)
5921e6f8 David Howells  2012-10-13   98  #define __cpu_to_be64s(x) __swab64s((x))
5921e6f8 David Howells  2012-10-13   99  #define __be64_to_cpus(x) __swab64s((x))
5921e6f8 David Howells  2012-10-13  100  #define __cpu_to_be32s(x) __swab32s((x))
5921e6f8 David Howells  2012-10-13  101  #define __be32_to_cpus(x) __swab32s((x))
5921e6f8 David Howells  2012-10-13  102  #define __cpu_to_be16s(x) __swab16s((x))
5921e6f8 David Howells  2012-10-13  103  #define __be16_to_cpus(x) __swab16s((x))
5921e6f8 David Howells  2012-10-13  104  
5921e6f8 David Howells  2012-10-13  105  

:::::: The code at line 44 was first introduced by commit
:::::: bc27fb68aaad44dd8f5c34924f05721f0abaeec1 include/uapi/linux/byteorder, swab: force inlining of some byteswap operations

:::::: TO: Denys Vlasenko <dvlasenk@redhat.com>
:::::: CC: Linus Torvalds <torvalds@linux-foundation.org>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field
  2018-04-16 21:50 ` [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field Mylène Josserand
@ 2018-04-17  7:52   ` Maxime Ripard
  2018-04-17  7:57     ` Chen-Yu Tsai
  0 siblings, 1 reply; 36+ messages in thread
From: Maxime Ripard @ 2018-04-17  7:52 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 2215 bytes --]

Hi,

On Mon, Apr 16, 2018 at 11:50:29PM +0200, Mylène Josserand wrote:
> To prepare the support of sun8i-a83t, add a field in the smp_data
> structure to know if we are on sun9i-a80 or sun8i-a83t.
> 
> Add also a global variable to retrieve which architecture we are
> having.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> ---
>  arch/arm/mach-sunxi/mc_smp.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
> index 03f021d0c73e..9d57ea27dacc 100644
> --- a/arch/arm/mach-sunxi/mc_smp.c
> +++ b/arch/arm/mach-sunxi/mc_smp.c
> @@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
>  
>  extern void sunxi_mc_smp_secondary_startup(void);
>  extern void sunxi_mc_smp_resume(void);
> +static int is_sun8i;
>  
>  static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
>  {
> @@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
>  struct sunxi_mc_smp_data {
>  	const char *enable_method;
>  	int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
> +	int is_sun8i;
>  };
>  
>  static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
> @@ -664,6 +666,7 @@ static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
>  	{
>  		.enable_method	= "allwinner,sun9i-a80-smp",
>  		.get_smp_nodes	= sun9i_a80_get_smp_nodes,
> +		.is_sun8i	= false,

I'm still not convinced about the name of that flag. sun8i doesn't
mean anything, really. What you want to discriminate against it what
you're writing in your commit log: if it is an A80 or an A83t. The
A33, H3, A23, you name it are also part of the sun8i family, yet they
are completely irrelevant to this file.

Also, false is the default value, you can leave it out.

>  	},
>  };
>  
> @@ -697,6 +700,8 @@ static int __init sunxi_mc_smp_init(void)
>  			break;
>  	}
>  
> +	is_sun8i = sunxi_mc_smp_data[i].is_sun8i;
> +

Do we really need to cache it? Can't we just have a pointer to the SMP
data structure and use that instead?

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field
  2018-04-17  7:52   ` Maxime Ripard
@ 2018-04-17  7:57     ` Chen-Yu Tsai
  2018-04-17 11:19       ` Maxime Ripard
  0 siblings, 1 reply; 36+ messages in thread
From: Chen-Yu Tsai @ 2018-04-17  7:57 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Mylène Josserand, Russell King, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

On Tue, Apr 17, 2018 at 3:52 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> Hi,
>
> On Mon, Apr 16, 2018 at 11:50:29PM +0200, Mylène Josserand wrote:
>> To prepare the support of sun8i-a83t, add a field in the smp_data
>> structure to know if we are on sun9i-a80 or sun8i-a83t.
>>
>> Add also a global variable to retrieve which architecture we are
>> having.
>>
>> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
>> ---
>>  arch/arm/mach-sunxi/mc_smp.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
>> index 03f021d0c73e..9d57ea27dacc 100644
>> --- a/arch/arm/mach-sunxi/mc_smp.c
>> +++ b/arch/arm/mach-sunxi/mc_smp.c
>> @@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
>>
>>  extern void sunxi_mc_smp_secondary_startup(void);
>>  extern void sunxi_mc_smp_resume(void);
>> +static int is_sun8i;
>>
>>  static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
>>  {
>> @@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
>>  struct sunxi_mc_smp_data {
>>       const char *enable_method;
>>       int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
>> +     int is_sun8i;
>>  };
>>
>>  static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
>> @@ -664,6 +666,7 @@ static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
>>       {
>>               .enable_method  = "allwinner,sun9i-a80-smp",
>>               .get_smp_nodes  = sun9i_a80_get_smp_nodes,
>> +             .is_sun8i       = false,
>
> I'm still not convinced about the name of that flag. sun8i doesn't
> mean anything, really. What you want to discriminate against it what
> you're writing in your commit log: if it is an A80 or an A83t. The
> A33, H3, A23, you name it are also part of the sun8i family, yet they
> are completely irrelevant to this file.
>
> Also, false is the default value, you can leave it out.
>
>>       },
>>  };
>>
>> @@ -697,6 +700,8 @@ static int __init sunxi_mc_smp_init(void)
>>                       break;
>>       }
>>
>> +     is_sun8i = sunxi_mc_smp_data[i].is_sun8i;
>> +
>
> Do we really need to cache it? Can't we just have a pointer to the SMP
> data structure and use that instead?

I recommended that. We don't need any of the other fields in the SMP
data structure once we're past the init phase. This saves a dereference
or two.

ChenYu

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off
  2018-04-16 21:50 ` [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
@ 2018-04-17  8:21   ` Sergei Shtylyov
  2018-04-18  5:51     ` Mylène Josserand
  0 siblings, 1 reply; 36+ messages in thread
From: Sergei Shtylyov @ 2018-04-17  8:21 UTC (permalink / raw)
  To: Mylène Josserand, linux, maxime.ripard, wens, marc.zyngier,
	mark.rutland, robh+dt, horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel

Hello!

On 4/17/2018 12:50 AM, Mylène Josserand wrote:

> To prepare the support for sun8i-a83t, rename the variable name

    s/variable/macro/ maybe? Also "rename the ... name" sounds tautological...

> that handles the power-off of clusters because it is different from
> sun9i-a80 to sun8i-a83t.
> 
> The power off register for clusters are different from a80 and a83t.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> ---
>   arch/arm/mach-sunxi/mc_smp.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
> index 727968d6a3e5..03f021d0c73e 100644
> --- a/arch/arm/mach-sunxi/mc_smp.c
> +++ b/arch/arm/mach-sunxi/mc_smp.c
> @@ -60,7 +60,7 @@
>   #define PRCM_CPU_PO_RST_CTRL_CORE(n)	BIT(n)
>   #define PRCM_CPU_PO_RST_CTRL_CORE_ALL	0xf
>   #define PRCM_PWROFF_GATING_REG(c)	(0x100 + 0x4 * (c))
> -#define PRCM_PWROFF_GATING_REG_CLUSTER	BIT(4)
> +#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I	BIT(4)
>   #define PRCM_PWROFF_GATING_REG_CORE(n)	BIT(n)
>   #define PRCM_PWR_SWITCH_REG(c, cpu)	(0x140 + 0x10 * (c) + 0x4 * (cpu))
>   #define PRCM_CPU_SOFT_ENTRY_REG		0x164
> @@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
>   
>   	/* clear cluster power gate */
>   	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
> -	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
> +	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
>   	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
>   	udelay(20);
>   
> @@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
>   	/* gate cluster power */
>   	pr_debug("%s: gate cluster power\n", __func__);
>   	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
> -	reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
> +	reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
>   	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
>   	udelay(20);
>   

MBR, Sergei

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
  2018-04-17  3:12   ` Chen-Yu Tsai
  2018-04-17  6:36   ` kbuild test robot
@ 2018-04-17 10:46   ` kbuild test robot
  2 siblings, 0 replies; 36+ messages in thread
From: kbuild test robot @ 2018-04-17 10:46 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: kbuild-all, linux, maxime.ripard, wens, marc.zyngier,
	mark.rutland, robh+dt, horms, geert, magnus.damm,
	linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

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Hi Mylène,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on arm-soc/for-next]
[also build test ERROR on v4.17-rc1 next-20180417]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Myl-ne-Josserand/Sunxi-Add-SMP-support-on-A83T/20180417-113911
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git for-next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All error/warnings (new ones prefixed by >>):

   In file included from arch/arm/include/asm/cputype.h:6:0,
                    from arch/arm/mach-sunxi/headsmp.S:15:
>> include/linux/kernel.h:57:0: warning: "ALIGN" redefined
    #define ALIGN(x, a)  __ALIGN_KERNEL((x), (a))
    
   In file included from arch/arm/mach-sunxi/headsmp.S:13:0:
   include/linux/linkage.h:79:0: note: this is the location of the previous definition
    #define ALIGN __ALIGN
    
   /usr/lib/gcc-cross/arm-linux-gnueabi/7/include/stdarg.h: Assembler messages:
>> /usr/lib/gcc-cross/arm-linux-gnueabi/7/include/stdarg.h:40: Error: bad instruction `typedef __builtin_va_list __gnuc_va_list'
>> /usr/lib/gcc-cross/arm-linux-gnueabi/7/include/stdarg.h:99: Error: bad instruction `typedef __gnuc_va_list va_list'
>> include/linux/stddef.h:10: Error: bad instruction `enum {'
>> include/linux/stddef.h:11: Error: junk at end of line, first unrecognized character is `,'
   include/linux/stddef.h:13: Error: junk at end of line, first unrecognized character is `}'
>> include/linux/bitops.h:29: Error: bad instruction `extern unsigned int __sw_hweight8(unsigned int w)'
>> include/linux/bitops.h:30: Error: bad instruction `extern unsigned int __sw_hweight16(unsigned int w)'
>> include/linux/bitops.h:31: Error: bad instruction `extern unsigned int __sw_hweight32(unsigned int w)'
>> include/linux/bitops.h:32: Error: bad instruction `extern unsigned long __sw_hweight64(__u64 w)'
>> arch/arm/include/asm/irqflags.h:25: Error: bad instruction `static inline unsigned long arch_local_irq_save(void)'
>> arch/arm/include/asm/irqflags.h:26: Error: junk at end of line, first unrecognized character is `{'
>> arch/arm/include/asm/irqflags.h:27: Error: bad instruction `unsigned long flags'
>> arch/arm/include/asm/irqflags.h:29: Error: bad instruction `asm volatile('
   arch/arm/include/asm/irqflags.h:30: Error: bad instruction `	mrs	%0, ""cpsr""	@ arch_local_irq_save\n"'
>> arch/arm/include/asm/irqflags.h:31: Error: bad instruction `	cpsid	i"'
>> arch/arm/include/asm/irqflags.h:32: Error: junk at end of line, first unrecognized character is `:'
>> arch/arm/include/asm/irqflags.h:33: Error: bad instruction `return flags'
   arch/arm/include/asm/irqflags.h:34: Error: junk at end of line, first unrecognized character is `}'
>> arch/arm/include/asm/irqflags.h:37: Error: bad instruction `static inline void arch_local_irq_enable(void)'
   arch/arm/include/asm/irqflags.h:38: Error: junk at end of line, first unrecognized character is `{'
   arch/arm/include/asm/irqflags.h:39: Error: bad instruction `asm volatile('
>> arch/arm/include/asm/irqflags.h:40: Error: bad instruction `	cpsie i			@ arch_local_irq_enable"'
   arch/arm/include/asm/irqflags.h:41: Error: junk at end of line, first unrecognized character is `:'
   arch/arm/include/asm/irqflags.h:42: Error: junk at end of line, first unrecognized character is `:'
   arch/arm/include/asm/irqflags.h:43: Error: junk at end of line, first unrecognized character is `:'
   arch/arm/include/asm/irqflags.h:44: Error: junk at end of line, first unrecognized character is `}'
>> arch/arm/include/asm/irqflags.h:47: Error: bad instruction `static inline void arch_local_irq_disable(void)'
   arch/arm/include/asm/irqflags.h:48: Error: junk at end of line, first unrecognized character is `{'
   arch/arm/include/asm/irqflags.h:49: Error: bad instruction `asm volatile('
>> arch/arm/include/asm/irqflags.h:50: Error: bad instruction `	cpsid i			@ arch_local_irq_disable"'
   arch/arm/include/asm/irqflags.h:51: Error: junk at end of line, first unrecognized character is `:'
   arch/arm/include/asm/irqflags.h:52: Error: junk at end of line, first unrecognized character is `:'
   arch/arm/include/asm/irqflags.h:53: Error: junk at end of line, first unrecognized character is `:'
   arch/arm/include/asm/irqflags.h:54: Error: junk at end of line, first unrecognized character is `}'

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-17  3:12   ` Chen-Yu Tsai
@ 2018-04-17 11:17     ` Maxime Ripard
  2018-04-17 11:25       ` Chen-Yu Tsai
  0 siblings, 1 reply; 36+ messages in thread
From: Maxime Ripard @ 2018-04-17 11:17 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mylène Josserand, Russell King, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 1326 bytes --]

On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
> <mylene.josserand@bootlin.com> wrote:
> > Move the assembly code for cluster cache enabling and resuming
> > into an assembly file instead of having it directly in C code.
> >
> > Remove the CFLAGS because we are using the ARM directive "arch"
> > instead.
> >
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> > ---
> >  arch/arm/mach-sunxi/Makefile  |  4 +--
> >  arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
> >  3 files changed, 85 insertions(+), 81 deletions(-)
> >  create mode 100644 arch/arm/mach-sunxi/headsmp.S
> 
> I'm still not convinced about this whole "move ASM to separate
> file" thing, especially now that you aren't actually adding any
> sunxi-specific ASM code beyond a simple function call.
> 
> Could you drop this for now?

I'd really like to have this merged actually. There's a significant
readibility improvement, so even if there's no particular functional
improvement, I'd still call it a win.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field
  2018-04-17  7:57     ` Chen-Yu Tsai
@ 2018-04-17 11:19       ` Maxime Ripard
  0 siblings, 0 replies; 36+ messages in thread
From: Maxime Ripard @ 2018-04-17 11:19 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mylène Josserand, Russell King, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 676 bytes --]

On Tue, Apr 17, 2018 at 03:57:07PM +0800, Chen-Yu Tsai wrote:
> >> @@ -697,6 +700,8 @@ static int __init sunxi_mc_smp_init(void)
> >>                       break;
> >>       }
> >>
> >> +     is_sun8i = sunxi_mc_smp_data[i].is_sun8i;
> >> +
> >
> > Do we really need to cache it? Can't we just have a pointer to the SMP
> > data structure and use that instead?
> 
> I recommended that. We don't need any of the other fields in the SMP
> data structure once we're past the init phase. This saves a dereference
> or two.

Fair enough.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T
  2018-04-16 21:50 ` [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T Mylène Josserand
@ 2018-04-17 11:20   ` Maxime Ripard
  2018-04-18  5:46     ` Mylène Josserand
  0 siblings, 1 reply; 36+ messages in thread
From: Maxime Ripard @ 2018-04-17 11:20 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 681 bytes --]

On Mon, Apr 16, 2018 at 11:50:30PM +0200, Mylène Josserand wrote:
> @@ -535,8 +599,12 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
>  	return !ret;
>  }
>  
> -static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
> +static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
>  {
> +	/* CPU0 hotplug not handled for sun8i-a83t */
> +	if (is_sun8i)
> +		if (cpu == 0)
> +			return false;
>  	return true;

I think Chen-Yu told you how to implement the hotplug in the previous
iteration, did you have time to test it?

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-17 11:17     ` Maxime Ripard
@ 2018-04-17 11:25       ` Chen-Yu Tsai
  2018-04-18  8:45         ` Maxime Ripard
  0 siblings, 1 reply; 36+ messages in thread
From: Chen-Yu Tsai @ 2018-04-17 11:25 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Mylène Josserand, Russell King, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
>> <mylene.josserand@bootlin.com> wrote:
>> > Move the assembly code for cluster cache enabling and resuming
>> > into an assembly file instead of having it directly in C code.
>> >
>> > Remove the CFLAGS because we are using the ARM directive "arch"
>> > instead.
>> >
>> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
>> > ---
>> >  arch/arm/mach-sunxi/Makefile  |  4 +--
>> >  arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
>> >  arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
>> >  3 files changed, 85 insertions(+), 81 deletions(-)
>> >  create mode 100644 arch/arm/mach-sunxi/headsmp.S
>>
>> I'm still not convinced about this whole "move ASM to separate
>> file" thing, especially now that you aren't actually adding any
>> sunxi-specific ASM code beyond a simple function call.
>>
>> Could you drop this for now?
>
> I'd really like to have this merged actually. There's a significant
> readibility improvement, so even if there's no particular functional
> improvement, I'd still call it a win.

What parts do you consider hard to read? The extra quotes? Trailing
newline? Or perhaps the __stringify bits?

ChenYu

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T
  2018-04-17 11:20   ` Maxime Ripard
@ 2018-04-18  5:46     ` Mylène Josserand
  0 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-18  5:46 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

Hello Maxime,

On Tue, 17 Apr 2018 13:20:38 +0200
Maxime Ripard <maxime.ripard@bootlin.com> wrote:

> On Mon, Apr 16, 2018 at 11:50:30PM +0200, Mylène Josserand wrote:
> > @@ -535,8 +599,12 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
> >  	return !ret;
> >  }
> >  
> > -static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
> > +static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
> >  {
> > +	/* CPU0 hotplug not handled for sun8i-a83t */
> > +	if (is_sun8i)
> > +		if (cpu == 0)
> > +			return false;
> >  	return true;  
> 
> I think Chen-Yu told you how to implement the hotplug in the previous
> iteration, did you have time to test it?

Not yet, I will have a look this evening.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 00/11] Sunxi: Add SMP support on A83T
  2018-04-17  2:15 ` [PATCH v6 00/11] Sunxi: Add SMP support on A83T Ondřej Jirman
@ 2018-04-18  5:50   ` Mylène Josserand
  0 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-18  5:50 UTC (permalink / raw)
  To: Ondřej Jirman
  Cc: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm, devicetree, quentin.schulz,
	linux-kernel, linux-renesas-soc, clabbe.montjoie,
	thomas.petazzoni, linux-arm-kernel

Hello Ondrej,

On Tue, 17 Apr 2018 04:15:00 +0200
Ondřej Jirman <doudahwezomiechahtah@xff.cz> wrote:

> Hello Mylène,
> 
> Please also add this:
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index ce53ceaf4cc5..d9c8ecf88ec6 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -51,7 +51,7 @@ config MACH_SUN9I
>  config ARCH_SUNXI_MC_SMP
>         bool
>         depends on SMP
> -   default MACH_SUN9I
> + default MACH_SUN9I || MACH_SUN8I
>         select ARM_CCI400_PORT_CTRL
>         select ARM_CPU_SUSPEND
> 
> Because otherwise when I'm building kernel just for sun8i and I don't have sun9i
> enabled, this new SMP code for A83T (which is sun8i) will not be built.
> 

True, I forgot to add this, thanks!

Best regards,

Mylène

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com


> thank you,
>   Ondrej
> 
> On Mon, Apr 16, 2018 at 11:50:21PM +0200, Mylène Josserand wrote:
> > Hello everyone,
> > 
> > This is a V6 of my series that adds SMP support for Allwinner sun8i-a83t.
> > Based on sunxi's tree, sunxi/for-next branch.
> > Depends on a patch from Doug Berger that allows to include the "cpu-type"
> > header on assembly files:
> > 6c7dd080ba4b ("ARM: Allow this header to be included by assembly files")
> > 
> > This new series refactors the shmobile code to use the function introduced
> > in this series: "secure_cntvoff_init".
> > Geert Uytterhoeven and Simon Horman, could you review and test this series
> > on Renesas boards? Thank you very much!
> > 
> > If you have any remarks/questions, let me know.
> > Thank you in advance,
> > Mylène
> > 
> > Changes since v5:
> >     - Remove my patch 01 and use the patch of Doug Berger to be able to
> >     include the cpu-type header on assembly files.
> >     - Rename smp_init_cntvoff function into secure_cntvoff_init according
> >     to Marc Zyngier's review.
> >     - According to Chen-Yu and Maxime's reviews, remove the patch that was
> >     moving structures. Instead of using an index to retrieve which
> >     architecture we are having, use a global variable.
> >     - Merge the 2 patches that move assembly code from C to assembly file.
> >     - Use a sun8i field instead of sun9i to know on which architecture we
> >     are using because many modifications/additions of the code are for
> >     sun8i-a83t.
> >     - Rework the patch "add is_sun8i field" to add only this field in this
> >     patch. The part of the patch that was starting to handle the differences
> >     between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
> >     support of sun8i-a83t.
> >     - Add a new patch that refactor the shmobile code to use the new function
> >     secure_cntvoff_init introduced in this series.
> > 
> > Changes since v4:
> >     - Rebased my series according to new Chen-Yu series:
> >        "ARM: sunxi: Clean and improvements for multi-cluster SMP"
> >        https://lkml.org/lkml/2018/3/8/886
> >     - Updated my series according to Marc Zyngier's reviews to add CNTVOFF
> >     initialization's function into ARM's common part. Thanks to that, other
> >     platforms such as Renesa can use this function.
> >     - For boot CPU, create a new machine to handle the CNTVOFF initialization
> >     using "init_early" callback.
> > Changes since v3:
> >     - Take into account Maxime's reviews:
> > 	- split the first patch into 4 new patches: add sun9i device tree
> > 	parsing, rename some variables, add a83t support and finally,
> > 	add hotplug support.
> > 	- Move the code of previous patch 07 (to disable CPU0 disabling)
> > 	into hotplug support patch (see patch 04)
> > 	- Remove the patch that added PRCM register because it is already
> > 	available. Because of that, update the device tree parsing to use
> > 	"sun8i-a83t-r-ccu".
> > 	- Use a variable to know which SoC we currently have
> >     - Take into account Chen-Yu's reviews: create two iounmap functions
> >     to release the resources of the device tree parsing.
> >     - Take into account Marc's review: Update the code to initialize CNTVOFF
> >     register. As there is already assembly code in the driver, I decided
> >     to create an assembly file not to mix assembly and C code.
> >     For that, I create 3 new patches: move the current assembly code that
> >     handles the cluster cache enabling into a file, move the cpu_resume entry
> >     in this file and finally, add a new assembly entry to initialize the timer
> >     offset for boot CPU and secondary CPUs.
> > 
> > Changes since v2:
> >     - Rebased my modifications according to new Chen Yu's patch series
> >     that adds SMP support for sun9i-a80 (without MCPM).
> >     - Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
> >     and PRCM registers for more visibility.
> >     - The hotplug of CPU0 is currently not working (even after trying what
> >     Allwinner's code is doing) so remove the possibility of disabling
> >     this CPU. Created a new patch for it.
> > 
> > Changes since v1:
> >     - Add Chen Yu's patch in my series (see path 01)
> >     - Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
> >     Create two functions to separate the DT parsing of sun9i-a80 and
> >     sun8i-a83t.
> >     - Thanks to Maxime's review: order device tree's nodes according
> >     to physical addresses, remove unused label and fix registers' sizes.
> >     Update the commit log and commit title of my last patch (see
> >     patch 05).
> > 
> > Mylène Josserand (11):
> >   ARM: sunxi: smp: Move assembly code into a file
> >   ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
> >   ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
> >   ARM: dts: sun8i: a83t: Add CCI-400 node
> >   ARM: smp: Add initialization of CNTVOFF
> >   ARM: sunxi: Add initialization of CNTVOFF
> >   ARM: sun9i: smp: Rename clusters's power-off
> >   ARM: sun9i: smp: Add is_sun8i field
> >   ARM: sun8i: smp: Add support for A83T
> >   ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
> >   ARM: shmobile: Convert file to use cntvoff
> > 
> >  arch/arm/boot/dts/sun8i-a83t.dtsi        |  59 ++++++++
> >  arch/arm/common/Makefile                 |   1 +
> >  arch/arm/common/secure_cntvoff.S         |  31 ++++
> >  arch/arm/include/asm/secure_cntvoff.h    |   8 ++
> >  arch/arm/mach-shmobile/common.h          |   1 -
> >  arch/arm/mach-shmobile/headsmp-apmu.S    |  22 +--
> >  arch/arm/mach-shmobile/setup-rcar-gen2.c |   3 +-
> >  arch/arm/mach-sunxi/Makefile             |   4 +-
> >  arch/arm/mach-sunxi/headsmp.S            |  81 +++++++++++
> >  arch/arm/mach-sunxi/mc_smp.c             | 240 +++++++++++++++++++------------
> >  arch/arm/mach-sunxi/sunxi.c              |  20 ++-
> >  11 files changed, 349 insertions(+), 121 deletions(-)
> >  create mode 100644 arch/arm/common/secure_cntvoff.S
> >  create mode 100644 arch/arm/include/asm/secure_cntvoff.h
> >  create mode 100644 arch/arm/mach-sunxi/headsmp.S
> > 
> > -- 
> > 2.11.0
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel  

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off
  2018-04-17  8:21   ` Sergei Shtylyov
@ 2018-04-18  5:51     ` Mylène Josserand
  0 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-18  5:51 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm, linux-renesas-soc, devicetree,
	clabbe.montjoie, quentin.schulz, thomas.petazzoni,
	linux-arm-kernel, linux-kernel

Hello,

On Tue, 17 Apr 2018 11:21:02 +0300
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote:

> Hello!
> 
> On 4/17/2018 12:50 AM, Mylène Josserand wrote:
> 
> > To prepare the support for sun8i-a83t, rename the variable name  
> 
>     s/variable/macro/ maybe? Also "rename the ... name" sounds tautological...

Thank you for the correction.

Best regards,

Mylène

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

> 
> > that handles the power-off of clusters because it is different from
> > sun9i-a80 to sun8i-a83t.
> > 
> > The power off register for clusters are different from a80 and a83t.
> > 
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> > Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > ---
> >   arch/arm/mach-sunxi/mc_smp.c | 6 +++---
> >   1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
> > index 727968d6a3e5..03f021d0c73e 100644
> > --- a/arch/arm/mach-sunxi/mc_smp.c
> > +++ b/arch/arm/mach-sunxi/mc_smp.c
> > @@ -60,7 +60,7 @@
> >   #define PRCM_CPU_PO_RST_CTRL_CORE(n)	BIT(n)
> >   #define PRCM_CPU_PO_RST_CTRL_CORE_ALL	0xf
> >   #define PRCM_PWROFF_GATING_REG(c)	(0x100 + 0x4 * (c))
> > -#define PRCM_PWROFF_GATING_REG_CLUSTER	BIT(4)
> > +#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I	BIT(4)
> >   #define PRCM_PWROFF_GATING_REG_CORE(n)	BIT(n)
> >   #define PRCM_PWR_SWITCH_REG(c, cpu)	(0x140 + 0x10 * (c) + 0x4 * (cpu))
> >   #define PRCM_CPU_SOFT_ENTRY_REG		0x164
> > @@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
> >   
> >   	/* clear cluster power gate */
> >   	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
> > -	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
> > +	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
> >   	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
> >   	udelay(20);
> >   
> > @@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
> >   	/* gate cluster power */
> >   	pr_debug("%s: gate cluster power\n", __func__);
> >   	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
> > -	reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
> > +	reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
> >   	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
> >   	udelay(20);
> >     
> 
> MBR, Sergei

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-17 11:25       ` Chen-Yu Tsai
@ 2018-04-18  8:45         ` Maxime Ripard
  2018-04-18 10:05           ` Chen-Yu Tsai
  0 siblings, 1 reply; 36+ messages in thread
From: Maxime Ripard @ 2018-04-18  8:45 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mylène Josserand, Russell King, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 1725 bytes --]

On Tue, Apr 17, 2018 at 07:25:15PM +0800, Chen-Yu Tsai wrote:
> On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
> >> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
> >> <mylene.josserand@bootlin.com> wrote:
> >> > Move the assembly code for cluster cache enabling and resuming
> >> > into an assembly file instead of having it directly in C code.
> >> >
> >> > Remove the CFLAGS because we are using the ARM directive "arch"
> >> > instead.
> >> >
> >> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> >> > ---
> >> >  arch/arm/mach-sunxi/Makefile  |  4 +--
> >> >  arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
> >> >  arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
> >> >  3 files changed, 85 insertions(+), 81 deletions(-)
> >> >  create mode 100644 arch/arm/mach-sunxi/headsmp.S
> >>
> >> I'm still not convinced about this whole "move ASM to separate
> >> file" thing, especially now that you aren't actually adding any
> >> sunxi-specific ASM code beyond a simple function call.
> >>
> >> Could you drop this for now?
> >
> > I'd really like to have this merged actually. There's a significant
> > readibility improvement, so even if there's no particular functional
> > improvement, I'd still call it a win.
> 
> What parts do you consider hard to read? The extra quotes? Trailing
> newline? Or perhaps the __stringify bits?

All of this, plus the clobbers and operands.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF
  2018-04-16 21:50 ` [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
@ 2018-04-18  9:30   ` Geert Uytterhoeven
  2018-04-18 10:01     ` Mylène Josserand
  0 siblings, 1 reply; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-04-18  9:30 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: Russell King, Maxime Ripard, Chen-Yu Tsai, Marc Zyngier,
	Mark Rutland, Rob Herring, Simon Horman, Magnus Damm,
	Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	LABBE Corentin, quentin.schulz, Thomas Petazzoni, Linux ARM,
	Linux Kernel Mailing List

Allo Mylène,

On Mon, Apr 16, 2018 at 11:50 PM, Mylène Josserand
<mylene.josserand@bootlin.com> wrote:
> The CNTVOFF register from arch timer is uninitialized.
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
> It leads to an random offset value meaning that each CPU will have a
> different time, which isn't working very well.
>
> Add assembly code used for boot CPU and secondary CPU cores to make
> sure that the CNTVOFF register is initialized. Because this code can
> be used by different platforms, add this assembly file in ARM's common
> folder.

Thanks for your patch!

> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff
  2018-04-16 21:50 ` [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
@ 2018-04-18  9:36   ` Geert Uytterhoeven
  2018-04-18 10:03     ` Mylène Josserand
  0 siblings, 1 reply; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-04-18  9:36 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: Russell King, Maxime Ripard, Chen-Yu Tsai, Marc Zyngier,
	Mark Rutland, Rob Herring, Simon Horman, Magnus Damm,
	Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	LABBE Corentin, quentin.schulz, Thomas Petazzoni, Linux ARM,
	Linux Kernel Mailing List

Hi Mylène,

On Mon, Apr 16, 2018 at 11:50 PM, Mylène Josserand
<mylene.josserand@bootlin.com> wrote:
> Now that a common function is available for CNTVOFF's
> initialization, let's convert shmobile-apmu code to use
> this function.

Thanks for your patch, works fine on Renesas ALT with R-Car E2,
which suffers from lack of CNTVOFF initialization.

> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF
  2018-04-18  9:30   ` Geert Uytterhoeven
@ 2018-04-18 10:01     ` Mylène Josserand
  0 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-18 10:01 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Russell King, Maxime Ripard, Chen-Yu Tsai, Marc Zyngier,
	Mark Rutland, Rob Herring, Simon Horman, Magnus Damm,
	Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	LABBE Corentin, quentin.schulz, Thomas Petazzoni, Linux ARM,
	Linux Kernel Mailing List

Hello Geert,

On Wed, 18 Apr 2018 11:30:47 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> Allo Mylène,
> 
> On Mon, Apr 16, 2018 at 11:50 PM, Mylène Josserand
> <mylene.josserand@bootlin.com> wrote:
> > The CNTVOFF register from arch timer is uninitialized.
> > It should be done by the bootloader but it is currently not the case,
> > even for boot CPU because this SoC is booting in secure mode.
> > It leads to an random offset value meaning that each CPU will have a
> > different time, which isn't working very well.
> >
> > Add assembly code used for boot CPU and secondary CPU cores to make
> > sure that the CNTVOFF register is initialized. Because this code can
> > be used by different platforms, add this assembly file in ARM's common
> > folder.  
> 
> Thanks for your patch!
> 
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>  
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

Great, thank you very much for your test!

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff
  2018-04-18  9:36   ` Geert Uytterhoeven
@ 2018-04-18 10:03     ` Mylène Josserand
  2018-04-18 13:48       ` Simon Horman
  0 siblings, 1 reply; 36+ messages in thread
From: Mylène Josserand @ 2018-04-18 10:03 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Russell King, Maxime Ripard, Chen-Yu Tsai, Marc Zyngier,
	Mark Rutland, Rob Herring, Simon Horman, Magnus Damm,
	Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	LABBE Corentin, quentin.schulz, Thomas Petazzoni, Linux ARM,
	Linux Kernel Mailing List

Hello,

On Wed, 18 Apr 2018 11:36:27 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> Hi Mylène,
> 
> On Mon, Apr 16, 2018 at 11:50 PM, Mylène Josserand
> <mylene.josserand@bootlin.com> wrote:
> > Now that a common function is available for CNTVOFF's
> > initialization, let's convert shmobile-apmu code to use
> > this function.  
> 
> Thanks for your patch, works fine on Renesas ALT with R-Car E2,
> which suffers from lack of CNTVOFF initialization.

Great to know that it works on this board.

> 
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>  
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

Thank you again for testing it :)

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-18  8:45         ` Maxime Ripard
@ 2018-04-18 10:05           ` Chen-Yu Tsai
  2018-04-19  6:53             ` Mylène Josserand
  0 siblings, 1 reply; 36+ messages in thread
From: Chen-Yu Tsai @ 2018-04-18 10:05 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Mylène Josserand, Russell King, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

On Wed, Apr 18, 2018 at 4:45 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Tue, Apr 17, 2018 at 07:25:15PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
>> <maxime.ripard@bootlin.com> wrote:
>> > On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
>> >> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
>> >> <mylene.josserand@bootlin.com> wrote:
>> >> > Move the assembly code for cluster cache enabling and resuming
>> >> > into an assembly file instead of having it directly in C code.
>> >> >
>> >> > Remove the CFLAGS because we are using the ARM directive "arch"
>> >> > instead.
>> >> >
>> >> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
>> >> > ---
>> >> >  arch/arm/mach-sunxi/Makefile  |  4 +--
>> >> >  arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
>> >> >  arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
>> >> >  3 files changed, 85 insertions(+), 81 deletions(-)
>> >> >  create mode 100644 arch/arm/mach-sunxi/headsmp.S
>> >>
>> >> I'm still not convinced about this whole "move ASM to separate
>> >> file" thing, especially now that you aren't actually adding any
>> >> sunxi-specific ASM code beyond a simple function call.
>> >>
>> >> Could you drop this for now?
>> >
>> > I'd really like to have this merged actually. There's a significant
>> > readibility improvement, so even if there's no particular functional
>> > improvement, I'd still call it a win.
>>
>> What parts do you consider hard to read? The extra quotes? Trailing
>> newline? Or perhaps the __stringify bits?
>
> All of this, plus the clobbers and operands.

Ok. Lets move it then.

The kbuild reports indicate this still needs some work though.

ChenYu

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff
  2018-04-18 10:03     ` Mylène Josserand
@ 2018-04-18 13:48       ` Simon Horman
  2018-04-19  6:40         ` Mylène Josserand
  0 siblings, 1 reply; 36+ messages in thread
From: Simon Horman @ 2018-04-18 13:48 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: Geert Uytterhoeven, Russell King, Maxime Ripard, Chen-Yu Tsai,
	Marc Zyngier, Mark Rutland, Rob Herring, Magnus Damm,
	Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	LABBE Corentin, quentin.schulz, Thomas Petazzoni, Linux ARM,
	Linux Kernel Mailing List

On Wed, Apr 18, 2018 at 12:03:27PM +0200, Mylène Josserand wrote:
> Hello,
> 
> On Wed, 18 Apr 2018 11:36:27 +0200
> Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> > Hi Mylène,
> > 
> > On Mon, Apr 16, 2018 at 11:50 PM, Mylène Josserand
> > <mylene.josserand@bootlin.com> wrote:
> > > Now that a common function is available for CNTVOFF's
> > > initialization, let's convert shmobile-apmu code to use
> > > this function.  
> > 
> > Thanks for your patch, works fine on Renesas ALT with R-Car E2,
> > which suffers from lack of CNTVOFF initialization.
> 
> Great to know that it works on this board.
> 
> > 
> > > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>  
> > 
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > 
> > Gr{oetje,eeting}s,
> > 
> >                         Geert
> > 
> 
> Thank you again for testing it :)

What is the plan for merging this patch/series?

I'd be happy to take this patch through the renesas tree once any
dependencies are in place.

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff
  2018-04-18 13:48       ` Simon Horman
@ 2018-04-19  6:40         ` Mylène Josserand
  0 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-19  6:40 UTC (permalink / raw)
  To: Simon Horman
  Cc: Geert Uytterhoeven, Russell King, Maxime Ripard, Chen-Yu Tsai,
	Marc Zyngier, Mark Rutland, Rob Herring, Magnus Damm,
	Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	LABBE Corentin, quentin.schulz, Thomas Petazzoni, Linux ARM,
	Linux Kernel Mailing List

Hello Simon,

On Wed, 18 Apr 2018 15:48:55 +0200
Simon Horman <horms@verge.net.au> wrote:

> On Wed, Apr 18, 2018 at 12:03:27PM +0200, Mylène Josserand wrote:
> > Hello,
> > 
> > On Wed, 18 Apr 2018 11:36:27 +0200
> > Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >   
> > > Hi Mylène,
> > > 
> > > On Mon, Apr 16, 2018 at 11:50 PM, Mylène Josserand
> > > <mylene.josserand@bootlin.com> wrote:  
> > > > Now that a common function is available for CNTVOFF's
> > > > initialization, let's convert shmobile-apmu code to use
> > > > this function.    
> > > 
> > > Thanks for your patch, works fine on Renesas ALT with R-Car E2,
> > > which suffers from lack of CNTVOFF initialization.  
> > 
> > Great to know that it works on this board.
> >   
> > >   
> > > > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>    
> > > 
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > 
> > > Gr{oetje,eeting}s,
> > > 
> > >                         Geert
> > >   
> > 
> > Thank you again for testing it :)  
> 
> What is the plan for merging this patch/series?
> 
> I'd be happy to take this patch through the renesas tree once any
> dependencies are in place.

I will send a new series before the end of the week to correct the
reviews I got so far and I hope that the next one will be merged
(otherwise, I will fix what needs to be fixed, of course).

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file
  2018-04-18 10:05           ` Chen-Yu Tsai
@ 2018-04-19  6:53             ` Mylène Josserand
  0 siblings, 0 replies; 36+ messages in thread
From: Mylène Josserand @ 2018-04-19  6:53 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Maxime Ripard, Russell King, Marc Zyngier, Mark Rutland,
	Rob Herring, Simon, Geert Uytterhoeven, Magnus Damm,
	open list:ARM/SHMOBILE ARM...,
	devicetree, LABBE Corentin, Quentin Schulz, Thomas Petazzoni,
	linux-arm-kernel, linux-kernel

Hello Chen-Yu,

On Wed, 18 Apr 2018 18:05:03 +0800
Chen-Yu Tsai <wens@csie.org> wrote:

> On Wed, Apr 18, 2018 at 4:45 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Tue, Apr 17, 2018 at 07:25:15PM +0800, Chen-Yu Tsai wrote:  
> >> On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
> >> <maxime.ripard@bootlin.com> wrote:  
> >> > On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:  
> >> >> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
> >> >> <mylene.josserand@bootlin.com> wrote:  
> >> >> > Move the assembly code for cluster cache enabling and resuming
> >> >> > into an assembly file instead of having it directly in C code.
> >> >> >
> >> >> > Remove the CFLAGS because we are using the ARM directive "arch"
> >> >> > instead.
> >> >> >
> >> >> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> >> >> > ---
> >> >> >  arch/arm/mach-sunxi/Makefile  |  4 +--
> >> >> >  arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
> >> >> >  arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
> >> >> >  3 files changed, 85 insertions(+), 81 deletions(-)
> >> >> >  create mode 100644 arch/arm/mach-sunxi/headsmp.S  
> >> >>
> >> >> I'm still not convinced about this whole "move ASM to separate
> >> >> file" thing, especially now that you aren't actually adding any
> >> >> sunxi-specific ASM code beyond a simple function call.
> >> >>
> >> >> Could you drop this for now?  
> >> >
> >> > I'd really like to have this merged actually. There's a significant
> >> > readibility improvement, so even if there's no particular functional
> >> > improvement, I'd still call it a win.  
> >>
> >> What parts do you consider hard to read? The extra quotes? Trailing
> >> newline? Or perhaps the __stringify bits?  
> >
> > All of this, plus the clobbers and operands.  
> 
> Ok. Lets move it then.

Ok, I will not drop this patch then.

> 
> The kbuild reports indicate this still needs some work though.

Yes, this is "normal" because the patch, that I depend on, is not
applied yet (even if my cover-letter can let think that, it is not the
case, sorry).

It is applied on Broadcom ARM SoC since Tuesday: 
https://lkml.org/lkml/2018/2/23/1263
https://github.com/Broadcom/stblinux/commits/soc/next

With this patch, it should fix the errors reported by kbuild.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

^ permalink raw reply	[flat|nested] 36+ messages in thread

end of thread, other threads:[~2018-04-19  6:53 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
2018-04-17  3:12   ` Chen-Yu Tsai
2018-04-17 11:17     ` Maxime Ripard
2018-04-17 11:25       ` Chen-Yu Tsai
2018-04-18  8:45         ` Maxime Ripard
2018-04-18 10:05           ` Chen-Yu Tsai
2018-04-19  6:53             ` Mylène Josserand
2018-04-17  6:36   ` kbuild test robot
2018-04-17 10:46   ` kbuild test robot
2018-04-16 21:50 ` [PATCH v6 02/11] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
2018-04-17  3:13   ` Chen-Yu Tsai
2018-04-16 21:50 ` [PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
2018-04-18  9:30   ` Geert Uytterhoeven
2018-04-18 10:01     ` Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 06/11] ARM: sunxi: " Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
2018-04-17  8:21   ` Sergei Shtylyov
2018-04-18  5:51     ` Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field Mylène Josserand
2018-04-17  7:52   ` Maxime Ripard
2018-04-17  7:57     ` Chen-Yu Tsai
2018-04-17 11:19       ` Maxime Ripard
2018-04-16 21:50 ` [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T Mylène Josserand
2018-04-17 11:20   ` Maxime Ripard
2018-04-18  5:46     ` Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 10/11] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
2018-04-16 21:50 ` [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
2018-04-18  9:36   ` Geert Uytterhoeven
2018-04-18 10:03     ` Mylène Josserand
2018-04-18 13:48       ` Simon Horman
2018-04-19  6:40         ` Mylène Josserand
2018-04-17  2:15 ` [PATCH v6 00/11] Sunxi: Add SMP support on A83T Ondřej Jirman
2018-04-18  5:50   ` Mylène Josserand

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