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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	Marcel Ziswiler <marcel@ziswiler.com>,
	Marc Dietrich <marvin24@gmx.de>, <linux-clk@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1 2/4] pinctrl: tegra20: Provide CDEV1/2 clock muxes
Date: Mon, 30 Apr 2018 10:46:09 +0300	[thread overview]
Message-ID: <20180430074609.GK6835@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <20180426235818.10018-3-digetx@gmail.com>

On Fri, Apr 27, 2018 at 02:58:16AM +0300, Dmitry Osipenko wrote:
> Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
> Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
> that main clk-controller driver could get an actual parent clock for the
> CDEV1/2 clocks.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  drivers/pinctrl/tegra/pinctrl-tegra.c   | 11 ---------
>  drivers/pinctrl/tegra/pinctrl-tegra.h   | 11 +++++++++
>  drivers/pinctrl/tegra/pinctrl-tegra20.c | 30 ++++++++++++++++++++++++-
>  3 files changed, 40 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index 72c718e66ebb..49c7c1499bc3 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -33,17 +33,6 @@
>  #include "../pinctrl-utils.h"
>  #include "pinctrl-tegra.h"
>  
> -struct tegra_pmx {
> -	struct device *dev;
> -	struct pinctrl_dev *pctl;
> -
> -	const struct tegra_pinctrl_soc_data *soc;
> -	const char **group_pins;
> -
> -	int nbanks;
> -	void __iomem **regs;
> -};
> -
>  static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
>  {
>  	return readl(pmx->regs[bank] + reg);
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
> index 33b17cb1471e..aa33c20766c4 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
> @@ -16,6 +16,17 @@
>  #ifndef __PINMUX_TEGRA_H__
>  #define __PINMUX_TEGRA_H__
>  
> +struct tegra_pmx {
> +	struct device *dev;
> +	struct pinctrl_dev *pctl;
> +
> +	const struct tegra_pinctrl_soc_data *soc;
> +	const char **group_pins;
> +
> +	int nbanks;
> +	void __iomem **regs;
> +};
> +
>  enum tegra_pinconf_param {
>  	/* argument: tegra_pinconf_pull */
>  	TEGRA_PINCONF_PARAM_PULL,
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c
> index 7e38ee9bae78..f31e39d797f9 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c
> @@ -19,6 +19,7 @@
>   * more details.
>   */
>  
> +#include <linux/clk-provider.h>
>  #include <linux/init.h>
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
> @@ -2231,9 +2232,36 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
>  	.drvtype_in_mux = false,
>  };
>  
> +static const char *cdev1_parents[4] = {

No need to have 4 here, just cdev1_parents[] will do. 

> +	"cdev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
> +};
> +
> +static const char *cdev2_parents[4] = {
> +	"cdev2_osc_div", "hclk", "pclk", "pll_p_out4",
> +};
> +

Same here.

> +static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
> +{
> +	struct tegra_pmx *pmx = platform_get_drvdata(pdev);
> +
> +	clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
> +			 pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
> +
> +	clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
> +			 pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
> +}
> +
>  static int tegra20_pinctrl_probe(struct platform_device *pdev)
>  {
> -	return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
> +	int err;
> +
> +	err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
> +	if (err)
> +		return err;
> +
> +	tegra20_pinctrl_register_clock_muxes(pdev);
> +
> +	return 0;
>  }
>  
>  static const struct of_device_id tegra20_pinctrl_of_match[] = {

Apart from these nitpicks:

Acked-By:  Peter De Schrijver <pdeschrijver@nvidia.com>

  reply	other threads:[~2018-04-30  7:46 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-26 23:58 [PATCH v1 0/4] Restore ULPI USB on Tegra20 Dmitry Osipenko
2018-04-26 23:58 ` [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers Dmitry Osipenko
2018-04-27 12:33   ` Marcel Ziswiler
2018-04-27 12:54     ` Dmitry Osipenko
2018-04-27 13:00       ` Marcel Ziswiler
2018-05-03 11:59         ` Dmitry Osipenko
2018-05-03 12:02           ` Dmitry Osipenko
2018-05-03 12:30             ` Marcel Ziswiler
2018-05-03 12:35               ` Dmitry Osipenko
2018-04-30  7:48   ` Peter De Schrijver
2018-04-26 23:58 ` [PATCH v1 2/4] pinctrl: tegra20: Provide CDEV1/2 clock muxes Dmitry Osipenko
2018-04-30  7:46   ` Peter De Schrijver [this message]
2018-05-02 12:32   ` Linus Walleij
2018-04-26 23:58 ` [PATCH v1 3/4] clk: tegra20: Set correct parents for CDEV1/2 clocks Dmitry Osipenko
2018-04-30  7:46   ` Peter De Schrijver
2018-05-01 21:31   ` Stephen Boyd
2018-04-26 23:58 ` [PATCH v1 4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20" Dmitry Osipenko
2018-04-27 12:30 ` [PATCH v1 0/4] Restore ULPI USB on Tegra20 Marc Dietrich
2018-04-30  9:48 ` Thierry Reding
2018-04-30 11:28   ` Thierry Reding
2018-05-01 21:30     ` Stephen Boyd
2018-05-02 12:58     ` Linus Walleij

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