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* [PATCH v8 00/12] Sunxi: Add SMP support on A83T
@ 2018-05-01 12:31 Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 01/12] ARM: Allow this header to be included by assembly files Mylène Josserand
                   ` (11 more replies)
  0 siblings, 12 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Hello everyone,

This is a V8 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files that I included in my series (patch 01).

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes from v7:
    - Add the patch of Doug Berger in my series.
    - Rename the machine name to start secure_cntvoff into "sun8i-a83t",
    according to Maxime's review.
    - Change the type of is_a83t field from integer into boolean.

Changes from v6:
    - Correct the commit log on patch 07 according to Sergei Shtylyov's
    review.
    - Rename the field "is_sun8i" into "is_a83t".
    - Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
    - Remove my patch 01 and use the patch of Doug Berger to be able to
    include the cpu-type header on assembly files.
    - Rename smp_init_cntvoff function into secure_cntvoff_init according
    to Marc Zyngier's review.
    - According to Chen-Yu and Maxime's reviews, remove the patch that was
    moving structures. Instead of using an index to retrieve which
    architecture we are having, use a global variable.
    - Merge the 2 patches that move assembly code from C to assembly file.
    - Use a sun8i field instead of sun9i to know on which architecture we
    are using because many modifications/additions of the code are for
    sun8i-a83t.
    - Rework the patch "add is_sun8i field" to add only this field in this
    patch. The part of the patch that was starting to handle the differences
    between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
    support of sun8i-a83t.
    - Add a new patch that refactor the shmobile code to use the new function
    secure_cntvoff_init introduced in this series.

Changes from v4:
    - Rebased my series according to new Chen-Yu series:
       "ARM: sunxi: Clean and improvements for multi-cluster SMP"
       https://lkml.org/lkml/2018/3/8/886
    - Updated my series according to Marc Zyngier's reviews to add CNTVOFF
    initialization's function into ARM's common part. Thanks to that, other
    platforms such as Renesa can use this function.
    - For boot CPU, create a new machine to handle the CNTVOFF initialization
    using "init_early" callback.

Changes from v3:
    - Take into account Maxime's reviews:
	- split the first patch into 4 new patches: add sun9i device tree
	parsing, rename some variables, add a83t support and finally,
	add hotplug support.
	- Move the code of previous patch 07 (to disable CPU0 disabling)
	into hotplug support patch (see patch 04)
	- Remove the patch that added PRCM register because it is already
	available. Because of that, update the device tree parsing to use
	"sun8i-a83t-r-ccu".
	- Use a variable to know which SoC we currently have
    - Take into account Chen-Yu's reviews: create two iounmap functions
    to release the resources of the device tree parsing.
    - Take into account Marc's review: Update the code to initialize CNTVOFF
    register. As there is already assembly code in the driver, I decided
    to create an assembly file not to mix assembly and C code.
    For that, I create 3 new patches: move the current assembly code that
    handles the cluster cache enabling into a file, move the cpu_resume entry
    in this file and finally, add a new assembly entry to initialize the timer
    offset for boot CPU and secondary CPUs.

Changes from v2:
    - Rebased my modifications according to new Chen Yu's patch series
    that adds SMP support for sun9i-a80 (without MCPM).
    - Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
    and PRCM registers for more visibility.
    - The hotplug of CPU0 is currently not working (even after trying what
    Allwinner's code is doing) so remove the possibility of disabling
    this CPU. Created a new patch for it.

Changes from v1:
    - Add Chen Yu's patch in my series (see path 01)
    - Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
    Create two functions to separate the DT parsing of sun9i-a80 and
    sun8i-a83t.
    - Thanks to Maxime's review: order device tree's nodes according
    to physical addresses, remove unused label and fix registers' sizes.
    Update the commit log and commit title of my last patch (see
    patch 05).

Doug Berger (1):
  ARM: Allow this header to be included by assembly files

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: sun9i: smp: Add is_a83t field
  ARM: sun8i: smp: Add support for A83T
  ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
  ARM: shmobile: Convert file to use cntvoff

 arch/arm/boot/dts/sun8i-a83t.dtsi        |  59 ++++++++
 arch/arm/common/Makefile                 |   1 +
 arch/arm/common/secure_cntvoff.S         |  31 ++++
 arch/arm/include/asm/cputype.h           |  10 +-
 arch/arm/include/asm/secure_cntvoff.h    |   8 ++
 arch/arm/mach-shmobile/common.h          |   1 -
 arch/arm/mach-shmobile/headsmp-apmu.S    |  22 +--
 arch/arm/mach-shmobile/setup-rcar-gen2.c |   3 +-
 arch/arm/mach-sunxi/Kconfig              |   2 +-
 arch/arm/mach-sunxi/Makefile             |   2 +-
 arch/arm/mach-sunxi/headsmp.S            |  81 +++++++++++
 arch/arm/mach-sunxi/mc_smp.c             | 239 +++++++++++++++++++------------
 arch/arm/mach-sunxi/sunxi.c              |  20 ++-
 13 files changed, 356 insertions(+), 123 deletions(-)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 01/12] ARM: Allow this header to be included by assembly files
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
                   ` (10 subsequent siblings)
  11 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand, Doug Berger, Florian Fainelli

From: Doug Berger <opendmb@gmail.com>

The constants defined in this file are equally useful in assembly and C
source files. The arm64 architecture version of this file allows
inclusion in both assembly and C source files, so this this commit adds
that capability to the arm architecture version so that the constants
don't need to be defined in multiple places.

Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/include/asm/cputype.h | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb546425da8a..e7632f536633 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,9 +2,6 @@
 #ifndef __ASM_ARM_CPUTYPE_H
 #define __ASM_ARM_CPUTYPE_H
 
-#include <linux/stringify.h>
-#include <linux/kernel.h>
-
 #define CPUID_ID	0
 #define CPUID_CACHETYPE	1
 #define CPUID_TCM	2
@@ -98,6 +95,11 @@
 /* Qualcomm implemented cores */
 #define ARM_CPU_PART_SCORPION		0x510002d0
 
+#ifndef __ASSEMBLY__
+
+#include <linux/stringify.h>
+#include <linux/kernel.h>
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -326,4 +328,6 @@ static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 #define cpuid_feature_extract(reg, field) \
 	cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 
+#endif /* __ASSEMBLY__ */
+
 #endif
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 01/12] ARM: Allow this header to be included by assembly files Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-02 13:18   ` Maxime Ripard
  2018-05-01 12:31 ` [PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
                   ` (9 subsequent siblings)
  11 siblings, 1 reply; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/Makefile  |  2 +-
 arch/arm/mach-sunxi/headsmp.S | 80 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++----------------------------------------
 3 files changed, 85 insertions(+), 79 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..71429aa85143 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_mc_smp.o	+= -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 000000000000..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ * Mylène Josserand <mylene.josserand@bootlin.com>
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/cputype.h>
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+	.arch	armv7-a
+	/*
+	 * Enable cluster-level coherency, in preparation for turning on the MMU.
+	 *
+	 * Also enable regional clock gating and L2 data latency settings for
+	 * Cortex-A15. These settings are from the vendor kernel.
+	 */
+	mrc	p15, 0, r1, c0, c0, 0
+	movw	r2, #(ARM_CPU_PART_MASK & 0xffff)
+	movt	r2, #(ARM_CPU_PART_MASK >> 16)
+	and	r1, r1, r2
+	movw	r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
+	movt	r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+	cmp	r1, r2
+	bne	not_a15
+
+	/* The following is Cortex-A15 specific */
+
+	/* ACTLR2: Enable CPU regional clock gates */
+	mrc p15, 1, r1, c15, c0, 4
+	orr r1, r1, #(0x1 << 31)
+	mcr p15, 1, r1, c15, c0, 4
+
+	/* L2ACTLR */
+	mrc p15, 1, r1, c15, c0, 0
+	/* Enable L2, GIC, and Timer regional clock gates */
+	orr r1, r1, #(0x1 << 26)
+	/* Disable clean/evict from being pushed to external */
+	orr r1, r1, #(0x1<<3)
+	mcr p15, 1, r1, c15, c0, 0
+
+	/* L2CTRL: L2 data RAM latency */
+	mrc p15, 1, r1, c9, c0, 2
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #(0x3 << 0)
+	mcr p15, 1, r1, c9, c0, 2
+
+	/* End of Cortex-A15 specific setup */
+	not_a15:
+
+	/* Get value of sunxi_mc_smp_first_comer */
+	adr	r1, first
+	ldr	r0, [r1]
+	ldr	r0, [r1, r0]
+
+	/* Skip cci_enable_port_for_self if not first comer */
+	cmp	r0, #0
+	bxeq	lr
+	b	cci_enable_port_for_self
+
+	.align 2
+	first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+	bl	sunxi_mc_smp_cluster_cache_enable
+	b	secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+	bl	sunxi_mc_smp_cluster_cache_enable
+	b	cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
 	struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-	asm volatile (
-		"mrc	p15, 0, r1, c0, c0, 0\n"
-		"movw	r2, #" __stringify(ARM_CPU_PART_MASK & 0xffff) "\n"
-		"movt	r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-		"and	r1, r1, r2\n"
-		"movw	r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0xffff) "\n"
-		"movt	r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
-		"cmp	r1, r2\n"
-		"bne	not_a15\n"
-
-		/* The following is Cortex-A15 specific */
-
-		/* ACTLR2: Enable CPU regional clock gates */
-		"mrc p15, 1, r1, c15, c0, 4\n"
-		"orr r1, r1, #(0x1<<31)\n"
-		"mcr p15, 1, r1, c15, c0, 4\n"
-
-		/* L2ACTLR */
-		"mrc p15, 1, r1, c15, c0, 0\n"
-		/* Enable L2, GIC, and Timer regional clock gates */
-		"orr r1, r1, #(0x1<<26)\n"
-		/* Disable clean/evict from being pushed to external */
-		"orr r1, r1, #(0x1<<3)\n"
-		"mcr p15, 1, r1, c15, c0, 0\n"
-
-		/* L2CTRL: L2 data RAM latency */
-		"mrc p15, 1, r1, c9, c0, 2\n"
-		"bic r1, r1, #(0x7<<0)\n"
-		"orr r1, r1, #(0x3<<0)\n"
-		"mcr p15, 1, r1, c9, c0, 2\n"
-
-		/* End of Cortex-A15 specific setup */
-		"not_a15:\n"
-
-		/* Get value of sunxi_mc_smp_first_comer */
-		"adr	r1, first\n"
-		"ldr	r0, [r1]\n"
-		"ldr	r0, [r1, r0]\n"
-
-		/* Skip cci_enable_port_for_self if not first comer */
-		"cmp	r0, #0\n"
-		"bxeq	lr\n"
-		"b	cci_enable_port_for_self\n"
-
-		".align 2\n"
-		"first: .word sunxi_mc_smp_first_comer - .\n"
-	);
-}
-
-static void __naked sunxi_mc_smp_secondary_startup(void)
-{
-	asm volatile(
-		"bl	sunxi_mc_smp_cluster_cache_enable\n"
-		"b	secondary_startup"
-		/* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
-		:: "i" (sunxi_mc_smp_cluster_cache_enable)
-	);
-}
+int sunxi_mc_smp_first_comer;
 
 static DEFINE_SPINLOCK(boot_lock);
 
@@ -637,16 +573,6 @@ static bool __init sunxi_mc_smp_cpu_table_init(void)
  */
 typedef typeof(cpu_reset) phys_reset_t;
 
-static void __init __naked sunxi_mc_smp_resume(void)
-{
-	asm volatile(
-		"bl	sunxi_mc_smp_cluster_cache_enable\n"
-		"b	cpu_resume"
-		/* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
-		:: "i" (sunxi_mc_smp_cluster_cache_enable)
-	);
-}
-
 static int __init nocache_trampoline(unsigned long __unused)
 {
 	phys_reset_t phys_reset;
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 01/12] ARM: Allow this header to be included by assembly files Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
                   ` (8 subsequent siblings)
  11 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 379981389eea..a50ccb475de8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
 			};
 		};
 
+		cpucfg@1700000 {
+			compatible = "allwinner,sun8i-a83t-cpucfg";
+			reg = <0x01700000 0x400>;
+		};
+
 		syscon: syscon@1c00000 {
 			compatible = "allwinner,sun8i-a83t-system-controller",
 				"syscon";
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (2 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
                   ` (7 subsequent siblings)
  11 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a50ccb475de8..53ace066b7dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -938,6 +938,11 @@
 			#reset-cells = <1>;
 		};
 
+		r_cpucfg@1f01c00 {
+			compatible = "allwinner,sun8i-a83t-r-cpucfg";
+			reg = <0x1f01c00 0x400>;
+		};
+
 		r_pio: pinctrl@1f02c00 {
 			compatible = "allwinner,sun8i-a83t-r-pinctrl";
 			reg = <0x01f02c00 0x400>;
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (3 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
                   ` (6 subsequent siblings)
  11 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <0>;
 		};
 
@@ -73,6 +74,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <1>;
 		};
 
@@ -80,6 +82,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <2>;
 		};
 
@@ -87,6 +90,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			cci-control-port = <&cci_control0>;
 			reg = <3>;
 		};
 
@@ -96,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x100>;
 		};
 
@@ -103,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x101>;
 		};
 
@@ -110,6 +116,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x102>;
 		};
 
@@ -117,6 +124,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
+			cci-control-port = <&cci_control1>;
 			reg = <0x103>;
 		};
 	};
@@ -354,6 +362,39 @@
 			reg = <0x01700000 0x400>;
 		};
 
+		cci@1790000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x01790000 0x10000>;
+			ranges = <0x0 0x01790000 0x10000>;
+
+			cci_control0: slave-if@4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control1: slave-if@5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		syscon: syscon@1c00000 {
 			compatible = "allwinner,sun8i-a83t-system-controller",
 				"syscon";
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (4 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 07/12] ARM: sunxi: " Mylène Josserand
                   ` (5 subsequent siblings)
  11 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/common/Makefile              |  1 +
 arch/arm/common/secure_cntvoff.S      | 31 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/secure_cntvoff.h |  8 ++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
 obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
+obj-$(CONFIG_SMP)		+= secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 CFLAGS_REMOVE_mcpm_entry.o	= -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index 000000000000..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(secure_cntvoff_init)
+	.arch	armv7-a
+	/*
+	 * CNTVOFF has to be initialized either from non-secure Hypervisor
+	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+	 * then it should be handled by the secure code
+	 */
+	cps	#MON_MODE
+	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
+	orr	r0, r1, #1
+	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
+	isb
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
+	isb
+	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
+	isb
+	cps	#SVC_MODE
+	ret	lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index 000000000000..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 07/12] ARM: sunxi: Add initialization of CNTVOFF
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (5 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-02 13:08   ` Maxime Ripard
  2018-05-01 12:31 ` [PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
                   ` (4 subsequent siblings)
  11 siblings, 1 reply; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add the initialization of CNTVOFF for sun8i-a83t.

For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because of that, this function can't be called in SMP's early_initcall
function which is called after timer's init.

For secondary CPUs, add this function into secondary_startup
assembly entry.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 arch/arm/mach-sunxi/headsmp.S |  1 +
 arch/arm/mach-sunxi/sunxi.c   | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
index 37dc772701f3..32d76be98541 100644
--- a/arch/arm/mach-sunxi/headsmp.S
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
 
 ENTRY(sunxi_mc_smp_secondary_startup)
 	bl	sunxi_mc_smp_cluster_cache_enable
+	bl	secure_cntvoff_init
 	b	secondary_startup
 ENDPROC(sunxi_mc_smp_secondary_startup)
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..2770a31a9278 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/mach/arch.h>
+#include <asm/secure_cntvoff.h>
 
 static const char * const sunxi_board_dt_compat[] = {
 	"allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
 	"allwinner,sun8i-a23",
 	"allwinner,sun8i-a33",
-	"allwinner,sun8i-a83t",
 	"allwinner,sun8i-h2-plus",
 	"allwinner,sun8i-h3",
 	"allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
 	.dt_compat	= sun8i_board_dt_compat,
 MACHINE_END
 
+void __init sun8i_a83t_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+	secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+	"allwinner,sun8i-a83t",
+	NULL,
+};
+
+DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")
+	.init_early	= sun8i_a83t_cntvoff_init,
+	.init_time	= sun6i_timer_init,
+	.dt_compat	= sun8i_a83t_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
 	"allwinner,sun9i-a80",
 	NULL,
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (6 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 07/12] ARM: sunxi: " Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field Mylène Josserand
                   ` (3 subsequent siblings)
  11 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)	BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL	0xf
 #define PRCM_PWROFF_GATING_REG(c)	(0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER	BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I	BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n)	BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)	(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG		0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
 	/* clear cluster power gate */
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
 	/* gate cluster power */
 	pr_debug("%s: gate cluster power\n", __func__);
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+	reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (7 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-02 13:09   ` Maxime Ripard
  2018-05-01 12:31 ` [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T Mylène Josserand
                   ` (2 subsequent siblings)
  11 siblings, 1 reply; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/mc_smp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..fc10e3a3268f 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static bool is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
 	const char *enable_method;
 	int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+	bool is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -697,6 +699,8 @@ static int __init sunxi_mc_smp_init(void)
 			break;
 	}
 
+	is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
 	of_node_put(node);
 	if (ret)
 		return -ENODEV;
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (8 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-02 13:14   ` Maxime Ripard
  2018-05-01 12:31 ` [PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
  11 siblings, 1 reply; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/Kconfig  |   2 +-
 arch/arm/mach-sunxi/mc_smp.c | 151 ++++++++++++++++++++++++++++++++++++++-----
 2 files changed, 137 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
 	bool
 	depends on SMP
-	default MACH_SUN9I
+	default MACH_SUN9I || MACH_SUN8I
 	select ARM_CCI400_PORT_CTRL
 	select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index fc10e3a3268f..b4037b603897 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST	BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)	BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n)	BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL	(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)		(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)	BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL	0xf
 #define PRCM_PWROFF_GATING_REG(c)	(0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I	BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I	BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n)	BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)	(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG		0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)	(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)	BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG		0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC0	0xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC1	0x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
 	reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+	if (is_a83t) {
+		/* assert cpu power-on reset */
+		reg  = readl(r_cpucfg_base +
+			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+		writel(reg, r_cpucfg_base +
+		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* Cortex-A7: hold L1 reset disable signal low */
 	if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
 		reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
 	/* open power switch */
 	sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+	/* Handle A83T bit swap */
+	if (is_a83t) {
+		if (cpu == 0)
+			cpu = 4;
+	}
+
 	/* clear processor power gate */
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
+	/* Handle A83T bit swap */
+	if (is_a83t) {
+		if (cpu == 4)
+			cpu = 0;
+	}
+
 	/* de-assert processor power-on reset */
 	reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 	reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+	if (is_a83t) {
+		reg  = readl(r_cpucfg_base +
+			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+		writel(reg, r_cpucfg_base +
+		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* de-assert all processor resets */
 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
 	reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 	if (cluster >= SUNXI_NR_CLUSTERS)
 		return -EINVAL;
 
+	/* For A83T, assert cluster cores resets */
+	if (is_a83t) {
+		reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+		reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;   /* Core Reset    */
+		writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* assert ACINACTM */
 	reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
 	reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
@@ -226,6 +274,16 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 	reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
 	writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+	/* assert cluster cores resets */
+	if (is_a83t) {
+		reg  = readl(r_cpucfg_base +
+			     R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
+		writel(reg, r_cpucfg_base +
+		       R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+		udelay(10);
+	}
+
 	/* assert cluster resets */
 	reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
 	reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
@@ -256,7 +314,10 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
 	/* clear cluster power gate */
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
+	if (is_a83t)
+		reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
+	else
+		reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
@@ -453,7 +514,10 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
 	/* gate cluster power */
 	pr_debug("%s: gate cluster power\n", __func__);
 	reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-	reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
+	if (is_a83t)
+		reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
+	else
+		reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
 	writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
 	udelay(20);
 
@@ -535,8 +599,12 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
 	return !ret;
 }
 
-static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
+static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
 {
+	/* CPU0 hotplug not handled for sun8i-a83t */
+	if (is_a83t)
+		if (cpu == 0)
+			return false;
 	return true;
 }
 #endif
@@ -619,6 +687,7 @@ struct sunxi_mc_smp_nodes {
 	struct device_node *prcm_node;
 	struct device_node *cpucfg_node;
 	struct device_node *sram_node;
+	struct device_node *r_cpucfg_node;
 };
 
 /* This structure holds SoC-specific bits tied to an enable-method string. */
@@ -633,6 +702,7 @@ static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
 	of_node_put(nodes->prcm_node);
 	of_node_put(nodes->cpucfg_node);
 	of_node_put(nodes->sram_node);
+	of_node_put(nodes->r_cpucfg_node);
 	memset(nodes, 0, sizeof(*nodes));
 }
 
@@ -662,11 +732,42 @@ static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
 	return 0;
 }
 
+static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
+{
+	nodes->prcm_node = of_find_compatible_node(NULL, NULL,
+						   "allwinner,sun8i-a83t-r-ccu");
+	if (!nodes->prcm_node) {
+		pr_err("%s: PRCM not available\n", __func__);
+		return -ENODEV;
+	}
+
+	nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
+						     "allwinner,sun8i-a83t-cpucfg");
+	if (!nodes->cpucfg_node) {
+		pr_err("%s: CPUCFG not available\n", __func__);
+		return -ENODEV;
+	}
+
+	nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
+						       "allwinner,sun8i-a83t-r-cpucfg");
+	if (!nodes->r_cpucfg_node) {
+		pr_err("%s: RCPUCFG not available\n", __func__);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
 static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
 	{
 		.enable_method	= "allwinner,sun9i-a80-smp",
 		.get_smp_nodes	= sun9i_a80_get_smp_nodes,
 	},
+	{
+		.enable_method	= "allwinner,sun8i-a83t-smp",
+		.get_smp_nodes	= sun8i_a83t_get_smp_nodes,
+		.is_a83t	= true,
+	},
 };
 
 static int __init sunxi_mc_smp_init(void)
@@ -674,6 +775,7 @@ static int __init sunxi_mc_smp_init(void)
 	struct sunxi_mc_smp_nodes nodes = { 0 };
 	struct device_node *node;
 	struct resource res;
+	void __iomem *addr;
 	int i, ret;
 
 	/*
@@ -738,12 +840,23 @@ static int __init sunxi_mc_smp_init(void)
 		goto err_unmap_prcm;
 	}
 
-	sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
-						"sunxi-mc-smp");
-	if (IS_ERR(sram_b_smp_base)) {
-		ret = PTR_ERR(sram_b_smp_base);
-		pr_err("%s: failed to map secure SRAM\n", __func__);
-		goto err_unmap_release_cpucfg;
+	if (is_a83t) {
+		r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
+						      0, "sunxi-mc-smp");
+		if (IS_ERR(r_cpucfg_base)) {
+			ret = PTR_ERR(r_cpucfg_base);
+			pr_err("%s: failed to map R-CPUCFG registers\n",
+			       __func__);
+			goto err_unmap_release_cpucfg;
+		}
+	} else {
+		sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
+							"sunxi-mc-smp");
+		if (IS_ERR(sram_b_smp_base)) {
+			ret = PTR_ERR(sram_b_smp_base);
+			pr_err("%s: failed to map secure SRAM\n", __func__);
+			goto err_unmap_release_cpucfg;
+		}
 	}
 
 	/* Configure CCI-400 for boot cluster */
@@ -751,15 +864,18 @@ static int __init sunxi_mc_smp_init(void)
 	if (ret) {
 		pr_err("%s: failed to configure boot cluster: %d\n",
 		       __func__, ret);
-		goto err_unmap_release_secure_sram;
+		goto err_unmap_release_sram_rcpucfg;
 	}
 
 	/* We don't need the device nodes anymore */
 	sunxi_mc_smp_put_nodes(&nodes);
 
 	/* Set the hardware entry point address */
-	writel(__pa_symbol(sunxi_mc_smp_secondary_startup),
-	       prcm_base + PRCM_CPU_SOFT_ENTRY_REG);
+	if (is_a83t)
+		addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
+	else
+		addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
+	writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
 
 	/* Actually enable multi cluster SMP */
 	smp_set_ops(&sunxi_mc_smp_smp_ops);
@@ -768,9 +884,14 @@ static int __init sunxi_mc_smp_init(void)
 
 	return 0;
 
-err_unmap_release_secure_sram:
-	iounmap(sram_b_smp_base);
-	of_address_to_resource(nodes.sram_node, 0, &res);
+err_unmap_release_sram_rcpucfg:
+	if (is_a83t) {
+		iounmap(r_cpucfg_base);
+		of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
+	} else {
+		iounmap(sram_b_smp_base);
+		of_address_to_resource(nodes.sram_node, 0, &res);
+	}
 	release_mem_region(res.start, resource_size(&res));
 err_unmap_release_cpucfg:
 	iounmap(cpucfg_base);
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (9 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-01 12:31 ` [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
  11 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0669b8dc499d..2be23d600957 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0>;
 		};
 
@@ -75,6 +76,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <1>;
 		};
 
@@ -83,6 +85,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <2>;
 		};
 
@@ -91,6 +94,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <3>;
 		};
 
@@ -101,6 +105,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x100>;
 		};
 
@@ -109,6 +114,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x101>;
 		};
 
@@ -117,6 +123,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x102>;
 		};
 
@@ -125,6 +132,7 @@
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
+			enable-method = "allwinner,sun8i-a83t-smp";
 			reg = <0x103>;
 		};
 	};
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff
  2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
                   ` (10 preceding siblings ...)
  2018-05-01 12:31 ` [PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
@ 2018-05-01 12:31 ` Mylène Josserand
  2018-05-02  6:36   ` Simon Horman
  11 siblings, 1 reply; 20+ messages in thread
From: Mylène Josserand @ 2018-05-01 12:31 UTC (permalink / raw)
  To: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	horms, geert, magnus.damm
  Cc: linux-renesas-soc, devicetree, clabbe.montjoie, quentin.schulz,
	thomas.petazzoni, linux-arm-kernel, linux-kernel,
	mylene.josserand

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/mach-shmobile/common.h          |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S    | 22 +---------------------
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-ENTRY(shmobile_init_cntvoff)
-	/*
-	 * CNTVOFF has to be initialized either from non-secure Hypervisor
-	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-	 * then it should be handled by the secure code
-	 */
-	cps	#MON_MODE
-	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
-	orr	r0, r1, #1
-	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
-	instr_sync
-	mov	r0, #0
-	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
-	instr_sync
-	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
-	instr_sync
-	cps	#SVC_MODE
-	ret	lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-	bl	shmobile_init_cntvoff
+	bl	secure_cntvoff_init
 	b	secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
+#include <asm/secure_cntvoff.h>
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
 	void __iomem *base;
 	u32 freq;
 
-	shmobile_init_cntvoff();
+	secure_cntvoff_init();
 
 	if (of_machine_is_compatible("renesas,r8a7745") ||
 	    of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff
  2018-05-01 12:31 ` [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
@ 2018-05-02  6:36   ` Simon Horman
  2018-05-02 13:18     ` Maxime Ripard
  0 siblings, 1 reply; 20+ messages in thread
From: Simon Horman @ 2018-05-02  6:36 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, maxime.ripard, wens, marc.zyngier, mark.rutland, robh+dt,
	geert, magnus.damm, linux-renesas-soc, devicetree,
	clabbe.montjoie, quentin.schulz, thomas.petazzoni,
	linux-arm-kernel, linux-kernel

On Tue, May 01, 2018 at 02:31:31PM +0200, Mylène Josserand wrote:
> Now that a common function is available for CNTVOFF's
> initialization, let's convert shmobile-apmu code to use
> this function.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

Acked-by: Simon Horman <horms+renesas@verge.net.au>

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v8 07/12] ARM: sunxi: Add initialization of CNTVOFF
  2018-05-01 12:31 ` [PATCH v8 07/12] ARM: sunxi: " Mylène Josserand
@ 2018-05-02 13:08   ` Maxime Ripard
  2018-05-02 13:28     ` Mylène Josserand
  0 siblings, 1 reply; 20+ messages in thread
From: Maxime Ripard @ 2018-05-02 13:08 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

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On Tue, May 01, 2018 at 02:31:26PM +0200, Mylène Josserand wrote:
> Add the initialization of CNTVOFF for sun8i-a83t.
> 
> For boot CPU, create a new machine that handles this
> function's call in an "init_early" callback. We need to initialize
> CNTVOFF before the arch timer's initialization otherwise, it will
> not be taken into account and fails to boot correctly.
> Because of that, this function can't be called in SMP's early_initcall
> function which is called after timer's init.
> 
> For secondary CPUs, add this function into secondary_startup
> assembly entry.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  arch/arm/mach-sunxi/headsmp.S |  1 +
>  arch/arm/mach-sunxi/sunxi.c   | 20 +++++++++++++++++++-
>  2 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> index 37dc772701f3..32d76be98541 100644
> --- a/arch/arm/mach-sunxi/headsmp.S
> +++ b/arch/arm/mach-sunxi/headsmp.S
> @@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
>  
>  ENTRY(sunxi_mc_smp_secondary_startup)
>  	bl	sunxi_mc_smp_cluster_cache_enable
> +	bl	secure_cntvoff_init
>  	b	secondary_startup
>  ENDPROC(sunxi_mc_smp_secondary_startup)
>  
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index 5e9602ce1573..2770a31a9278 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -16,6 +16,7 @@
>  #include <linux/platform_device.h>
>  
>  #include <asm/mach/arch.h>
> +#include <asm/secure_cntvoff.h>
>  
>  static const char * const sunxi_board_dt_compat[] = {
>  	"allwinner,sun4i-a10",
> @@ -62,7 +63,6 @@ MACHINE_END
>  static const char * const sun8i_board_dt_compat[] = {
>  	"allwinner,sun8i-a23",
>  	"allwinner,sun8i-a33",
> -	"allwinner,sun8i-a83t",
>  	"allwinner,sun8i-h2-plus",
>  	"allwinner,sun8i-h3",
>  	"allwinner,sun8i-r40",
> @@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
>  	.dt_compat	= sun8i_board_dt_compat,
>  MACHINE_END
>  
> +void __init sun8i_a83t_cntvoff_init(void)
> +{
> +#ifdef CONFIG_SMP
> +	secure_cntvoff_init();
> +#endif
> +}
> +
> +static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
> +	"allwinner,sun8i-a83t",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")

I put my Acked-by on the condition that you would fix this. And you
still didn't.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field
  2018-05-01 12:31 ` [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field Mylène Josserand
@ 2018-05-02 13:09   ` Maxime Ripard
  0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2018-05-02 13:09 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

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On Tue, May 01, 2018 at 02:31:28PM +0200, Mylène Josserand wrote:
> To prepare the support of sun8i-a83t, add a field in the smp_data
> structure to know if we are on sun9i-a80 or sun8i-a83t.
> 
> Add also a global variable to retrieve which architecture we are
> having.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T
  2018-05-01 12:31 ` [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T Mylène Josserand
@ 2018-05-02 13:14   ` Maxime Ripard
  0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2018-05-02 13:14 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

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On Tue, May 01, 2018 at 02:31:29PM +0200, Mylène Josserand wrote:
> Add the support for A83T.
> 
> A83T SoC has an additional register than A80 to handle CPU configurations:
> R_CPUS_CFG. Information about the register comes from Allwinner's BSP
> driver.
> An important difference is the Power Off Gating register for clusters
> which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
> There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
> handled.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff
  2018-05-02  6:36   ` Simon Horman
@ 2018-05-02 13:18     ` Maxime Ripard
  0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2018-05-02 13:18 UTC (permalink / raw)
  To: Simon Horman
  Cc: Mylène Josserand, linux, wens, marc.zyngier, mark.rutland,
	robh+dt, geert, magnus.damm, linux-renesas-soc, devicetree,
	clabbe.montjoie, quentin.schulz, thomas.petazzoni,
	linux-arm-kernel, linux-kernel

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Hi Simon,

On Wed, May 02, 2018 at 08:36:39AM +0200, Simon Horman wrote:
> On Tue, May 01, 2018 at 02:31:31PM +0200, Mylène Josserand wrote:
> > Now that a common function is available for CNTVOFF's
> > initialization, let's convert shmobile-apmu code to use
> > this function.
> > 
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Acked-by: Simon Horman <horms+renesas@verge.net.au>

For the sake of bisectability (and to ease the merge), is it ok if we
take it through the sunxi (and then arm-soc) tree?

Thanks!
Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file
  2018-05-01 12:31 ` [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
@ 2018-05-02 13:18   ` Maxime Ripard
  0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2018-05-02 13:18 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

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On Tue, May 01, 2018 at 02:31:21PM +0200, Mylène Josserand wrote:
> Move the assembly code for cluster cache enabling and resuming
> into an assembly file instead of having it directly in C code.
> 
> Remove the CFLAGS because we are using the ARM directive "arch"
> instead.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v8 07/12] ARM: sunxi: Add initialization of CNTVOFF
  2018-05-02 13:08   ` Maxime Ripard
@ 2018-05-02 13:28     ` Mylène Josserand
  0 siblings, 0 replies; 20+ messages in thread
From: Mylène Josserand @ 2018-05-02 13:28 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: linux, wens, marc.zyngier, mark.rutland, robh+dt, horms, geert,
	magnus.damm, linux-renesas-soc, devicetree, clabbe.montjoie,
	quentin.schulz, thomas.petazzoni, linux-arm-kernel, linux-kernel

Hi Maxime,

On Wed, 2 May 2018 15:08:42 +0200
Maxime Ripard <maxime.ripard@bootlin.com> wrote:

> On Tue, May 01, 2018 at 02:31:26PM +0200, Mylène Josserand wrote:
> > Add the initialization of CNTVOFF for sun8i-a83t.
> > 
> > For boot CPU, create a new machine that handles this
> > function's call in an "init_early" callback. We need to initialize
> > CNTVOFF before the arch timer's initialization otherwise, it will
> > not be taken into account and fails to boot correctly.
> > Because of that, this function can't be called in SMP's early_initcall
> > function which is called after timer's init.
> > 
> > For secondary CPUs, add this function into secondary_startup
> > assembly entry.
> > 
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> > Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> >  arch/arm/mach-sunxi/headsmp.S |  1 +
> >  arch/arm/mach-sunxi/sunxi.c   | 20 +++++++++++++++++++-
> >  2 files changed, 20 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> > index 37dc772701f3..32d76be98541 100644
> > --- a/arch/arm/mach-sunxi/headsmp.S
> > +++ b/arch/arm/mach-sunxi/headsmp.S
> > @@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
> >  
> >  ENTRY(sunxi_mc_smp_secondary_startup)
> >  	bl	sunxi_mc_smp_cluster_cache_enable
> > +	bl	secure_cntvoff_init
> >  	b	secondary_startup
> >  ENDPROC(sunxi_mc_smp_secondary_startup)
> >  
> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> > index 5e9602ce1573..2770a31a9278 100644
> > --- a/arch/arm/mach-sunxi/sunxi.c
> > +++ b/arch/arm/mach-sunxi/sunxi.c
> > @@ -16,6 +16,7 @@
> >  #include <linux/platform_device.h>
> >  
> >  #include <asm/mach/arch.h>
> > +#include <asm/secure_cntvoff.h>
> >  
> >  static const char * const sunxi_board_dt_compat[] = {
> >  	"allwinner,sun4i-a10",
> > @@ -62,7 +63,6 @@ MACHINE_END
> >  static const char * const sun8i_board_dt_compat[] = {
> >  	"allwinner,sun8i-a23",
> >  	"allwinner,sun8i-a33",
> > -	"allwinner,sun8i-a83t",
> >  	"allwinner,sun8i-h2-plus",
> >  	"allwinner,sun8i-h3",
> >  	"allwinner,sun8i-r40",
> > @@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
> >  	.dt_compat	= sun8i_board_dt_compat,
> >  MACHINE_END
> >  
> > +void __init sun8i_a83t_cntvoff_init(void)
> > +{
> > +#ifdef CONFIG_SMP
> > +	secure_cntvoff_init();
> > +#endif
> > +}
> > +
> > +static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
> > +	"allwinner,sun8i-a83t",
> > +	NULL,
> > +};
> > +
> > +DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")  
> 
> I put my Acked-by on the condition that you would fix this. And you
> still didn't.

Grrr, stupid me.
I modified the names of functions but I forgot the machine. Sorry
about that.

Best regards,

-- 
Mylène Josserand, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2018-05-02 13:28 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 01/12] ARM: Allow this header to be included by assembly files Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
2018-05-02 13:18   ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 07/12] ARM: sunxi: " Mylène Josserand
2018-05-02 13:08   ` Maxime Ripard
2018-05-02 13:28     ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field Mylène Josserand
2018-05-02 13:09   ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T Mylène Josserand
2018-05-02 13:14   ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
2018-05-02  6:36   ` Simon Horman
2018-05-02 13:18     ` Maxime Ripard

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