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From: Tony Lindgren <tony@atomide.com>
To: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: bcousson@baylibre.com, linux-omap@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	j-keerthy@ti.com
Subject: Re: [PATCH 0/4] ARM: dts: am437x boards: Correct (again) tps65218 irq type
Date: Tue, 8 May 2018 07:16:00 -0700	[thread overview]
Message-ID: <20180508141600.GT98604@atomide.com> (raw)
In-Reply-To: <20180508132053.5471-1-peter.ujfalusi@ti.com>

* Peter Ujfalusi <peter.ujfalusi@ti.com> [180508 13:22]:
> Hi,
> 
> While based on the datasheet of tps65218 the INT is low active, the GIC_SPI
> does not support anythin but IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING:
> 
> [    2.761814] genirq: Setting trigger mode 8 for irq 102 failed (irq_chip_set_type_parent+0x0/0x30)
> [    2.770913] tps65218 0-0024: Failed to request IRQ 102 for tps65218: -22
> [    2.777854] tps65218: probe of 0-0024 failed with error -22

So does the tps65218 have some register to control the interrupt
direction or is it's datasheet wrong?

BTW, ADC might be a good test case for PMIC interrupt if it has one.

> Use LEVEL_HIGH for the interrupt as it looks to be the correct setting:
> INTn of tps65218 is connected to NMIn of the SoC.
> 
> The offending patches are only in linux-next.

OK

Regards,

Tony

  parent reply	other threads:[~2018-05-08 14:16 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-08 13:20 Peter Ujfalusi
2018-05-08 13:20 ` [PATCH 1/4] ARM: dts: am437x-gp-evm: Fixup " Peter Ujfalusi
2018-05-08 13:20 ` [PATCH 2/4] ARM: dts: am437x-cm-t43: " Peter Ujfalusi
2018-05-08 13:20 ` [PATCH 3/4] ARM: dts: am437x-epos-evm: " Peter Ujfalusi
2018-05-08 13:20 ` [PATCH 4/4] Revert "ARM: dts: am437x-sk-evm: Correct tps65218 irq type" Peter Ujfalusi
2018-05-08 14:16 ` Tony Lindgren [this message]
2018-05-09  4:00   ` [PATCH 0/4] ARM: dts: am437x boards: Correct (again) tps65218 irq type Keerthy
2018-05-15 18:15     ` Tony Lindgren

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