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From: Jeremy Linton <jeremy.linton@arm.com>
To: linux-acpi@vger.kernel.org
Cc: Sudeep.Holla@arm.com, linux-arm-kernel@lists.infradead.org,
	Lorenzo.Pieralisi@arm.com, hanjun.guo@linaro.org,
	rjw@rjwysocki.net, Will.Deacon@arm.com, Catalin.Marinas@arm.com,
	gregkh@linuxfoundation.org, Mark.Rutland@arm.com,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	wangxiongfeng2@huawei.com, vkilari@codeaurora.org,
	ahs3@redhat.com, Dietmar.Eggemann@arm.com,
	Morten.Rasmussen@arm.com, palmer@sifive.com, lenb@kernel.org,
	john.garry@huawei.com, austinwc@codeaurora.org,
	tnowicki@caviumnetworks.com, jhugo@codeaurora.org,
	ard.biesheuvel@linaro.org, Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v9 12/12] arm64: topology: divorce MC scheduling domain from core_siblings
Date: Fri, 11 May 2018 18:58:07 -0500	[thread overview]
Message-ID: <20180511235807.30834-13-jeremy.linton@arm.com> (raw)
In-Reply-To: <20180511235807.30834-1-jeremy.linton@arm.com>

Now that we have an accurate view of the physical topology
we need to represent it correctly to the scheduler. Generally MC
should equal the LLC in the system, but there are a number of
special cases that need to be dealt with.

In the case of NUMA in socket, we need to assure that the sched
domain we build for the MC layer isn't larger than the DIE above it.
Similarly for LLC's that might exist in cross socket interconnect or
directory hardware we need to assure that MC is shrunk to the socket
or NUMA node.

This patch builds a sibling mask for the LLC, and then picks the
smallest of LLC, socket siblings, or NUMA node siblings, which
gives us the behavior described above. This is ever so slightly
different than the similar alternative where we look for a cache
layer less than or equal to the socket/NUMA siblings.

The logic to pick the MC layer affects all arm64 machines, but
only changes the behavior for DT/MPIDR systems if the NUMA domain
is smaller than the core siblings (generally set to the cluster).
Potentially this fixes a possible bug in DT systems, but really
it only affects ACPI systems where the core siblings is correctly
set to the socket siblings. Thus all currently available ACPI
systems should have MC equal to LLC, including the NUMA in socket
machines where the LLC is partitioned between the NUMA nodes.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Vijaya Kumar K <vkilari@codeaurora.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Tested-by: Tomasz Nowicki <Tomasz.Nowicki@cavium.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Morten Rasmussen <morten.rasmussen@arm.com>
---
 arch/arm64/include/asm/topology.h |  2 ++
 arch/arm64/kernel/topology.c      | 36 +++++++++++++++++++++++++++++++++++-
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
index 6b10459e6905..df48212f767b 100644
--- a/arch/arm64/include/asm/topology.h
+++ b/arch/arm64/include/asm/topology.h
@@ -8,8 +8,10 @@ struct cpu_topology {
 	int thread_id;
 	int core_id;
 	int package_id;
+	int llc_id;
 	cpumask_t thread_sibling;
 	cpumask_t core_sibling;
+	cpumask_t llc_siblings;
 };
 
 extern struct cpu_topology cpu_topology[NR_CPUS];
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index 047d98e68502..7415c166281f 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -13,6 +13,7 @@
 
 #include <linux/acpi.h>
 #include <linux/arch_topology.h>
+#include <linux/cacheinfo.h>
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
 #include <linux/init.h>
@@ -214,7 +215,19 @@ EXPORT_SYMBOL_GPL(cpu_topology);
 
 const struct cpumask *cpu_coregroup_mask(int cpu)
 {
-	return &cpu_topology[cpu].core_sibling;
+	const cpumask_t *core_mask = cpumask_of_node(cpu_to_node(cpu));
+
+	/* Find the smaller of NUMA, core or LLC siblings */
+	if (cpumask_subset(&cpu_topology[cpu].core_sibling, core_mask)) {
+		/* not numa in package, lets use the package siblings */
+		core_mask = &cpu_topology[cpu].core_sibling;
+	}
+	if (cpu_topology[cpu].llc_id != -1) {
+		if (cpumask_subset(&cpu_topology[cpu].llc_siblings, core_mask))
+			core_mask = &cpu_topology[cpu].llc_siblings;
+	}
+
+	return core_mask;
 }
 
 static void update_siblings_masks(unsigned int cpuid)
@@ -226,6 +239,9 @@ static void update_siblings_masks(unsigned int cpuid)
 	for_each_possible_cpu(cpu) {
 		cpu_topo = &cpu_topology[cpu];
 
+		if (cpuid_topo->llc_id == cpu_topo->llc_id)
+			cpumask_set_cpu(cpu, &cpuid_topo->llc_siblings);
+
 		if (cpuid_topo->package_id != cpu_topo->package_id)
 			continue;
 
@@ -291,6 +307,10 @@ static void __init reset_cpu_topology(void)
 		cpu_topo->core_id = 0;
 		cpu_topo->package_id = -1;
 
+		cpu_topo->llc_id = -1;
+		cpumask_clear(&cpu_topo->llc_siblings);
+		cpumask_set_cpu(cpu, &cpu_topo->llc_siblings);
+
 		cpumask_clear(&cpu_topo->core_sibling);
 		cpumask_set_cpu(cpu, &cpu_topo->core_sibling);
 		cpumask_clear(&cpu_topo->thread_sibling);
@@ -311,6 +331,8 @@ static int __init parse_acpi_topology(void)
 	is_threaded = read_cpuid_mpidr() & MPIDR_MT_BITMASK;
 
 	for_each_possible_cpu(cpu) {
+		int i, cache_id;
+
 		topology_id = find_acpi_cpu_topology(cpu, 0);
 		if (topology_id < 0)
 			return topology_id;
@@ -325,6 +347,18 @@ static int __init parse_acpi_topology(void)
 		}
 		topology_id = find_acpi_cpu_topology_package(cpu);
 		cpu_topology[cpu].package_id = topology_id;
+
+		i = acpi_find_last_cache_level(cpu);
+
+		if (i > 0) {
+			/*
+			 * this is the only part of cpu_topology that has
+			 * a direct relationship with the cache topology
+			 */
+			cache_id = find_acpi_cpu_cache_topology(cpu, i);
+			if (cache_id > 0)
+				cpu_topology[cpu].llc_id = cache_id;
+		}
 	}
 
 	return 0;
-- 
2.13.6

  parent reply	other threads:[~2018-05-11 23:58 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-11 23:57 [PATCH v9 00/12] Support PPTT for ARM64 Jeremy Linton
2018-05-11 23:57 ` [PATCH v9 01/12] drivers: base: cacheinfo: move cache_setup_of_node() Jeremy Linton
2018-05-11 23:57 ` [PATCH v9 02/12] drivers: base: cacheinfo: setup DT cache properties early Jeremy Linton
2018-05-15 17:15   ` Jeremy Linton
2018-05-15 19:32     ` Andy Shevchenko
2018-05-16 10:56       ` Sudeep Holla
2018-05-17 15:47         ` Sudeep Holla
2018-05-18 21:50           ` Andy Shevchenko
2018-05-21  9:27             ` Sudeep Holla
2018-05-21 10:15               ` Sudeep Holla
2018-05-21 10:32       ` [PATCH] drivers: base: cacheinfo: use OF property_read_u64 instead of get_property,read_number Sudeep Holla
2018-05-21 12:53         ` [PATCH v2] drivers: base: cacheinfo: use OF property_read_u32 " Sudeep Holla
2018-06-05 16:21           ` Andy Shevchenko
2018-06-05 16:26             ` Sudeep Holla
2018-06-05 16:34               ` Andy Shevchenko
2018-05-17  6:54     ` [PATCH v9 02/12] drivers: base: cacheinfo: setup DT cache properties early Greg KH
2018-05-17  9:08       ` Sudeep Holla
2018-05-17  9:35         ` Greg KH
2018-05-11 23:57 ` [PATCH v9 03/12] cacheinfo: rename of_node to fw_token Jeremy Linton
2018-05-11 23:57 ` [PATCH v9 04/12] arm64/acpi: Create arch specific cpu to acpi id helper Jeremy Linton
2018-05-14 14:41   ` Sudeep Holla
2018-05-11 23:58 ` [PATCH v9 05/12] ACPI/PPTT: Add Processor Properties Topology Table parsing Jeremy Linton
2018-05-12 10:09   ` Rafael J. Wysocki
2018-05-15 21:42     ` Jeremy Linton
2018-05-16  8:24       ` Rafael J. Wysocki
2018-05-11 23:58 ` [PATCH v9 06/12] ACPI: Enable PPTT support on ARM64 Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 07/12] drivers: base cacheinfo: Add support for ACPI based firmware tables Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 08/12] arm64: " Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 09/12] arm64: topology: rename cluster_id Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 10/12] arm64: topology: enable ACPI/PPTT based CPU topology Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 11/12] ACPI: Add PPTT to injectable table list Jeremy Linton
2018-05-12 10:10   ` Rafael J. Wysocki
2018-05-11 23:58 ` Jeremy Linton [this message]
2018-05-17 17:05 ` [PATCH v9 00/12] Support PPTT for ARM64 Catalin Marinas
2018-05-29 10:48   ` Geert Uytterhoeven
2018-05-29 11:14     ` Sudeep Holla
2018-05-29 11:56       ` Geert Uytterhoeven
2018-05-29 13:18         ` Sudeep Holla
2018-05-29 15:08           ` Will Deacon
2018-05-29 15:51             ` Geert Uytterhoeven
2018-05-29 17:08               ` Robin Murphy
2018-05-29 17:18                 ` Geert Uytterhoeven
2018-05-29 17:31                 ` Sudeep Holla
2018-05-29 20:16               ` Will Deacon
2018-05-29 20:48                 ` Jeremy Linton
2018-05-29 21:52               ` Jeremy Linton
2018-05-30 13:24                 ` Sudeep Holla
2018-05-29 15:23           ` Jeremy Linton
2018-05-29 15:50           ` Geert Uytterhoeven
2018-05-30  8:52             ` Morten Rasmussen
2018-06-05 13:55     ` [PATCH 1/3] Revert "arm64: topology: divorce MC scheduling domain from core_siblings" Sudeep Holla
2018-06-05 13:55       ` [PATCH 2/3] ACPI / PPTT: fix build when CONFIG_ACPI_PPTT is not enabled Sudeep Holla
2018-06-05 13:55       ` [PATCH 3/3] arm64: disable ACPI PPTT support temporarily Sudeep Holla
2018-06-05 14:09       ` [PATCH 1/3] Revert "arm64: topology: divorce MC scheduling domain from core_siblings" Geert Uytterhoeven
2018-06-05 14:12         ` Sudeep Holla
2018-06-04 15:12   ` [PATCH v9 00/12] Support PPTT for ARM64 Catalin Marinas

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