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From: Jeremy Linton <jeremy.linton@arm.com>
To: linux-acpi@vger.kernel.org
Cc: Sudeep.Holla@arm.com, linux-arm-kernel@lists.infradead.org,
	Lorenzo.Pieralisi@arm.com, hanjun.guo@linaro.org,
	rjw@rjwysocki.net, Will.Deacon@arm.com, Catalin.Marinas@arm.com,
	gregkh@linuxfoundation.org, Mark.Rutland@arm.com,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	wangxiongfeng2@huawei.com, vkilari@codeaurora.org,
	ahs3@redhat.com, Dietmar.Eggemann@arm.com,
	Morten.Rasmussen@arm.com, palmer@sifive.com, lenb@kernel.org,
	john.garry@huawei.com, austinwc@codeaurora.org,
	tnowicki@caviumnetworks.com, jhugo@codeaurora.org,
	ard.biesheuvel@linaro.org, Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v9 02/12] drivers: base: cacheinfo: setup DT cache properties early
Date: Fri, 11 May 2018 18:57:57 -0500	[thread overview]
Message-ID: <20180511235807.30834-3-jeremy.linton@arm.com> (raw)
In-Reply-To: <20180511235807.30834-1-jeremy.linton@arm.com>

The original intent in cacheinfo was that an architecture
specific populate_cache_leaves() would probe the hardware
and then cache_shared_cpu_map_setup() and
cache_override_properties() would provide firmware help to
extend/expand upon what was probed. Arm64 was really
the only architecture that was working this way, and
with the removal of most of the hardware probing logic it
became clear that it was possible to simplify the logic a bit.

This patch combines the walk of the DT nodes with the
code updating the cache size/line_size and nr_sets.
cache_override_properties() (which was DT specific) is
then removed. The result is that cacheinfo.of_node is
no longer used as a temporary place to hold DT references
for future calls that update cache properties. That change
helps to clarify its one remaining use (matching
cacheinfo nodes that represent shared caches) which
will be used by the ACPI/PPTT code in the following patches.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Vijaya Kumar K <vkilari@codeaurora.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Tested-by: Tomasz Nowicki <Tomasz.Nowicki@cavium.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/riscv/kernel/cacheinfo.c |  1 -
 drivers/base/cacheinfo.c      | 65 +++++++++++++++++++------------------------
 2 files changed, 29 insertions(+), 37 deletions(-)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 10ed2749e246..0bc86e5f8f3f 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -20,7 +20,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
 			 struct device_node *node,
 			 enum cache_type type, unsigned int level)
 {
-	this_leaf->of_node = node;
 	this_leaf->level = level;
 	this_leaf->type = type;
 	/* not a sector cache */
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 09ccef7ddc99..a872523e8951 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -71,7 +71,7 @@ static inline int get_cacheinfo_idx(enum cache_type type)
 	return type;
 }
 
-static void cache_size(struct cacheinfo *this_leaf)
+static void cache_size(struct cacheinfo *this_leaf, struct device_node *np)
 {
 	const char *propname;
 	const __be32 *cache_size;
@@ -80,13 +80,14 @@ static void cache_size(struct cacheinfo *this_leaf)
 	ct_idx = get_cacheinfo_idx(this_leaf->type);
 	propname = cache_type_info[ct_idx].size_prop;
 
-	cache_size = of_get_property(this_leaf->of_node, propname, NULL);
+	cache_size = of_get_property(np, propname, NULL);
 	if (cache_size)
 		this_leaf->size = of_read_number(cache_size, 1);
 }
 
 /* not cache_line_size() because that's a macro in include/linux/cache.h */
-static void cache_get_line_size(struct cacheinfo *this_leaf)
+static void cache_get_line_size(struct cacheinfo *this_leaf,
+				struct device_node *np)
 {
 	const __be32 *line_size;
 	int i, lim, ct_idx;
@@ -98,7 +99,7 @@ static void cache_get_line_size(struct cacheinfo *this_leaf)
 		const char *propname;
 
 		propname = cache_type_info[ct_idx].line_size_props[i];
-		line_size = of_get_property(this_leaf->of_node, propname, NULL);
+		line_size = of_get_property(np, propname, NULL);
 		if (line_size)
 			break;
 	}
@@ -107,7 +108,7 @@ static void cache_get_line_size(struct cacheinfo *this_leaf)
 		this_leaf->coherency_line_size = of_read_number(line_size, 1);
 }
 
-static void cache_nr_sets(struct cacheinfo *this_leaf)
+static void cache_nr_sets(struct cacheinfo *this_leaf, struct device_node *np)
 {
 	const char *propname;
 	const __be32 *nr_sets;
@@ -116,7 +117,7 @@ static void cache_nr_sets(struct cacheinfo *this_leaf)
 	ct_idx = get_cacheinfo_idx(this_leaf->type);
 	propname = cache_type_info[ct_idx].nr_sets_prop;
 
-	nr_sets = of_get_property(this_leaf->of_node, propname, NULL);
+	nr_sets = of_get_property(np, propname, NULL);
 	if (nr_sets)
 		this_leaf->number_of_sets = of_read_number(nr_sets, 1);
 }
@@ -135,32 +136,27 @@ static void cache_associativity(struct cacheinfo *this_leaf)
 		this_leaf->ways_of_associativity = (size / nr_sets) / line_size;
 }
 
-static bool cache_node_is_unified(struct cacheinfo *this_leaf)
+static bool cache_node_is_unified(struct cacheinfo *this_leaf,
+				  struct device_node *np)
 {
-	return of_property_read_bool(this_leaf->of_node, "cache-unified");
+	return of_property_read_bool(np, "cache-unified");
 }
 
-static void cache_of_override_properties(unsigned int cpu)
+static void cache_of_set_props(struct cacheinfo *this_leaf,
+			       struct device_node *np)
 {
-	int index;
-	struct cacheinfo *this_leaf;
-	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
-
-	for (index = 0; index < cache_leaves(cpu); index++) {
-		this_leaf = this_cpu_ci->info_list + index;
-		/*
-		 * init_cache_level must setup the cache level correctly
-		 * overriding the architecturally specified levels, so
-		 * if type is NONE at this stage, it should be unified
-		 */
-		if (this_leaf->type == CACHE_TYPE_NOCACHE &&
-		    cache_node_is_unified(this_leaf))
-			this_leaf->type = CACHE_TYPE_UNIFIED;
-		cache_size(this_leaf);
-		cache_get_line_size(this_leaf);
-		cache_nr_sets(this_leaf);
-		cache_associativity(this_leaf);
-	}
+	/*
+	 * init_cache_level must setup the cache level correctly
+	 * overriding the architecturally specified levels, so
+	 * if type is NONE at this stage, it should be unified
+	 */
+	if (this_leaf->type == CACHE_TYPE_NOCACHE &&
+	    cache_node_is_unified(this_leaf, np))
+		this_leaf->type = CACHE_TYPE_UNIFIED;
+	cache_size(this_leaf, np);
+	cache_get_line_size(this_leaf, np);
+	cache_nr_sets(this_leaf, np);
+	cache_associativity(this_leaf);
 }
 
 static int cache_setup_of_node(unsigned int cpu)
@@ -193,6 +189,7 @@ static int cache_setup_of_node(unsigned int cpu)
 			np = of_node_get(np);/* cpu node itself */
 		if (!np)
 			break;
+		cache_of_set_props(this_leaf, np);
 		this_leaf->of_node = np;
 		index++;
 	}
@@ -203,7 +200,6 @@ static int cache_setup_of_node(unsigned int cpu)
 	return 0;
 }
 #else
-static void cache_of_override_properties(unsigned int cpu) { }
 static inline int cache_setup_of_node(unsigned int cpu) { return 0; }
 static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf,
 					   struct cacheinfo *sib_leaf)
@@ -286,12 +282,6 @@ static void cache_shared_cpu_map_remove(unsigned int cpu)
 	}
 }
 
-static void cache_override_properties(unsigned int cpu)
-{
-	if (of_have_populated_dt())
-		return cache_of_override_properties(cpu);
-}
-
 static void free_cache_attributes(unsigned int cpu)
 {
 	if (!per_cpu_cacheinfo(cpu))
@@ -325,6 +315,10 @@ static int detect_cache_attributes(unsigned int cpu)
 	if (per_cpu_cacheinfo(cpu) == NULL)
 		return -ENOMEM;
 
+	/*
+	 * populate_cache_leaves() may completely setup the cache leaves and
+	 * shared_cpu_map or it may leave it partially setup.
+	 */
 	ret = populate_cache_leaves(cpu);
 	if (ret)
 		goto free_ci;
@@ -338,7 +332,6 @@ static int detect_cache_attributes(unsigned int cpu)
 		goto free_ci;
 	}
 
-	cache_override_properties(cpu);
 	return 0;
 
 free_ci:
-- 
2.13.6

  parent reply	other threads:[~2018-05-11 23:57 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-11 23:57 [PATCH v9 00/12] Support PPTT for ARM64 Jeremy Linton
2018-05-11 23:57 ` [PATCH v9 01/12] drivers: base: cacheinfo: move cache_setup_of_node() Jeremy Linton
2018-05-11 23:57 ` Jeremy Linton [this message]
2018-05-15 17:15   ` [PATCH v9 02/12] drivers: base: cacheinfo: setup DT cache properties early Jeremy Linton
2018-05-15 19:32     ` Andy Shevchenko
2018-05-16 10:56       ` Sudeep Holla
2018-05-17 15:47         ` Sudeep Holla
2018-05-18 21:50           ` Andy Shevchenko
2018-05-21  9:27             ` Sudeep Holla
2018-05-21 10:15               ` Sudeep Holla
2018-05-21 10:32       ` [PATCH] drivers: base: cacheinfo: use OF property_read_u64 instead of get_property,read_number Sudeep Holla
2018-05-21 12:53         ` [PATCH v2] drivers: base: cacheinfo: use OF property_read_u32 " Sudeep Holla
2018-06-05 16:21           ` Andy Shevchenko
2018-06-05 16:26             ` Sudeep Holla
2018-06-05 16:34               ` Andy Shevchenko
2018-05-17  6:54     ` [PATCH v9 02/12] drivers: base: cacheinfo: setup DT cache properties early Greg KH
2018-05-17  9:08       ` Sudeep Holla
2018-05-17  9:35         ` Greg KH
2018-05-11 23:57 ` [PATCH v9 03/12] cacheinfo: rename of_node to fw_token Jeremy Linton
2018-05-11 23:57 ` [PATCH v9 04/12] arm64/acpi: Create arch specific cpu to acpi id helper Jeremy Linton
2018-05-14 14:41   ` Sudeep Holla
2018-05-11 23:58 ` [PATCH v9 05/12] ACPI/PPTT: Add Processor Properties Topology Table parsing Jeremy Linton
2018-05-12 10:09   ` Rafael J. Wysocki
2018-05-15 21:42     ` Jeremy Linton
2018-05-16  8:24       ` Rafael J. Wysocki
2018-05-11 23:58 ` [PATCH v9 06/12] ACPI: Enable PPTT support on ARM64 Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 07/12] drivers: base cacheinfo: Add support for ACPI based firmware tables Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 08/12] arm64: " Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 09/12] arm64: topology: rename cluster_id Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 10/12] arm64: topology: enable ACPI/PPTT based CPU topology Jeremy Linton
2018-05-11 23:58 ` [PATCH v9 11/12] ACPI: Add PPTT to injectable table list Jeremy Linton
2018-05-12 10:10   ` Rafael J. Wysocki
2018-05-11 23:58 ` [PATCH v9 12/12] arm64: topology: divorce MC scheduling domain from core_siblings Jeremy Linton
2018-05-17 17:05 ` [PATCH v9 00/12] Support PPTT for ARM64 Catalin Marinas
2018-05-29 10:48   ` Geert Uytterhoeven
2018-05-29 11:14     ` Sudeep Holla
2018-05-29 11:56       ` Geert Uytterhoeven
2018-05-29 13:18         ` Sudeep Holla
2018-05-29 15:08           ` Will Deacon
2018-05-29 15:51             ` Geert Uytterhoeven
2018-05-29 17:08               ` Robin Murphy
2018-05-29 17:18                 ` Geert Uytterhoeven
2018-05-29 17:31                 ` Sudeep Holla
2018-05-29 20:16               ` Will Deacon
2018-05-29 20:48                 ` Jeremy Linton
2018-05-29 21:52               ` Jeremy Linton
2018-05-30 13:24                 ` Sudeep Holla
2018-05-29 15:23           ` Jeremy Linton
2018-05-29 15:50           ` Geert Uytterhoeven
2018-05-30  8:52             ` Morten Rasmussen
2018-06-05 13:55     ` [PATCH 1/3] Revert "arm64: topology: divorce MC scheduling domain from core_siblings" Sudeep Holla
2018-06-05 13:55       ` [PATCH 2/3] ACPI / PPTT: fix build when CONFIG_ACPI_PPTT is not enabled Sudeep Holla
2018-06-05 13:55       ` [PATCH 3/3] arm64: disable ACPI PPTT support temporarily Sudeep Holla
2018-06-05 14:09       ` [PATCH 1/3] Revert "arm64: topology: divorce MC scheduling domain from core_siblings" Geert Uytterhoeven
2018-06-05 14:12         ` Sudeep Holla
2018-06-04 15:12   ` [PATCH v9 00/12] Support PPTT for ARM64 Catalin Marinas

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