From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751839AbeELPAj convert rfc822-to-8bit (ORCPT ); Sat, 12 May 2018 11:00:39 -0400 Received: from mail.bootlin.com ([62.4.15.54]:36706 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750847AbeELPAi (ORCPT ); Sat, 12 May 2018 11:00:38 -0400 Date: Sat, 12 May 2018 17:00:34 +0200 From: Boris Brezillon To: Paul Cercueil Cc: Mark Rutland , David Woodhouse , linux-mtd@lists.infradead.org, Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Brian Norris , Richard Weinberger , Boris Brezillon , Marek Vasut Subject: Re: [PATCH] mtd: nand: Add support for reading ooblayout from device tree Message-ID: <20180512170034.12779313@bbrezillon> In-Reply-To: <1526135906.4971.0@smtp.crapouillou.net> References: <20180512115551.56C6E20787@mail.bootlin.com> <20180512154223.3b81c7f7@bbrezillon> <1526135906.4971.0@smtp.crapouillou.net> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 12 May 2018 11:38:26 -0300 Paul Cercueil wrote: > Le sam. 12 mai 2018 à 10:42, Boris Brezillon > a écrit : > > On Sat, 12 May 2018 08:55:40 -0300 > > Paul Cercueil wrote: > > > >> Hi Boris, > >> > >> Le 12 mai 2018 02:55, Boris Brezillon > >> a écrit : > >> > > >> > Hi Paul, > >> > > >> > On Fri, 11 May 2018 23:29:12 +0200 > >> > Paul Cercueil wrote: > >> > > >> > > By specifying the properties "mtd-oob-ecc" and "mtd-oob-free", > >> it is > >> > > now possible to specify from devicetree where the ECC data is > >> located > >> > > inside the OOB region. > >> > > >> > Why would we want to do that? I mean, ECC/free regions are ECC > >> > controller dependent (and NAND chip dependent for the OOB size > >> part), > >> > so there's no reason to describe it in the DT. And more > >> importantly, > >> > people are likely to get it wrong. > >> > > >> > I'm curious, why do you need that? > >> > >> Good question. > >> > >> The reason is that some SoCs have no ECC controller. > >> The various boards for these SoCs then all use a different layout. > > > > Okay. Still think defining the layouts in the DT is a bad idea. We > > can add a jz4740 specific property to define the layout id > > (ingenic,nand-oob-layout = ), but not a generic way to > > define custom layouts for all kind of NAND controller. > > Okay. > > >> > >> My motivation is to get rid of this (move it to devicetree): > >> > >> https://elixir.bootlin.com/linux/latest/source/arch/mips/jz4740/board-qi_lb60.c#L93 > >> And enable the support of other boards with custom OOB layouts. > > > > Can you list the different layouts you have? I'm pretty sure there's a > > pattern. Maybe we can even deduce the layout from the page size or OOB > > size. > > This is the other layout I have for another ingenic device: > http://projects.qi-hardware.com/index.php/p/qi-kernel/source/tree/od-2011-09-18/arch/mips/jz4740/board-a320.c#L125 > > Page size and OOB size are the same between these two devices. Indeed. Do you know if there are other kind of layouts in the wild? Note that can be a string, so if each each board is defining its own layout, you could specify the board name here. Otherwise, if you just have those 2 patterns, you can just name them "contiguous" and "interleaved".