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* [PATCH net] net: phy: broadcom: Fix auxiliary control register reads
@ 2018-05-22 23:22 Florian Fainelli
  2018-05-23 19:19 ` David Miller
  0 siblings, 1 reply; 2+ messages in thread
From: Florian Fainelli @ 2018-05-22 23:22 UTC (permalink / raw)
  To: netdev
  Cc: jon.mason, Florian Fainelli, Andrew Lunn, David S. Miller, open list

We are currently doing auxiliary control register reads with the shadow
register value 0b111 (0x7) which incidentally is also the selector value
that should be present in bits [2:0]. Fix this by using the appropriate
selector mask which is defined (MII_BCM54XX_AUXCTL_SHDWSEL_MASK).

This does not have a functional impact yet because we always access the
MII_BCM54XX_AUXCTL_SHDWSEL_MISC (0x7) register in the current code.
This might change at some point though.

Fixes: 5b4e29005123 ("net: phy: broadcom: add bcm54xx_auxctl_read")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
David, please queue this for -stable as well, thank you!

 drivers/net/phy/bcm-phy-lib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/bcm-phy-lib.c b/drivers/net/phy/bcm-phy-lib.c
index 5ad130c3da43..d5e0833d69b9 100644
--- a/drivers/net/phy/bcm-phy-lib.c
+++ b/drivers/net/phy/bcm-phy-lib.c
@@ -56,7 +56,7 @@ int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
 	/* The register must be written to both the Shadow Register Select and
 	 * the Shadow Read Register Selector
 	 */
-	phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
+	phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
 		  regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
 	return phy_read(phydev, MII_BCM54XX_AUX_CTL);
 }
-- 
2.14.1

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH net] net: phy: broadcom: Fix auxiliary control register reads
  2018-05-22 23:22 [PATCH net] net: phy: broadcom: Fix auxiliary control register reads Florian Fainelli
@ 2018-05-23 19:19 ` David Miller
  0 siblings, 0 replies; 2+ messages in thread
From: David Miller @ 2018-05-23 19:19 UTC (permalink / raw)
  To: f.fainelli; +Cc: netdev, jon.mason, andrew, linux-kernel

From: Florian Fainelli <f.fainelli@gmail.com>
Date: Tue, 22 May 2018 16:22:26 -0700

> We are currently doing auxiliary control register reads with the shadow
> register value 0b111 (0x7) which incidentally is also the selector value
> that should be present in bits [2:0]. Fix this by using the appropriate
> selector mask which is defined (MII_BCM54XX_AUXCTL_SHDWSEL_MASK).
> 
> This does not have a functional impact yet because we always access the
> MII_BCM54XX_AUXCTL_SHDWSEL_MISC (0x7) register in the current code.
> This might change at some point though.
> 
> Fixes: 5b4e29005123 ("net: phy: broadcom: add bcm54xx_auxctl_read")
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> David, please queue this for -stable as well, thank you!

Applied and queued up for -stable.

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2018-05-22 23:22 [PATCH net] net: phy: broadcom: Fix auxiliary control register reads Florian Fainelli
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