From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752643AbeFEUjr (ORCPT ); Tue, 5 Jun 2018 16:39:47 -0400 Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:50091 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751950AbeFEUjo (ORCPT ); Tue, 5 Jun 2018 16:39:44 -0400 Date: Tue, 5 Jun 2018 22:39:41 +0200 From: Pavel Machek To: Andy Shevchenko Cc: "H. Nikolaus Schaller" , Kumar Gala , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Linus Walleij , Alexandre Courbot , devicetree , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Discussions about the Letux Kernel , kernel@pyra-handheld.com Subject: Re: [PATCH v7 3/3] gpio: pca953x: fix address calculation for pcal6524 Message-ID: <20180605203941.GA28143@amd> References: <20180523140635.GB27215@amd> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="d6Gm4EdcadzBjdND" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --d6Gm4EdcadzBjdND Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue 2018-06-05 18:37:21, Andy Shevchenko wrote: > On Wed, May 23, 2018 at 5:06 PM, Pavel Machek wrote: > > On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote: > >> The register constants are so far defined in a way that they fit > >> for the pcal9555a when shifted by the number of banks, i.e. are > >> multiplied by 2 in the accessor function. > >> > >> Now, the pcal6524 has 3 banks which means the relative offset > >> is multiplied by 4 for the standard registers. > >> > >> Simply applying the bit shift to the extended registers gives > >> a wrong result, since the base offset is already included in > >> the offset. > >> > >> Therefore, we have to add code to the 24 bit accessor functions > >> that adjusts the register number for these exended registers. > >> > >> The formula finally used was developed and proposed by > >> Andy Shevchenko . >=20 > >> int bank_shift =3D fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); > >> + int addr =3D (reg & PCAL_GPIO_MASK) << bank_shift; > >> + int pinctrl =3D (reg & PCAL_PINCTRL_MASK) << 1; >=20 > > Is this reasonable to do on each register access? Compiler will not be > > able to optimize out fls and shifts, right? >=20 > On modern CPUs fls() is one assembly command. OTOH, any proposal to do > this better? >=20 > What I can see is that bank_shift is invariant to the function, and > maybe cached. Yes, I thought that caching bank_shift might be good idea. I thought it was constant for given chip... Best regards, Pavel --=20 (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blo= g.html --d6Gm4EdcadzBjdND Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEARECAAYFAlsW9Q0ACgkQMOfwapXb+vLnsACfXGg75eku2hgA21L/7YAzxPdY nVUAnjrmbHRLIqtsz2vg2HQKeWmv0oei =E2tb -----END PGP SIGNATURE----- --d6Gm4EdcadzBjdND--