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From: Mark Rutland <mark.rutland@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will.deacon@arm.com,
robin.murphy@arm.com
Subject: Re: [PATCH v2 3/5] arm_pmu: Add support for 64bit event counters
Date: Wed, 6 Jun 2018 17:48:39 +0100 [thread overview]
Message-ID: <20180606164838.zeuygsp4teq64zor@lakrids.cambridge.arm.com> (raw)
In-Reply-To: <1527591356-10934-4-git-send-email-suzuki.poulose@arm.com>
On Tue, May 29, 2018 at 11:55:54AM +0100, Suzuki K Poulose wrote:
> Each PMU has a set of 32bit event counters. But in some
> special cases, the events could be counted using counters
> which are effectively 64bit wide.
>
> e.g, Arm V8 PMUv3 has a 64 bit cycle counter which can count
> only the CPU cycles. Also, the PMU can chain the event counters
> to effectively count as a 64bit counter.
>
> Add support for tracking the events that uses 64bit counters.
> This only affects the periods set for each counter in the core
> driver.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes since v1:
> - Rename ARMPMU_EVT_LONG => ARMPMU_EVT_64BIT
> ---
> drivers/perf/arm_pmu.c | 14 ++++++++------
> include/linux/perf/arm_pmu.h | 6 ++++++
> 2 files changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
> index 8962d26..ff858e6 100644
> --- a/drivers/perf/arm_pmu.c
> +++ b/drivers/perf/arm_pmu.c
> @@ -28,9 +28,10 @@
> static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
> static DEFINE_PER_CPU(int, cpu_irq);
>
> -static inline u64 arm_pmu_max_period(void)
> +static inline u64 arm_pmu_event_max_period(struct perf_event *event)
> {
> - return (1ULL << 32) - 1;
> + return (event->hw.flags & ARMPMU_EVT_64BIT) ?
> + ~0ULL : (1ULL << 32) - 1;
> }
Could we please have:
static inline u64 arm_pmu_event_max_period(struct perf_event *event)
{
if (event->hw.flags & ARMPMU_EVT_64BIT)
return GENMASK_ULL(63, 0);
else
return GENMASK_ULL(31, 0);
}
... since that's obviously balanced, with both values generated in the
same way.
Otherwise this looks good to me.
Thanks,
Mark.
next prev parent reply other threads:[~2018-06-06 16:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-29 10:55 [PATCH v2 0/5] arm64: perf: Support for chained counters Suzuki K Poulose
2018-05-29 10:55 ` [PATCH v2 1/5] arm_pmu: Clean up maximum period handling Suzuki K Poulose
2018-05-29 10:55 ` [PATCH v2 2/5] arm_pmu: Change API to support 64bit counter values Suzuki K Poulose
2018-05-29 10:55 ` [PATCH v2 3/5] arm_pmu: Add support for 64bit event counters Suzuki K Poulose
2018-06-06 16:48 ` Mark Rutland [this message]
2018-06-07 7:34 ` Suzuki K Poulose
2018-05-29 10:55 ` [PATCH v2 4/5] arm_pmu: Tidy up clear_event_idx call backs Suzuki K Poulose
2018-05-29 10:55 ` [PATCH v2 5/5] arm64: perf: Add support for chaining event counters Suzuki K Poulose
2018-06-06 18:01 ` Mark Rutland
2018-06-08 14:46 ` Suzuki K Poulose
2018-06-08 15:24 ` Mark Rutland
2018-06-08 16:05 ` Suzuki K Poulose
2018-06-11 13:54 ` Suzuki K Poulose
2018-06-11 14:24 ` Mark Rutland
2018-06-11 16:18 ` Suzuki K Poulose
2018-06-05 15:00 ` [PATCH v2 0/5] arm64: perf: Support for chained counters Julien Thierry
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