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* [LINUX PATCH v9 0/4] Add arm pl353 smc memory and nand driver for xilinx zynq soc
@ 2018-06-06  7:49 Naga Sureshkumar Relli
  2018-06-06  7:49 ` [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information Naga Sureshkumar Relli
                   ` (3 more replies)
  0 siblings, 4 replies; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-06  7:49 UTC (permalink / raw)
  To: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang,
	miquel.raynal
  Cc: linux-mtd, linux-kernel, nagasureshkumarrelli, Naga Sureshkumar Relli

The following patches add arm pl353 static memory controller driver and nand driver
for xilinx zynq soc. The arm pl353 smc supports two interfaces i.e nand and nor/sram
memory interfaces. The current implementation supports only a single SMC
instance and nand specific configuration.

xilinx zynq TRM link:
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/DDI0380G_smc_pl350_series_r2p1_trm.pdf

Tested Micron MT29F2G08ABAEAWP (On-die capable) and AMD/Spansion S34ML01G1.
This latest series make use of ->exec_op() . Referenced the marvel driver
as pointed by Miquel.

Naga Sureshkumar Relli (4):
  Devicetree: Add pl353 smc controller devicetree binding information
  memory: pl353: Add driver for arm pl353 static memory controller
  Documentation: nand: pl353: Add documentation for controller and
    driver
  mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface

 .../bindings/memory-controllers/pl353-smc.txt      |   53 +
 Documentation/mtd/nand/pl353-nand.txt              |   99 ++
 drivers/memory/Kconfig                             |    8 +
 drivers/memory/Makefile                            |    1 +
 drivers/memory/pl353-smc.c                         |  523 +++++++++
 drivers/mtd/nand/raw/Kconfig                       |    7 +
 drivers/mtd/nand/raw/Makefile                      |    3 +
 drivers/mtd/nand/raw/pl353_nand.c                  | 1236 ++++++++++++++++++++
 include/linux/platform_data/pl353-smc.h            |   29 +
 9 files changed, 1959 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
 create mode 100644 Documentation/mtd/nand/pl353-nand.txt
 create mode 100644 drivers/memory/pl353-smc.c
 create mode 100644 drivers/mtd/nand/raw/pl353_nand.c
 create mode 100644 include/linux/platform_data/pl353-smc.h

-- 
2.7.4

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information
  2018-06-06  7:49 [LINUX PATCH v9 0/4] Add arm pl353 smc memory and nand driver for xilinx zynq soc Naga Sureshkumar Relli
@ 2018-06-06  7:49 ` Naga Sureshkumar Relli
  2018-06-07 15:42   ` Miquel Raynal
  2018-06-06  7:49 ` [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static memory controller Naga Sureshkumar Relli
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-06  7:49 UTC (permalink / raw)
  To: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang,
	miquel.raynal
  Cc: linux-mtd, linux-kernel, nagasureshkumarrelli, Naga Sureshkumar Relli

Add pl353 static memory controller devicetree binding information.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
---
Changes in v9:
 - Addressed commens given by Randy Dunlap and Miquel Raynal
Changes in v8:
 - None
Changes in v7:
- Corrected clocks description
- prefixed '#' for address and size cells 
Changes in v6:
 - None
Changes in v5:
 - Removed timing properties
Changes in v4:
 - none
Changes in v3:
 - none
Changes in v2:
 - modified timing binding info as per onfi timing parameters
 - add suffix nano second as timing unit
 - modified the clock names as per the IP spec
---
 .../bindings/memory-controllers/pl353-smc.txt      | 53 ++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
new file mode 100644
index 0000000..551e66b
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
@@ -0,0 +1,53 @@
+Device tree bindings for ARM PL353 static memory controller
+
+PL353 static memory controller supports two kinds of memory
+interfaces.i.e NAND and SRAM/NOR interfaces.
+The actual devices are instantiated from the child nodes of pl353 smc node.
+
+Required properties:
+- compatible		: Should be "arm,pl353-smc-r2p1"
+- reg			: Controller registers map and length.
+- clock-names		: List of input clock names - "ref_clk", "aper_clk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+- address-cells		: Address cells, must be 1.
+- size-cells		: Size cells. Must be 1.
+
+Child nodes:
+ For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
+supported as child nodes.
+
+Mandatory timing properties for child nodes:
+- arm,nand-cycle-t0	: Read cycle time(t_rc).
+- arm,nand-cycle-t1	: Write cycle time(t_wc).
+- arm,nand-cycle-t2	: re_n assertion delay(t_rea).
+- arm,nand-cycle-t3	: we_n de-assertion delay(t_wp).
+- arm,nand-cycle-t4	: Status read time(t_clr)
+- arm,nand-cycle-t5	: ID read time(t_ar)
+- arm,nand-cycle-t6	: busy to re_n(t_rr)
+
+for nand partition information please refer the below file
+Documentation/devicetree/bindings/mtd/partition.txt
+
+Example:
+	pl353smcc_0: pl353smcc@e000e000 {
+			compatible = "arm,pl353-smc-r2p1"
+			clock-names = "memclk", "aclk";
+			clocks = <&clkc 11>, <&clkc 44>;
+			reg = <0xe000e000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			nand_0: nand@e1000000 {
+				compatible = "arm,pl353-nand-r2p1"
+				reg = <0xe1000000 0x1000000>;
+				arm,nand-cycle-t0 = <0x4>;
+				arm,nand-cycle-t1 = <0x4>;
+				arm,nand-cycle-t2 = <0x1>;
+				arm,nand-cycle-t3 = <0x2>;
+				arm,nand-cycle-t4 = <0x2>;
+				arm,nand-cycle-t5 = <0x2>;
+				arm,nand-cycle-t6 = <0x4>;
+				(...)
+			};
+	};
-- 
2.7.4

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static memory controller
  2018-06-06  7:49 [LINUX PATCH v9 0/4] Add arm pl353 smc memory and nand driver for xilinx zynq soc Naga Sureshkumar Relli
  2018-06-06  7:49 ` [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information Naga Sureshkumar Relli
@ 2018-06-06  7:49 ` Naga Sureshkumar Relli
  2018-06-07 16:07   ` Miquel Raynal
  2018-06-06  7:49 ` [LINUX PATCH v9 3/4] Documentation: nand: pl353: Add documentation for controller and driver Naga Sureshkumar Relli
  2018-06-06  7:49 ` [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface Naga Sureshkumar Relli
  3 siblings, 1 reply; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-06  7:49 UTC (permalink / raw)
  To: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang,
	miquel.raynal
  Cc: linux-mtd, linux-kernel, nagasureshkumarrelli, Naga Sureshkumar Relli

Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
---
Changes in v9:
 - Addressed the comments given by Julia Cartwright to the v8 series.
Changes in v8:
- None
Changes in v7:
- Corrected the kconfig to use tristate selection
- Corrected the GPL licence ident 
- Added boundary checks for nand timing parameters 
Changes in v6:
- Fixed checkpatch.pl reported warnings
Changes in v5:
- Added pl353_smc_get_clkrate function, made pl353_smc_set_cycles as public
  API
- Removed nand timing parameter initialization and moved it to nand driver  
Changes in v4:
- Modified driver to support multiple instances
- Used sleep instaed of busywait for delay
Changes in v3:
- None
Changes in v2:
- Since now the timing parameters are in nano seconds, added logic to convert
  them to the cycles
---
 drivers/memory/Kconfig                  |   8 +
 drivers/memory/Makefile                 |   1 +
 drivers/memory/pl353-smc.c              | 523 ++++++++++++++++++++++++++++++++
 include/linux/platform_data/pl353-smc.h |  29 ++
 4 files changed, 561 insertions(+)
 create mode 100644 drivers/memory/pl353-smc.c
 create mode 100644 include/linux/platform_data/pl353-smc.h

diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 19a0e83..9517da7 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -153,6 +153,14 @@ config DA8XX_DDRCTL
 	  Texas Instruments da8xx SoCs. It's used to tweak various memory
 	  controller configuration options.
 
+config PL353_SMC
+	tristate "ARM PL35X Static Memory Controller(SMC) driver"
+	default y
+	depends on ARM
+	help
+	  This driver is for the ARM PL351/PL353 Static Memory
+	  Controller(SMC) module.
+
 source "drivers/memory/samsung/Kconfig"
 source "drivers/memory/tegra/Kconfig"
 
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 66f5524..58e794d 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
 obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
 obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
 obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
+obj-$(CONFIG_PL353_SMC)		+= pl353-smc.o
 
 obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
 obj-$(CONFIG_TEGRA_MC)		+= tegra/
diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c
new file mode 100644
index 0000000..8758930
--- /dev/null
+++ b/drivers/memory/pl353-smc.c
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM PL353 SMC driver
+ *
+ * Copyright (C) 2012 Xilinx, Inc
+ * Author: Punnaiah Choudary Kalluri <punnaiah@xilinx.com>
+ * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/platform_data/pl353-smc.h>
+
+/* Register definitions */
+#define PL353_SMC_MEMC_STATUS_OFFS	0	/* Controller status reg, RO */
+#define PL353_SMC_CFG_CLR_OFFS		0xC	/* Clear config reg, WO */
+#define PL353_SMC_DIRECT_CMD_OFFS	0x10	/* Direct command reg, WO */
+#define PL353_SMC_SET_CYCLES_OFFS	0x14	/* Set cycles register, WO */
+#define PL353_SMC_SET_OPMODE_OFFS	0x18	/* Set opmode register, WO */
+#define PL353_SMC_ECC_STATUS_OFFS	0x400	/* ECC status register */
+#define PL353_SMC_ECC_MEMCFG_OFFS	0x404	/* ECC mem config reg */
+#define PL353_SMC_ECC_MEMCMD1_OFFS	0x408	/* ECC mem cmd1 reg */
+#define PL353_SMC_ECC_MEMCMD2_OFFS	0x40C	/* ECC mem cmd2 reg */
+#define PL353_SMC_ECC_VALUE0_OFFS	0x418	/* ECC value 0 reg */
+
+/* Controller status register specific constants */
+#define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT	6
+
+/* Clear configuration register specific constants */
+#define PL353_SMC_CFG_CLR_INT_CLR_1	0x10
+#define PL353_SMC_CFG_CLR_ECC_INT_DIS_1	0x40
+#define PL353_SMC_CFG_CLR_INT_DIS_1	0x2
+#define PL353_SMC_CFG_CLR_DEFAULT_MASK	(PL353_SMC_CFG_CLR_INT_CLR_1 | \
+					 PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \
+					 PL353_SMC_CFG_CLR_INT_DIS_1)
+
+/* Set cycles register specific constants */
+#define PL353_SMC_SET_CYCLES_T0_MASK	0xF
+#define PL353_SMC_SET_CYCLES_T0_SHIFT	0
+#define PL353_SMC_SET_CYCLES_T1_MASK	0xF
+#define PL353_SMC_SET_CYCLES_T1_SHIFT	4
+#define PL353_SMC_SET_CYCLES_T2_MASK	0x7
+#define PL353_SMC_SET_CYCLES_T2_SHIFT	8
+#define PL353_SMC_SET_CYCLES_T3_MASK	0x7
+#define PL353_SMC_SET_CYCLES_T3_SHIFT	11
+#define PL353_SMC_SET_CYCLES_T4_MASK	0x7
+#define PL353_SMC_SET_CYCLES_T4_SHIFT	14
+#define PL353_SMC_SET_CYCLES_T5_MASK	0x7
+#define PL353_SMC_SET_CYCLES_T5_SHIFT	17
+#define PL353_SMC_SET_CYCLES_T6_MASK	0xF
+#define PL353_SMC_SET_CYCLES_T6_SHIFT	20
+
+/* ECC status register specific constants */
+#define PL353_SMC_ECC_STATUS_BUSY	BIT(6)
+
+/* ECC memory config register specific constants */
+#define PL353_SMC_ECC_MEMCFG_MODE_MASK	0xC
+#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT	2
+#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK	0xC
+
+#define PL353_SMC_DC_UPT_NAND_REGS	((4 << 23) |	/* CS: NAND chip */ \
+				 (2 << 21))	/* UpdateRegs operation */
+
+#define PL353_NAND_ECC_CMD1	((0x80)       |	/* Write command */ \
+				 (0 << 8)     |	/* Read command */ \
+				 (0x30 << 16) |	/* Read End command */ \
+				 (1 << 24))	/* Read End command calid */
+
+#define PL353_NAND_ECC_CMD2	((0x85)	      |	/* Write col change cmd */ \
+				 (5 << 8)     |	/* Read col change cmd */ \
+				 (0xE0 << 16) |	/* Read col change end cmd */ \
+				 (1 << 24)) /* Read col change end cmd valid */
+#define PL353_NAND_ECC_BUSY_TIMEOUT	(1 * HZ)
+/**
+ * struct pl353_smc_data - Private smc driver structure
+ * @devclk:		Pointer to the peripheral clock
+ * @aperclk:		Pointer to the APER clock
+ */
+struct pl353_smc_data {
+	struct clk		*memclk;
+	struct clk		*aclk;
+};
+
+/* SMC virtual register base */
+static void __iomem *pl353_smc_base;
+
+/**
+ * pl353_smc_set_buswidth - Set memory buswidth
+ * @bw:	Memory buswidth (8 | 16)
+ * Return: 0 on success or negative errno.
+ */
+int pl353_smc_set_buswidth(unsigned int bw)
+{
+	if (bw != PL353_SMC_MEM_WIDTH_8  && bw != PL353_SMC_MEM_WIDTH_16)
+		return -EINVAL;
+
+	writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS);
+	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
+	       PL353_SMC_DIRECT_CMD_OFFS);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth);
+
+/**
+ * pl353_smc_set_cycles - Set memory timing parameters
+ * @t0:	t_rc		read cycle time
+ * @t1:	t_wc		write cycle time
+ * @t2:	t_rea/t_ceoe	output enable assertion delay
+ * @t3:	t_wp		write enable deassertion delay
+ * @t4:	t_clr/t_pc	page cycle time
+ * @t5:	t_ar/t_ta	ID read time/turnaround time
+ * @t6:	t_rr		busy to RE timing
+ *
+ * Sets NAND chip specific timing parameters.
+ */
+static void pl353_smc_set_cycles(u32 t0, u32 t1, u32 t2, u32 t3, u32
+			      t4, u32 t5, u32 t6)
+{
+	t0 &= PL353_SMC_SET_CYCLES_T0_MASK;
+	t1 = (t1 & PL353_SMC_SET_CYCLES_T1_MASK) <<
+			PL353_SMC_SET_CYCLES_T1_SHIFT;
+	t2 = (t2 & PL353_SMC_SET_CYCLES_T2_MASK) <<
+			PL353_SMC_SET_CYCLES_T2_SHIFT;
+	t3 = (t3 & PL353_SMC_SET_CYCLES_T3_MASK) <<
+			PL353_SMC_SET_CYCLES_T3_SHIFT;
+	t4 = (t4 & PL353_SMC_SET_CYCLES_T4_MASK) <<
+			PL353_SMC_SET_CYCLES_T4_SHIFT;
+	t5 = (t5 & PL353_SMC_SET_CYCLES_T5_MASK) <<
+			PL353_SMC_SET_CYCLES_T5_SHIFT;
+	t6 = (t6 & PL353_SMC_SET_CYCLES_T6_MASK) <<
+			PL353_SMC_SET_CYCLES_T6_SHIFT;
+
+	t0 |= t1 | t2 | t3 | t4 | t5 | t6;
+
+	writel(t0, pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS);
+	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
+	       PL353_SMC_DIRECT_CMD_OFFS);
+}
+
+/**
+ * pl353_smc_ecc_is_busy - Read ecc busy flag
+ * Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
+ */
+int pl353_smc_ecc_is_busy(void)
+{
+	return !!(readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) &
+		  PL353_SMC_ECC_STATUS_BUSY);
+}
+EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy);
+
+/**
+ * pl353_smc_get_ecc_val - Read ecc_valueN registers
+ * @ecc_reg:	Index of the ecc_value reg (0..3)
+ * Return: the content of the requested ecc_value register.
+ *
+ * There are four valid ecc_value registers. The argument is truncated to stay
+ * within this valid boundary.
+ */
+u32 pl353_smc_get_ecc_val(int ecc_reg)
+{
+	u32 addr, reg;
+
+	ecc_reg &= 3;
+	addr = PL353_SMC_ECC_VALUE0_OFFS + (ecc_reg << 2);
+	reg = readl(pl353_smc_base + addr);
+
+	return reg;
+}
+EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val);
+
+/**
+ * pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
+ * Return: the raw_int_status1 bit from the memc_status register
+ */
+int pl353_smc_get_nand_int_status_raw(void)
+{
+	u32 reg;
+
+	reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS);
+	reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
+	reg &= 1;
+
+	return reg;
+}
+EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw);
+
+/**
+ * pl353_smc_clr_nand_int - Clear NAND interrupt
+ */
+void pl353_smc_clr_nand_int(void)
+{
+	writel(PL353_SMC_CFG_CLR_INT_CLR_1,
+	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
+}
+EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int);
+
+/**
+ * pl353_smc_set_ecc_mode - Set SMC ECC mode
+ * @mode:	ECC mode (BYPASS, APB, MEM)
+ * Return: 0 on success or negative errno.
+ */
+int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)
+{
+	u32 reg;
+	int ret = 0;
+
+	switch (mode) {
+	case PL353_SMC_ECCMODE_BYPASS:
+	case PL353_SMC_ECCMODE_APB:
+	case PL353_SMC_ECCMODE_MEM:
+
+		reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
+		reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK;
+		reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;
+		writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
+
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode);
+
+/**
+ * pl353_smc_set_ecc_pg_size - Set SMC ECC page size
+ * @pg_sz:	ECC page size
+ * Return: 0 on success or negative errno.
+ */
+int pl353_smc_set_ecc_pg_size(unsigned int pg_sz)
+{
+	u32 reg, sz;
+
+	switch (pg_sz) {
+	case 0:
+		sz = 0;
+		break;
+	case SZ_512:
+		sz = 1;
+		break;
+	case SZ_1K:
+		sz = 2;
+		break;
+	case SZ_2K:
+		sz = 3;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
+	reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK;
+	reg |= sz;
+	writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size);
+
+static int __maybe_unused pl353_smc_suspend(struct device *dev)
+{
+	struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
+
+	clk_disable(pl353_smc->memclk);
+	clk_disable(pl353_smc->aclk);
+
+	return 0;
+}
+
+static int __maybe_unused pl353_smc_resume(struct device *dev)
+{
+	int ret;
+	struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
+
+	ret = clk_enable(pl353_smc->aclk);
+	if (ret) {
+		dev_err(dev, "Cannot enable axi domain clock.\n");
+		return ret;
+	}
+
+	ret = clk_enable(pl353_smc->memclk);
+	if (ret) {
+		dev_err(dev, "Cannot enable memory clock.\n");
+		clk_disable(pl353_smc->aclk);
+		return ret;
+	}
+	return ret;
+}
+
+static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
+			 pl353_smc_resume);
+
+/**
+ * pl353_smc_init_nand_interface - Initialize the NAND interface
+ * @pdev:	Pointer to the platform_device struct
+ * @nand_node:	Pointer to the pl353_nand device_node struct
+ */
+static void pl353_smc_init_nand_interface(struct platform_device *pdev,
+					  struct device_node *nand_node)
+{
+	u32 t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr;
+	int err;
+	unsigned long timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
+	/* nand-cycle-<X> property is refer to the NAND flash timing
+	 * mapping between dts and the NAND flash AC timing
+	 *  X  : AC timing name
+	 *  t0 : t_rc
+	 *  t1 : t_wc
+	 *  t2 : t_rea
+	 *  t3 : t_wp
+	 *  t4 : t_clr
+	 *  t5 : t_ar
+	 *  t6 : t_rr
+	 */
+	err = of_property_read_u32(nand_node, "arm,nand-cycle-t0", &t_rc);
+	if (err) {
+		dev_warn(&pdev->dev, "arm,nand-cycle-t0 not in device tree");
+		goto default_nand_timing;
+	}
+	err = of_property_read_u32(nand_node, "arm,nand-cycle-t1", &t_wc);
+	if (err) {
+		dev_warn(&pdev->dev, "arm,nand-cycle-t1 not in device tree");
+		goto default_nand_timing;
+	}
+	err = of_property_read_u32(nand_node, "arm,nand-cycle-t2", &t_rea);
+	if (err) {
+		dev_warn(&pdev->dev, "arm,nand-cycle-t2 not in device tree");
+		goto default_nand_timing;
+	}
+	err = of_property_read_u32(nand_node, "arm,nand-cycle-t3", &t_wp);
+	if (err) {
+		dev_warn(&pdev->dev, "arm,nand-cycle-t3 not in device tree");
+		goto default_nand_timing;
+	}
+	err = of_property_read_u32(nand_node, "arm,nand-cycle-t4", &t_clr);
+	if (err) {
+		dev_warn(&pdev->dev, "arm,nand-cycle-t4 not in device tree");
+		goto default_nand_timing;
+	}
+	err = of_property_read_u32(nand_node, "arm,nand-cycle-t5", &t_ar);
+	if (err) {
+		dev_warn(&pdev->dev, "arm,nand-cycle-t5 not in device tree");
+		goto default_nand_timing;
+	}
+	err = of_property_read_u32(nand_node, "arm,nand-cycle-t6", &t_rr);
+	if (err) {
+		dev_warn(&pdev->dev, "arm,nand-cycle-t6 not in device tree");
+		goto default_nand_timing;
+	}
+
+default_nand_timing:
+	/*
+	 * Default assume 50MHz clock (20ns cycle time) and 3V operation
+	 * The SET_CYCLES_REG register value depends on the flash device.
+	 * Look in to the device datasheet and change its value, This value
+	 * is for 2Gb Numonyx flash.
+	 */
+	if (err) {
+		/* set default NAND flash timing property */
+		dev_warn(&pdev->dev, "Using default timing for");
+		dev_warn(&pdev->dev, "2Gb Numonyx MT29F2G08ABAEAWP NAND flash");
+		dev_warn(&pdev->dev, "t_wp, t_clr, t_ar are set to 2");
+		dev_warn(&pdev->dev, "t_rc, t_wc, t_rr are set to 4");
+		dev_warn(&pdev->dev, "t_rea is set to 1");
+		t_rc = 4;
+		t_wc = 4;
+		t_rr = 4;
+		t_rea = 1;
+		t_wp = 2;
+		t_clr = 2;
+		t_ar = 2;
+	}
+
+	pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8);
+	pl353_smc_set_cycles(t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr);
+	writel(PL353_SMC_CFG_CLR_INT_CLR_1,
+	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
+	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
+	       PL353_SMC_DIRECT_CMD_OFFS);
+	/* Wait till the ECC operation is complete */
+	do {
+		if (pl353_smc_ecc_is_busy())
+			cpu_relax();
+		else
+			break;
+	} while (!time_after_eq(jiffies, timeout));
+
+	if (time_after_eq(jiffies, timeout))
+		dev_err(&pdev->dev, "nand ecc busy status timed out");
+
+	writel(PL353_NAND_ECC_CMD1,
+	       pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS);
+	writel(PL353_NAND_ECC_CMD2,
+	       pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS);
+}
+
+static const struct of_device_id pl353_smc_supported_children[] = {
+	{ .compatible = "cfi-flash" },
+	{ .compatible = "arm,pl353-nand-r2p1",
+	.data = pl353_smc_init_nand_interface },
+	{}
+};
+
+static int pl353_smc_probe(struct platform_device *pdev)
+{
+	struct pl353_smc_data *pl353_smc;
+	struct device_node *child;
+	struct resource *res;
+	int err;
+	struct device_node *of_node = pdev->dev.of_node;
+	void (*init)(struct platform_device *pdev,
+		     struct device_node *nand_node);
+	const struct of_device_id *match = NULL;
+
+	pl353_smc = devm_kzalloc(&pdev->dev, sizeof(*pl353_smc), GFP_KERNEL);
+	if (!pl353_smc)
+		return -ENOMEM;
+
+	/* Get the NAND controller virtual address */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	pl353_smc_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pl353_smc_base))
+		return PTR_ERR(pl353_smc_base);
+
+	pl353_smc->aclk = devm_clk_get(&pdev->dev, "aclk");
+	if (IS_ERR(pl353_smc->aclk)) {
+		dev_err(&pdev->dev, "aclk clock not found.\n");
+		return PTR_ERR(pl353_smc->aclk);
+	}
+
+	pl353_smc->memclk = devm_clk_get(&pdev->dev, "memclk");
+	if (IS_ERR(pl353_smc->memclk)) {
+		dev_err(&pdev->dev, "memclk clock not found.\n");
+		return PTR_ERR(pl353_smc->memclk);
+	}
+
+	err = clk_prepare_enable(pl353_smc->aclk);
+	if (err) {
+		dev_err(&pdev->dev, "Unable to enable AXI clock.\n");
+		return err;
+	}
+
+	err = clk_prepare_enable(pl353_smc->memclk);
+	if (err) {
+		dev_err(&pdev->dev, "Unable to enable memory clock.\n");
+		goto out_clk_dis_aper;
+	}
+
+	platform_set_drvdata(pdev, pl353_smc);
+
+	/* clear interrupts */
+	writel(PL353_SMC_CFG_CLR_DEFAULT_MASK,
+	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
+
+	/* Find compatible children. Only a single child is supported */
+	for_each_available_child_of_node(of_node, child) {
+		match = of_match_node(pl353_smc_supported_children, child);
+		if (!match) {
+			dev_warn(&pdev->dev, "unsupported child node\n");
+			continue;
+		}
+		break;
+	}
+	if (!match) {
+		dev_err(&pdev->dev, "no matching children\n");
+		goto out_clk_disable;
+	}
+
+	init = match->data;
+	if (init)
+		init(pdev, child);
+	of_platform_device_create(child, NULL, &pdev->dev);
+
+	return 0;
+
+out_clk_disable:
+	clk_disable_unprepare(pl353_smc->memclk);
+out_clk_dis_aper:
+	clk_disable_unprepare(pl353_smc->aclk);
+
+	return err;
+}
+
+static int pl353_smc_remove(struct platform_device *pdev)
+{
+	struct pl353_smc_data *pl353_smc = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(pl353_smc->memclk);
+	clk_disable_unprepare(pl353_smc->aclk);
+
+	return 0;
+}
+
+/* Match table for device tree binding */
+static const struct of_device_id pl353_smc_of_match[] = {
+	{ .compatible = "arm,pl353-smc-r2p1" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, pl353_smc_of_match);
+
+static struct platform_driver pl353_smc_driver = {
+	.probe		= pl353_smc_probe,
+	.remove		= pl353_smc_remove,
+	.driver		= {
+		.name	= "pl353-smc",
+		.pm	= &pl353_smc_dev_pm_ops,
+		.of_match_table = pl353_smc_of_match,
+	},
+};
+
+module_platform_driver(pl353_smc_driver);
+
+MODULE_AUTHOR("Xilinx, Inc.");
+MODULE_DESCRIPTION("ARM PL353 SMC Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/platform_data/pl353-smc.h b/include/linux/platform_data/pl353-smc.h
new file mode 100644
index 0000000..fc4129e
--- /dev/null
+++ b/include/linux/platform_data/pl353-smc.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM PL353 SMC Driver Header
+ *
+ * Copyright (C) 2017 Xilinx, Inc
+ */
+
+#ifndef __LINUX_MEMORY_PL353_SMC_H
+#define __LINUX_MEMORY_PL353_SMC_H
+
+enum pl353_smc_ecc_mode {
+	PL353_SMC_ECCMODE_BYPASS = 0,
+	PL353_SMC_ECCMODE_APB = 1,
+	PL353_SMC_ECCMODE_MEM = 2
+};
+
+enum pl353_smc_mem_width {
+	PL353_SMC_MEM_WIDTH_8 = 0,
+	PL353_SMC_MEM_WIDTH_16 = 1
+};
+
+u32 pl353_smc_get_ecc_val(int ecc_reg);
+int pl353_smc_ecc_is_busy(void);
+int pl353_smc_get_nand_int_status_raw(void);
+void pl353_smc_clr_nand_int(void);
+int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode);
+int pl353_smc_set_ecc_pg_size(unsigned int pg_sz);
+int pl353_smc_set_buswidth(unsigned int bw);
+#endif
-- 
2.7.4

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [LINUX PATCH v9 3/4] Documentation: nand: pl353: Add documentation for controller and driver
  2018-06-06  7:49 [LINUX PATCH v9 0/4] Add arm pl353 smc memory and nand driver for xilinx zynq soc Naga Sureshkumar Relli
  2018-06-06  7:49 ` [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information Naga Sureshkumar Relli
  2018-06-06  7:49 ` [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static memory controller Naga Sureshkumar Relli
@ 2018-06-06  7:49 ` Naga Sureshkumar Relli
  2018-06-06  7:49 ` [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface Naga Sureshkumar Relli
  3 siblings, 0 replies; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-06  7:49 UTC (permalink / raw)
  To: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang,
	miquel.raynal
  Cc: linux-mtd, linux-kernel, nagasureshkumarrelli, Naga Sureshkumar Relli

Added notes about the controller and driver

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
---
Changes in v9:
 - Addressed the comments given by Miquel and Randy
Changes in v8
 - None
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- Fixed the review comments
Changes in v4:
- None
---
 Documentation/mtd/nand/pl353-nand.txt | 99 +++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)
 create mode 100644 Documentation/mtd/nand/pl353-nand.txt

diff --git a/Documentation/mtd/nand/pl353-nand.txt b/Documentation/mtd/nand/pl353-nand.txt
new file mode 100644
index 0000000..c352c87
--- /dev/null
+++ b/Documentation/mtd/nand/pl353-nand.txt
@@ -0,0 +1,99 @@
+This document provides some notes about the ARM pl353 SMC controller used in
+Zynq SOC and confined to NAND specific details.
+
+Overview of the controller
+==========================
+	The SMC (PL353) supports two memory interfaces:
+	Interface 0 type SRAM.
+	Interface 1 type NAND.
+	This configuration supports the following configurable options:
+	   . 32-bit or 64-bit AXI data width
+	   . 8-bit, 16-bit, or 32-bit memory data width for interface 0
+	   . 8-bit, or 16-bit memory data width for interface 1
+	   . 1-4 chip selects on each interface
+	   . SLC ECC block for interface 1
+
+For more information, refer the below link for TRM
+http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/DDI0380G_smc_pl350_series_r2p1_trm.pdf
+
+NAND memory accesses
+====================
+	. Two phase NAND accesses
+	. NAND command phase transfers
+	. NAND data phase transfers
+
+Two phase NAND accesses
+	The SMC defines two phases of commands when transferring data to or from
+NAND flash.
+
+Command phase
+	Commands and optional address information are written to the NAND flash.
+The command and address can be associated with either a data phase operation to
+write to or read from the array, or a status/ID register transfer.
+
+Data phase
+ Data is either written to or read from the NAND flash. This data can be either
+data transferred to or from the array, or status/ID register information.
+
+NAND AXI address setup
+       AXI address      Command phase      Data phase
+	[31:24]         Chip address       Chip address
+	[23]            NoOfAddCycles_2    Reserved
+	[22]            NoOfAddCycles_1    Reserved
+	[21]            NoOfAddCycles_0    ClearCS
+	[20]            End command valid  End command valid
+	[19]            0                  1
+	[18:11]         End command        End command
+	[10:3]          Start command      [10] ECC Last
+					   [9:3] Reserved
+	[2:0]           Reserved           Reserved
+
+ECC
+===
+    It operates on a number of 512 byte blocks of NAND memory and can be
+programmed to store the ECC codes after the data in memory. For writes,
+the ECC is written to the spare area of the page. For reads, the result of
+a block ECC check are made available to the device driver.
+
+------------------------------------------------------------------------
+|               n * 512 blocks                  | extra  | ecc    |     |
+|                                               | block  | codes  |     |
+------------------------------------------------------------------------
+
+The ECC calculation uses a simple Hamming code, using 1-bit correction 2-bit
+detection. It starts when a valid read or write command with a 512 byte aligned
+address is detected on the memory interface.
+
+Driver details
+==============
+	The NAND driver has dependency with the pl353_smc memory controller
+driver for initializing the NAND timing parameters, bus width, ECC modes,
+control and status information.
+
+Since the controller expects that the chip select bit would be cleared for the
+last data transfer i.e last 4 data bytes, the existing nand page
+read/write routines for soft ECC and ECC none modes will not work. So, in order
+to make this driver work, it always updates the ECC mode as HW ECC and
+implements the page read/write functions for supporting the SW ECC.
+i.e. There is a limitation in SMC controller, that we must set ECC LAST on
+last data phase access, to tell ECC block not to expect any data further.
+Ex:  When number of ECC STEPS are 4, then till 3 we will write to flash
+using SMC with HW ECC enabled. And for the last ECC STEP, we will subtract
+4bytes from page size, and will initiate a transfer. And the remaining 4 as
+one more transfer with ECC_LAST bit set in NAND data phase register to notify
+ECC block not to expect any more data. The last block should be align with end
+of 512 byte block. Because of this limitation, we are not using core routines.
+
+HW ECC mode:
+	Up to 2K page size is supported and beyond that it returns
+-ENOTSUPPORT error. If the flash has on-die ECC controller then the
+priority is given to the on-die ECC controller. Also the current
+implementation has support for up to 64 bytes of OOB data.
+
+SW ECC mode:
+	It supports all the page sizes. But since, Zynq SOC bootrom uses
+HW ECC for the devices that have page <= 2K. so, When the kernel is not
+aware of the ECC mode, it uses HW ECC by default.
+
+For devicetree binding information please refer to the below dt binding file
+Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt.
-- 
2.7.4

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface
  2018-06-06  7:49 [LINUX PATCH v9 0/4] Add arm pl353 smc memory and nand driver for xilinx zynq soc Naga Sureshkumar Relli
                   ` (2 preceding siblings ...)
  2018-06-06  7:49 ` [LINUX PATCH v9 3/4] Documentation: nand: pl353: Add documentation for controller and driver Naga Sureshkumar Relli
@ 2018-06-06  7:49 ` Naga Sureshkumar Relli
  2018-06-07 19:59   ` Miquel Raynal
  3 siblings, 1 reply; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-06  7:49 UTC (permalink / raw)
  To: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang,
	miquel.raynal
  Cc: linux-mtd, linux-kernel, nagasureshkumarrelli, Naga Sureshkumar Relli

Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in xilinx zynq soc for interfacing
the nand flash memory.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
---
Changes in v9:
 - Addressed the below comments given by Miquel
 - instead of using pl353_nand_write32, use directly writel_relaxed
 - Fixed check patch warnings
 - Renamed write_buf/read_buf to write_data_op/read_data_op
 - use BIT macro instead of 1 << nr
 - Use NAND_ROW_ADDR_3 flag
 - Use nand_wait_ready()
 - Removed swecc functions
 - Use address cycles as per size, instead of reading it from Parameter page
 - Instead of writing too many patterns, use optional property
Changes in v8:
 - Added exec_op() implementation
 - Fixed the below v7 review comments
 - removed mtd_info from pl353_nand_info struct
 - Corrected ecc layout offsets
 - Added on-die ecc support
Changes in v7:
 - Currently not implemented the memclk rate adjustments. I will
   look into this later and once the basic driver is accepted.
 - Fixed GPL licence ident
Changes in v6:
 - Fixed the checkpatch.pl reported warnings
 - Using the address cycles information from the onfi param page
   earlier it is hardcoded to 5 in driver
Changes in v5:
 - Configure the nand timing parameters as per the onfi spec
Changes in v4:
 - Updated the driver to sync with pl353_smc driver APIs
Changes in v3:
 - implemented the proper error codes
 - further breakdown this patch to multiple sets
 - added the controller and driver details to Documentation section
 - updated the licenece to GPLv2
 - reorganized the pl353_nand_ecc_init function
Changes in v2:
 - use "depends on" rather than "select" option in kconfig
 - remove unused variable parts
 - remove dummy helper and use writel_relaxed directly
---

 drivers/mtd/nand/raw/Kconfig      |    7 +
 drivers/mtd/nand/raw/Makefile     |    3 +
 drivers/mtd/nand/raw/pl353_nand.c | 1236 +++++++++++++++++++++++++++++++++++++
 3 files changed, 1246 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/pl353_nand.c

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 6871ff0..1c5d528 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -530,4 +530,11 @@ config MTD_NAND_MTK
 	  Enables support for NAND controller on MTK SoCs.
 	  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_PL353
+	tristate "ARM Pl353 NAND flash driver"
+	depends on MTD_NAND && ARM
+	depends on PL353_SMC
+	help
+	  Enables support for PrimeCell Static Memory Controller PL353.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef..6855a0d 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,7 +56,9 @@ obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_PL353)		+= pl353_nand.o
 
+CFLAGS_{nand_base.o} := -DDEBUG
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
 nand-objs += nand_hynix.o
@@ -64,3 +66,4 @@ nand-objs += nand_macronix.o
 nand-objs += nand_micron.o
 nand-objs += nand_samsung.o
 nand-objs += nand_toshiba.o
+
diff --git a/drivers/mtd/nand/raw/pl353_nand.c b/drivers/mtd/nand/raw/pl353_nand.c
new file mode 100644
index 0000000..a880eade
--- /dev/null
+++ b/drivers/mtd/nand/raw/pl353_nand.c
@@ -0,0 +1,1236 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM PL353 NAND flash controller driver
+ *
+ * Copyright (C) 2017 Xilinx, Inc
+ * Author: Punnaiah chowdary kalluri <punnaiah@xilinx.com>
+ * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/platform_data/pl353-smc.h>
+
+#define PL353_NAND_DRIVER_NAME "pl353-nand"
+
+/* NAND flash driver defines */
+#define PL353_NAND_CMD_PHASE	1	/* End command valid in command phase */
+#define PL353_NAND_DATA_PHASE	2	/* End command valid in data phase */
+#define PL353_NAND_ECC_SIZE	512	/* Size of data for ECC operation */
+
+/* Flash memory controller operating parameters */
+
+#define PL353_NAND_ECC_CONFIG	(BIT(4)  |	/* ECC read at end of page */ \
+				 (0 << 5))	/* No Jumping */
+
+/* AXI Address definitions */
+#define START_CMD_SHIFT		3
+#define END_CMD_SHIFT		11
+#define END_CMD_VALID_SHIFT	20
+#define ADDR_CYCLES_SHIFT	21
+#define CLEAR_CS_SHIFT		21
+#define ECC_LAST_SHIFT		10
+#define COMMAND_PHASE		(0 << 19)
+#define DATA_PHASE		BIT(19)
+
+#define PL353_NAND_ECC_LAST	BIT(ECC_LAST_SHIFT)	/* Set ECC_Last */
+#define PL353_NAND_CLEAR_CS	BIT(CLEAR_CS_SHIFT)	/* Clear chip select */
+
+#define ONDIE_ECC_FEATURE_ADDR	0x90
+#define PL353_NAND_ECC_BUSY_TIMEOUT	(1 * HZ)
+#define PL353_NAND_DEV_BUSY_TIMEOUT	(1 * HZ)
+#define PL353_NAND_LAST_TRANSFER_LENGTH	4
+
+struct pl353_nfc_op {
+	u32 cmnds[4];
+	u32 thirdrow;
+	u32 type;
+	u32 end_cmd;
+	u32 addrs;
+	bool wait;
+	u32 len;
+	u32 naddrs;
+	unsigned int data_instr_idx;
+	const struct nand_op_instr *data_instr;
+	unsigned int rdy_timeout_ms;
+	unsigned int rdy_delay_ns;
+	unsigned int data_delay_ns;
+	unsigned int cle_ale_delay_ns;
+	u32 addr5;
+	u32 addr6;
+};
+
+/**
+ * struct pl353_nand_info - Defines the NAND flash driver instance
+ * @chip:		NAND chip information structure
+ * @nand_base:		Virtual address of the NAND flash device
+ * @end_cmd_pending:	End command is pending
+ * @end_cmd:		End command
+ * @row_addr_cycles:	Row address cycles
+ * @col_addr_cycles:	Column address cycles
+ * @address:		Page address
+ * @cmd_pending:	More command is needed
+ */
+struct pl353_nand_info {
+	struct nand_chip chip;
+	void __iomem *nand_base;
+	unsigned long end_cmd_pending;
+	unsigned long end_cmd;
+	u8 addr_cycles;
+	u32 address;
+	u32 cmd_pending;
+	struct completion complete;
+};
+
+static int pl353_ecc_ooblayout16_ecc(struct mtd_info *mtd, int section,
+				     struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if (section >= chip->ecc.steps)
+		return -ERANGE;
+
+	oobregion->offset = (section * chip->ecc.bytes);
+	oobregion->length = chip->ecc.bytes;
+
+	return 0;
+}
+
+static int pl353_ecc_ooblayout16_free(struct mtd_info *mtd, int section,
+				      struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if (section >= chip->ecc.steps)
+		return -ERANGE;
+
+	oobregion->offset = (section * chip->ecc.bytes) + 8;
+	oobregion->length = 8;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops pl353_ecc_ooblayout16_ops = {
+	.ecc = pl353_ecc_ooblayout16_ecc,
+	.free = pl353_ecc_ooblayout16_free,
+};
+
+static int pl353_ecc_ooblayout64_ecc(struct mtd_info *mtd, int section,
+				     struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if (section >= chip->ecc.steps)
+		return -ERANGE;
+
+	oobregion->offset = (section * chip->ecc.bytes) + 52;
+	oobregion->length = chip->ecc.bytes;
+
+	return 0;
+}
+
+static int pl353_ecc_ooblayout64_free(struct mtd_info *mtd, int section,
+				      struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if (section)
+		return -ERANGE;
+
+	if (section >= chip->ecc.steps)
+		return -ERANGE;
+
+	oobregion->offset = (section * chip->ecc.bytes) + 2;
+	oobregion->length = 50;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops pl353_ecc_ooblayout64_ops = {
+	.ecc = pl353_ecc_ooblayout64_ecc,
+	.free = pl353_ecc_ooblayout64_free,
+};
+
+/* Generic flash bbt decriptors */
+static u8 bbt_pattern[] = { 'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 4,
+	.len = 4,
+	.veroffs = 20,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 4,
+	.len = 4,
+	.veroffs = 20,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
+/**
+ * pl353_nand_read_data_op - read chip data into buffer
+ * @chip:	Pointer to the NAND chip info structure
+ * @in:		Pointer to the buffer to store read data
+ * @len:	Number of bytes to read
+ * Return:	Always return zero
+ */
+static int pl353_nand_read_data_op(struct nand_chip *chip,
+				   u8 *in,
+				   unsigned int len)
+{
+	int i;
+
+	if (IS_ALIGNED((uint32_t)in, sizeof(uint32_t)) &&
+	    IS_ALIGNED(len, sizeof(uint32_t))) {
+		u32 *ptr = (u32 *)in;
+
+		len /= 4;
+		for (i = 0; i < len; i++)
+			ptr[i] = readl(chip->IO_ADDR_R);
+	} else {
+		for (i = 0; i < len; i++)
+			in[i] = readb(chip->IO_ADDR_R);
+	}
+
+	return 0;
+}
+
+/**
+ * pl353_nand_write_buf - write buffer to chip
+ * @mtd:	Pointer to the mtd info structure
+ * @buf:	Pointer to the buffer to store write data
+ * @len:	Number of bytes to write
+ */
+static void pl353_nand_write_data_op(struct mtd_info *mtd, const u8 *buf,
+				     int len)
+{
+	int i;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
+	    IS_ALIGNED(len, sizeof(uint32_t))) {
+		u32 *ptr = (u32 *)buf;
+
+		len /= 4;
+		for (i = 0; i < len; i++)
+			writel(ptr[i], chip->IO_ADDR_W);
+	} else {
+		for (i = 0; i < len; i++)
+			writeb(buf[i], chip->IO_ADDR_W);
+	}
+}
+
+/**
+ * pl353_nand_calculate_hwecc - Calculate Hardware ECC
+ * @mtd:	Pointer to the mtd_info structure
+ * @data:	Pointer to the page data
+ * @ecc:	Pointer to the ECC buffer where ECC data needs to be stored
+ *
+ * This function retrieves the Hardware ECC data from the controller and returns
+ * ECC data back to the MTD subsystem.
+ *
+ * Return:	0 on success or error value on failure
+ */
+static int pl353_nand_calculate_hwecc(struct mtd_info *mtd,
+				      const u8 *data, u8 *ecc)
+{
+	u32 ecc_value, ecc_status;
+	u8 ecc_reg, ecc_byte;
+	unsigned long timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
+	/* Wait till the ECC operation is complete or timeout */
+	do {
+		if (pl353_smc_ecc_is_busy())
+			cpu_relax();
+		else
+			break;
+	} while (!time_after_eq(jiffies, timeout));
+
+	if (time_after_eq(jiffies, timeout)) {
+		pr_err("%s timed out\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
+		/* Read ECC value for each block */
+		ecc_value = pl353_smc_get_ecc_val(ecc_reg);
+		ecc_status = (ecc_value >> 24) & 0xFF;
+		/* ECC value valid */
+		if (ecc_status & 0x40) {
+			for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
+				/* Copy ECC bytes to MTD buffer */
+				*ecc = ~ecc_value & 0xFF;
+				ecc_value = ecc_value >> 8;
+				ecc++;
+			}
+		} else {
+			pr_warn("%s status failed\n", __func__);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+/**
+ * onehot - onehot function
+ * @value:	Value to check for onehot
+ *
+ * This function checks whether a value is onehot or not.
+ * onehot is if and only if onebit is set.
+ *
+ * Return:	1 if it is onehot else 0
+ */
+static int onehot(unsigned short value)
+{
+	return (value & (value - 1)) == 0;
+}
+
+/**
+ * pl353_nand_correct_data - ECC correction function
+ * @mtd:	Pointer to the mtd_info structure
+ * @buf:	Pointer to the page data
+ * @read_ecc:	Pointer to the ECC value read from spare data area
+ * @calc_ecc:	Pointer to the calculated ECC value
+ *
+ * This function corrects the ECC single bit errors & detects 2-bit errors.
+ *
+ * Return:	0 if no ECC errors found
+ *		1 if single bit error found and corrected.
+ *		-1 if multiple ECC errors found.
+ */
+static int pl353_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
+				   unsigned char *read_ecc,
+				   unsigned char *calc_ecc)
+{
+	unsigned char bit_addr;
+	unsigned int byte_addr;
+	unsigned short ecc_odd, ecc_even, read_ecc_lower, read_ecc_upper;
+	unsigned short calc_ecc_lower, calc_ecc_upper;
+
+	read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
+	read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
+
+	calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
+	calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
+
+	ecc_odd = read_ecc_lower ^ calc_ecc_lower;
+	ecc_even = read_ecc_upper ^ calc_ecc_upper;
+
+	/* no error */
+	if (ecc_odd == 0 && ecc_even == 0)
+		return 0;
+
+	if (ecc_odd == (~ecc_even & 0xfff)) {
+		/* bits [11:3] of error code is byte offset */
+		byte_addr = (ecc_odd >> 3) & 0x1ff;
+		/* bits [2:0] of error code is bit offset */
+		bit_addr = ecc_odd & 0x7;
+		/* Toggling error bit */
+		buf[byte_addr] ^= (BIT(bit_addr));
+		return 1;
+	}
+	/* one error in parity */
+	if (onehot(ecc_odd | ecc_even) == 1)
+		return 1;
+
+	/* Uncorrectable error */
+	return -1;
+}
+
+static int pl353_dev_timeout(struct mtd_info *mtd, struct nand_chip *chip)
+{
+	unsigned long timeout = jiffies + PL353_NAND_DEV_BUSY_TIMEOUT;
+
+	do {
+		if (chip->dev_ready(mtd))
+			break;
+		cpu_relax();
+	} while (!time_after_eq(jiffies, timeout));
+
+	if (time_after_eq(jiffies, timeout)) {
+		pr_err("%s timed out\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void pl353_prepare_cmd(struct mtd_info *mtd, struct nand_chip *chip,
+			      int page, int column, int start_cmd, int end_cmd,
+			      bool read)
+{
+	unsigned long data_phase_addr;
+	u32 end_cmd_valid = 0;
+	void __iomem *cmd_addr;
+	unsigned long cmd_phase_addr = 0, cmd_data = 0;
+
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+
+	end_cmd_valid = read ? 1 : 0;
+
+	cmd_phase_addr = (unsigned long __force)xnand->nand_base +
+			 ((xnand->addr_cycles
+			 << ADDR_CYCLES_SHIFT) |
+			 (end_cmd_valid << END_CMD_VALID_SHIFT) |
+			 (COMMAND_PHASE) |
+			 (end_cmd << END_CMD_SHIFT) |
+			 (start_cmd << START_CMD_SHIFT));
+	cmd_addr = (void __iomem * __force)cmd_phase_addr;
+
+	/* Get the data phase address */
+	data_phase_addr = (unsigned long __force)xnand->nand_base +
+			  ((0x0 << CLEAR_CS_SHIFT) |
+			  (0 << END_CMD_VALID_SHIFT) |
+			  (DATA_PHASE) |
+			  (end_cmd << END_CMD_SHIFT) |
+			  (0x0 << ECC_LAST_SHIFT));
+
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+	chip->IO_ADDR_W = chip->IO_ADDR_R;
+	if (chip->options & NAND_BUSWIDTH_16)
+		column /= 2;
+	cmd_data = column;
+	if (mtd->writesize > PL353_NAND_ECC_SIZE) {
+		cmd_data |= page << 16;
+		/* Another address cycle for devices > 128MiB */
+		if (chip->options & NAND_ROW_ADDR_3) {
+			writel_relaxed(cmd_data, cmd_addr);
+			cmd_data = (page >> 16);
+		}
+	} else {
+		cmd_data |= page << 8;
+	}
+
+	writel_relaxed(cmd_data, cmd_addr);
+}
+
+/**
+ * pl353_nand_read_oob - [REPLACEABLE] the most common OOB data read function
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ * @page:	Page number to read
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+			       int page)
+{
+	unsigned long data_phase_addr;
+	u8 *p;
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
+
+	chip->pagebuf = -1;
+	if (mtd->writesize < PL353_NAND_ECC_SIZE)
+		return 0;
+
+	pl353_prepare_cmd(mtd, chip, page, mtd->writesize, NAND_CMD_READ0,
+			  NAND_CMD_READSTART, 1);
+
+	ndelay(100);
+	pl353_dev_timeout(mtd, chip);
+
+	p = chip->oob_poi;
+	pl353_nand_read_data_op(chip, p,
+				(mtd->oobsize -
+				PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_write_oob - [REPLACEABLE] the most common OOB data write function
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ * @page:	Page number to write
+ *
+ * Return:	Zero on success and EIO on failure
+ */
+static int pl353_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+				int page)
+{
+	const u8 *buf = chip->oob_poi;
+	unsigned long data_phase_addr;
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
+	u32 addrcycles = 0;
+
+	chip->pagebuf = -1;
+	addrcycles = xnand->addr_cycles;
+	pl353_prepare_cmd(mtd, chip, page, mtd->writesize, NAND_CMD_SEQIN,
+			  NAND_CMD_PAGEPROG, 0);
+	ndelay(100);
+	pl353_nand_write_data_op(mtd, buf,
+				 (mtd->oobsize -
+				 PL353_NAND_LAST_TRANSFER_LENGTH));
+	buf += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+	pl353_nand_write_data_op(mtd, buf, PL353_NAND_LAST_TRANSFER_LENGTH);
+	nand_wait_ready(mtd);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_read_page_raw - [Intern] read raw page data without ecc
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the data buffer
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ * @page:		Page number to read
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_read_page_raw(struct mtd_info *mtd,
+				    struct nand_chip *chip,
+				    u8 *buf, int oob_required, int page)
+{
+	unsigned long data_phase_addr;
+	u8 *p;
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
+
+	pl353_nand_read_data_op(chip, buf, mtd->writesize);
+	p = chip->oob_poi;
+	pl353_nand_read_data_op(chip, p,
+				(mtd->oobsize -
+				PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+
+	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_write_page_raw - [Intern] raw page write function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the data buffer
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ * @page:		Page number to write
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_write_page_raw(struct mtd_info *mtd,
+				     struct nand_chip *chip,
+				     const u8 *buf, int oob_required,
+				     int page)
+{
+	unsigned long data_phase_addr;
+	u8 *p;
+
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
+
+	pl353_nand_write_data_op(mtd, buf, mtd->writesize);
+	p = chip->oob_poi;
+	pl353_nand_write_data_op(mtd, p,
+				 (mtd->oobsize -
+				 PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+
+	pl353_nand_write_data_op(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+	ndelay(100);
+	nand_wait_ready(mtd);
+	return 0;
+}
+
+/**
+ * nand_write_page_hwecc - Hardware ECC based page write function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the data buffer
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ * @page:		Page number to write
+ *
+ * This functions writes data and hardware generated ECC values in to the page.
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_write_page_hwecc(struct mtd_info *mtd,
+				       struct nand_chip *chip,
+				       const u8 *buf, int oob_required,
+				       int page)
+{
+	int eccsize = chip->ecc.size;
+	int eccsteps = chip->ecc.steps;
+	u8 *ecc_calc = chip->ecc.calc_buf;
+	u8 *oob_ptr;
+	const u8 *p = buf;
+	u32 ret;
+	unsigned long data_phase_addr;
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
+
+	pl353_prepare_cmd(mtd, chip, page, 0, NAND_CMD_SEQIN,
+			  NAND_CMD_PAGEPROG, 0);
+	ndelay(100);
+	for ( ; (eccsteps - 1); eccsteps--) {
+		pl353_nand_write_data_op(mtd, p, eccsize);
+		p += eccsize;
+	}
+	pl353_nand_write_data_op(mtd, p,
+				 (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Set ECC Last bit to 1 */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_ECC_LAST;
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+	pl353_nand_write_data_op(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	p = buf;
+	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+	/* Wait for ECC to be calculated and read the error values */
+	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi,
+					 0, chip->ecc.total);
+	if (ret)
+		return ret;
+	/* Clear ECC last bit */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr -= nand_offset;
+	data_phase_addr &= ~PL353_NAND_ECC_LAST;
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+
+	/* Write the spare area with ECC bytes */
+	oob_ptr = chip->oob_poi;
+	pl353_nand_write_data_op(mtd, oob_ptr,
+				 (mtd->oobsize -
+				 PL353_NAND_LAST_TRANSFER_LENGTH));
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+	pl353_nand_write_data_op(mtd, oob_ptr, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/*
+	 * Apply this short delay always to ensure that we do wait tWB in any
+	 * case on any machine.
+	 */
+	ndelay(100);
+	nand_wait_ready(mtd);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_read_page_hwecc - Hardware ECC based page read function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the buffer to store read data
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ * @page:		Page number to read
+ *
+ * This functions reads data and checks the data integrity by comparing hardware
+ * generated ECC values and read ECC values from spare area.
+ *
+ * Return:	0 always and updates ECC operation status in to MTD structure
+ */
+static int pl353_nand_read_page_hwecc(struct mtd_info *mtd,
+				      struct nand_chip *chip,
+				      u8 *buf, int oob_required, int page)
+{
+	int i, stat, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	u8 *p = buf;
+	u8 *ecc_calc = chip->ecc.calc_buf;
+	u8 *ecc = chip->ecc.code_buf;
+	unsigned int max_bitflips = 0;
+	u8 *oob_ptr;
+	u32 ret;
+	unsigned long data_phase_addr;
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
+
+	pl353_prepare_cmd(mtd, chip, page, 0, NAND_CMD_READ0,
+			  NAND_CMD_READSTART, 1);
+	ndelay(100);
+	pl353_dev_timeout(mtd, chip);
+
+	for ( ; (eccsteps - 1); eccsteps--) {
+		pl353_nand_read_data_op(chip, p, eccsize);
+		p += eccsize;
+	}
+	pl353_nand_read_data_op(chip, p,
+				(eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Set ECC Last bit to 1 */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_ECC_LAST;
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Read the calculated ECC value */
+	p = buf;
+	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+	/* Clear ECC last bit */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr -= nand_offset;
+	data_phase_addr &= ~PL353_NAND_ECC_LAST;
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+
+	/* Read the stored ECC value */
+	oob_ptr = chip->oob_poi;
+	pl353_nand_read_data_op(chip, oob_ptr,
+				(mtd->oobsize -
+				PL353_NAND_LAST_TRANSFER_LENGTH));
+
+	/* de-assert chip select */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr -= nand_offset;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr += nand_offset;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+
+	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+	pl353_nand_read_data_op(chip, oob_ptr, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	ret = mtd_ooblayout_get_eccbytes(mtd, ecc, chip->oob_poi, 0,
+					 chip->ecc.total);
+	if (ret)
+		return ret;
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	/* Check ECC error for all blocks and correct if it is correctable */
+	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		stat = chip->ecc.correct(mtd, p, &ecc[i], &ecc_calc[i]);
+		if (stat < 0) {
+			mtd->ecc_stats.failed++;
+		} else {
+			mtd->ecc_stats.corrected += stat;
+			max_bitflips = max_t(unsigned int, max_bitflips, stat);
+		}
+	}
+
+	return max_bitflips;
+}
+
+/**
+ * pl353_nand_select_chip - Select the flash device
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ *
+ * This function is empty as the NAND controller handles chip select line
+ * internally based on the chip address passed in command and data phase.
+ */
+static void pl353_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+}
+
+/* NAND framework ->exec_op() hooks and related helpers */
+static void pl353_nfc_parse_instructions(struct nand_chip *chip,
+					 const struct nand_subop *subop,
+					 struct pl353_nfc_op *nfc_op)
+{
+	const struct nand_op_instr *instr = NULL;
+	unsigned int op_id, offset, naddrs;
+	int i, len;
+	const u8 *addrs;
+
+	memset(nfc_op, 0, sizeof(struct pl353_nfc_op));
+	for (op_id = 0; op_id < subop->ninstrs; op_id++) {
+		nfc_op->len = nand_subop_get_data_len(subop, op_id);
+		len = nand_subop_get_data_len(subop, op_id);
+		instr = &subop->instrs[op_id];
+		if (subop->ninstrs == 1)
+			nfc_op->cmnds[0] = -1;
+		switch (instr->type) {
+		case NAND_OP_CMD_INSTR:
+			nfc_op->type = NAND_OP_CMD_INSTR;
+			if (op_id)
+				nfc_op->cmnds[1] = instr->ctx.cmd.opcode;
+			else
+				nfc_op->cmnds[0] = instr->ctx.cmd.opcode;
+			nfc_op->cle_ale_delay_ns = instr->delay_ns;
+			break;
+
+		case NAND_OP_ADDR_INSTR:
+			offset = nand_subop_get_addr_start_off(subop, op_id);
+			naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
+			addrs = &instr->ctx.addr.addrs[offset];
+			nfc_op->addrs = instr->ctx.addr.addrs[offset];
+			for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) {
+				nfc_op->addrs |= instr->ctx.addr.addrs[i] <<
+						 (8 * i);
+			}
+
+			if (naddrs >= 5)
+				nfc_op->addr5 = addrs[4];
+			if (naddrs >= 6)
+				nfc_op->addr6 = addrs[5];
+			nfc_op->naddrs = nand_subop_get_num_addr_cyc(subop,
+								     op_id);
+			nfc_op->cle_ale_delay_ns = instr->delay_ns;
+			break;
+
+		case NAND_OP_DATA_IN_INSTR:
+			nfc_op->data_instr = instr;
+			nfc_op->type = NAND_OP_DATA_IN_INSTR;
+			nfc_op->data_instr_idx = op_id;
+			nfc_op->data_delay_ns = instr->delay_ns;
+			break;
+
+		case NAND_OP_DATA_OUT_INSTR:
+			nfc_op->data_instr = instr;
+			nfc_op->type = NAND_OP_DATA_IN_INSTR;
+			nfc_op->data_instr_idx = op_id;
+			nfc_op->data_delay_ns = instr->delay_ns;
+			break;
+
+		case NAND_OP_WAITRDY_INSTR:
+			nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
+			nfc_op->rdy_delay_ns = instr->delay_ns;
+			nfc_op->wait = true;
+			break;
+		}
+	}
+}
+
+static void cond_delay(unsigned int ns)
+{
+	if (!ns)
+		return;
+
+	if (ns < 10000)
+		ndelay(ns);
+	else
+		udelay(DIV_ROUND_UP(ns, 1000));
+}
+
+/**
+ * pl353_nand_cmd_function - Send command to NAND device
+ * @chip:	Pointer to the NAND chip info structure
+ * @subop:	Pointer to array of instructions
+ * Return:	Always return zero
+ */
+static int pl353_nand_cmd_function(struct nand_chip *chip,
+				   const struct nand_subop *subop)
+{
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	const struct nand_op_instr *instr;
+	struct pl353_nfc_op nfc_op = {};
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+	void __iomem *cmd_addr;
+	unsigned long cmd_data = 0, end_cmd_valid = 0;
+	unsigned long cmd_phase_addr, data_phase_addr, end_cmd;
+	unsigned int op_id, len, offset;
+	bool reading;
+
+	pl353_nfc_parse_instructions(chip, subop, &nfc_op);
+	instr = nfc_op.data_instr;
+	op_id = nfc_op.data_instr_idx;
+	len = nand_subop_get_data_len(subop, op_id);
+	offset = nand_subop_get_data_start_off(subop, op_id);
+
+	if (nfc_op.cmnds[0] != -1) {
+		pl353_smc_clr_nand_int();
+		/* Get the command phase address */
+		if (nfc_op.cmnds[1] != 0) {
+			if (nfc_op.cmnds[0] == NAND_CMD_SEQIN)
+				end_cmd_valid = 0;
+			else
+				end_cmd_valid = 1;
+			end_cmd = nfc_op.cmnds[1];
+		}  else {
+			end_cmd = 0x0;
+		}
+		cmd_phase_addr = (unsigned long __force)xnand->nand_base +
+				 ((nfc_op.naddrs << ADDR_CYCLES_SHIFT) |
+				 (end_cmd_valid << END_CMD_VALID_SHIFT) |
+				 (COMMAND_PHASE) |
+				 (end_cmd << END_CMD_SHIFT) |
+				 (nfc_op.cmnds[0] << START_CMD_SHIFT));
+
+		cmd_addr = (void __iomem * __force)cmd_phase_addr;
+		/* Get the data phase address */
+		end_cmd_valid = 0;
+
+		data_phase_addr = (unsigned long __force)xnand->nand_base +
+				  ((0x0 << CLEAR_CS_SHIFT) |
+				  (end_cmd_valid << END_CMD_VALID_SHIFT) |
+				  (DATA_PHASE) |
+				  (end_cmd << END_CMD_SHIFT) |
+				  (0x0 << ECC_LAST_SHIFT));
+		chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+		chip->IO_ADDR_W = chip->IO_ADDR_R;
+		/* Command phase AXI Read & Write */
+		if (nfc_op.naddrs >= 5) {
+			if (mtd->writesize > PL353_NAND_ECC_SIZE) {
+				cmd_data = nfc_op.addrs;
+				/* Another address cycle for devices > 128MiB */
+				if (chip->options & NAND_ROW_ADDR_3) {
+					writel_relaxed(cmd_data, cmd_addr);
+					cmd_data = nfc_op.addr5;
+					if (nfc_op.naddrs >= 6)
+						cmd_data |= (nfc_op.addr6 << 8);
+				}
+			}
+		}  else {
+			if (nfc_op.addrs != -1) {
+				int column = nfc_op.addrs;
+				/*
+				 * Change read/write column, read id etc
+				 * Adjust columns for 16 bit bus width
+				 */
+				if ((chip->options & NAND_BUSWIDTH_16) &&
+				    (nfc_op.cmnds[0] == NAND_CMD_READ0 ||
+					nfc_op.cmnds[0] == NAND_CMD_SEQIN ||
+					nfc_op.cmnds[0] == NAND_CMD_RNDOUT ||
+					nfc_op.cmnds[0] == NAND_CMD_RNDIN)) {
+					column >>= 1;
+				}
+				cmd_data = column;
+			}
+		}
+		writel_relaxed(cmd_data, cmd_addr);
+	ndelay(100);
+	}
+
+	cond_delay(nfc_op.cle_ale_delay_ns);
+	if (!nfc_op.data_instr)
+		return 0;
+
+	reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
+	udelay(1000);
+
+	if (!reading) {
+		cond_delay(nfc_op.rdy_delay_ns);
+
+		if (nfc_op.cmnds[0] == NAND_CMD_SEQIN &&
+		    nfc_op.cmnds[1] == NAND_CMD_PAGEPROG) {
+			pl353_nand_write_page_raw(mtd, chip,
+						  instr->ctx.data.buf.out, 0,
+						  nfc_op.addrs);
+		} else {
+			pl353_nand_write_data_op(mtd, instr->ctx.data.buf.out,
+						 len);
+		}
+	}
+
+	else if (reading) {
+		cond_delay(nfc_op.rdy_delay_ns);
+		pl353_nand_read_data_op(chip, instr->ctx.data.buf.in, len);
+	}
+	cond_delay(nfc_op.data_delay_ns);
+
+	return 0;
+}
+
+static const struct nand_op_parser pl353_nfc_op_parser = NAND_OP_PARSER
+	(NAND_OP_PARSER_PATTERN
+		(pl353_nand_cmd_function,
+		NAND_OP_PARSER_PAT_CMD_ELEM(true),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 2048)),
+	NAND_OP_PARSER_PATTERN
+		(pl353_nand_cmd_function,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7),
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false),
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 2048)),
+	NAND_OP_PARSER_PATTERN
+		(pl353_nand_cmd_function,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
+		NAND_OP_PARSER_PAT_CMD_ELEM(true),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
+	NAND_OP_PARSER_PATTERN
+		(pl353_nand_cmd_function,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, 8),
+		NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 2048),
+		NAND_OP_PARSER_PAT_CMD_ELEM(true),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
+	NAND_OP_PARSER_PATTERN
+		(pl353_nand_cmd_function,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false)),
+	);
+
+static int pl353_nfc_exec_op(struct nand_chip *chip,
+			     const struct nand_operation *op,
+			     bool check_only)
+{
+	return nand_op_parser_exec_op(chip, &pl353_nfc_op_parser,
+					      op, check_only);
+}
+
+/**
+ * pl353_nand_device_ready - Check device ready/busy line
+ * @mtd:	Pointer to the mtd_info structure
+ *
+ * Return:	0 on busy or 1 on ready state
+ */
+static int pl353_nand_device_ready(struct mtd_info *mtd)
+{
+	if (pl353_smc_get_nand_int_status_raw()) {
+		pl353_smc_clr_nand_int();
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * pl353_nand_ecc_init - Initialize the ecc information as per the ecc mode
+ * @mtd:	Pointer to the mtd_info structure
+ * @ecc:	Pointer to ECC control structure
+ * @ecc_mode:	ondie ecc status
+ *
+ * This function initializes the ecc block and functional pointers as per the
+ * ecc mode
+ */
+static void pl353_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
+				int ecc_mode)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pl353_nand_info *xnand =
+		container_of(chip, struct pl353_nand_info, chip);
+
+
+	if (ecc_mode == NAND_ECC_ON_DIE) {
+		pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_BYPASS);
+		/*
+		 * On-Die ECC spare bytes offset 8 is used for ECC codes
+		 * Use the BBT pattern descriptors
+		 */
+		chip->bbt_td = &bbt_main_descr;
+		chip->bbt_md = &bbt_mirror_descr;
+		bitmap_set(chip->parameters.get_feature_list,
+			   ONFI_FEATURE_ON_DIE_ECC, ONFI_FEATURE_ON_DIE_ECC_EN);
+		bitmap_set(chip->parameters.set_feature_list,
+			   ONFI_FEATURE_ON_DIE_ECC, ONFI_FEATURE_ON_DIE_ECC_EN);
+	} else {
+		ecc->read_oob = pl353_nand_read_oob;
+		ecc->write_oob = pl353_nand_write_oob;
+
+		ecc->mode = NAND_ECC_HW;
+		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
+		ecc->bytes = 3;
+		ecc->strength = 1;
+		ecc->calculate = pl353_nand_calculate_hwecc;
+		ecc->correct = pl353_nand_correct_data;
+		ecc->hwctl = NULL;
+		ecc->read_page = pl353_nand_read_page_hwecc;
+		ecc->size = PL353_NAND_ECC_SIZE;
+		ecc->write_page = pl353_nand_write_page_hwecc;
+		pl353_smc_set_ecc_pg_size(mtd->writesize);
+		switch (mtd->writesize) {
+		case SZ_512:
+		case SZ_1K:
+		case SZ_2K:
+			pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_APB);
+			break;
+		default:
+			/*
+			 * The software ECC routines won't work with the
+			 * SMC controller
+			 */
+			ecc->calculate = nand_calculate_ecc;
+			ecc->correct = nand_correct_data;
+			ecc->size = 256;
+			break;
+		}
+		if (mtd->writesize <= SZ_512)
+			xnand->addr_cycles = 1;
+		else
+			xnand->addr_cycles = 2;
+
+		if (chip->options & NAND_ROW_ADDR_3)
+			xnand->addr_cycles += 3;
+		else
+			xnand->addr_cycles += 2;
+
+		if (mtd->oobsize == 16)
+			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout16_ops);
+		else if (mtd->oobsize == 64)
+			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout64_ops);
+	}
+}
+
+/**
+ * pl353_nand_probe - Probe method for the NAND driver
+ * @pdev:	Pointer to the platform_device structure
+ *
+ * This function initializes the driver data structures and the hardware.
+ *
+ * Return:	0 on success or error value on failure
+ */
+static int pl353_nand_probe(struct platform_device *pdev)
+{
+	struct pl353_nand_info *xnand;
+	struct mtd_info *mtd;
+	struct nand_chip *nand_chip;
+	struct resource *res;
+
+	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
+	if (!xnand)
+		return -ENOMEM;
+
+	/* Map physical address of NAND flash */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	xnand->nand_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(xnand->nand_base))
+		return PTR_ERR(xnand->nand_base);
+
+	nand_chip = &xnand->chip;
+	mtd = nand_to_mtd(nand_chip);
+	nand_chip->exec_op = pl353_nfc_exec_op;
+	nand_set_controller_data(nand_chip, xnand);
+	mtd->priv = nand_chip;
+	mtd->owner = THIS_MODULE;
+	mtd->name = PL353_NAND_DRIVER_NAME;
+	nand_set_flash_node(nand_chip, pdev->dev.of_node);
+
+	/* Set address of NAND IO lines */
+	nand_chip->IO_ADDR_R = xnand->nand_base;
+	nand_chip->IO_ADDR_W = xnand->nand_base;
+	/* Set the driver entry points for MTD */
+	nand_chip->dev_ready = pl353_nand_device_ready;
+	nand_chip->select_chip = pl353_nand_select_chip;
+	/* If we don't set this delay driver sets 20us by default */
+	nand_chip->chip_delay = 30;
+
+	/* Set the device option and flash width */
+	nand_chip->options = NAND_BUSWIDTH_AUTO;
+	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
+	platform_set_drvdata(pdev, xnand);
+
+	/* first scan to find the device and get the page size */
+	if (nand_scan_ident(mtd, 1, NULL)) {
+		dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
+		return -ENXIO;
+	}
+	pl353_nand_ecc_init(mtd, &nand_chip->ecc, nand_chip->ecc.mode);
+	if (nand_chip->options & NAND_BUSWIDTH_16)
+		pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_16);
+	/* second phase scan */
+	if (nand_scan_tail(mtd)) {
+		dev_err(&pdev->dev, "nand_scan_tail for NAND failed\n");
+		return -ENXIO;
+	}
+
+	mtd_device_register(mtd, NULL, 0);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_remove - Remove method for the NAND driver
+ * @pdev:	Pointer to the platform_device structure
+ *
+ * This function is called if the driver module is being unloaded. It frees all
+ * resources allocated to the device.
+ *
+ * Return:	0 on success or error value on failure
+ */
+static int pl353_nand_remove(struct platform_device *pdev)
+{
+	struct pl353_nand_info *xnand = platform_get_drvdata(pdev);
+	struct mtd_info *mtd = nand_to_mtd(&xnand->chip);
+
+	/* Release resources, unregister device */
+	nand_release(mtd);
+
+	return 0;
+}
+
+/* Match table for device tree binding */
+static const struct of_device_id pl353_nand_of_match[] = {
+	{ .compatible = "arm,pl353-nand-r2p1" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, pl353_nand_of_match);
+
+/*
+ * pl353_nand_driver - This structure defines the NAND subsystem platform driver
+ */
+static struct platform_driver pl353_nand_driver = {
+	.probe		= pl353_nand_probe,
+	.remove		= pl353_nand_remove,
+	.driver		= {
+		.name	= PL353_NAND_DRIVER_NAME,
+		.of_match_table = pl353_nand_of_match,
+	},
+};
+
+module_platform_driver(pl353_nand_driver);
+
+MODULE_AUTHOR("Xilinx, Inc.");
+MODULE_ALIAS("platform:" PL353_NAND_DRIVER_NAME);
+MODULE_DESCRIPTION("ARM PL353 NAND Flash Driver");
+MODULE_LICENSE("GPL");
-- 
2.7.4

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information
  2018-06-06  7:49 ` [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information Naga Sureshkumar Relli
@ 2018-06-07 15:42   ` Miquel Raynal
  2018-06-07 15:47     ` Miquel Raynal
  2018-06-08  5:20     ` Naga Sureshkumar Relli
  0 siblings, 2 replies; 17+ messages in thread
From: Miquel Raynal @ 2018-06-07 15:42 UTC (permalink / raw)
  To: Naga Sureshkumar Relli
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Naga,

On Wed, 6 Jun 2018 13:19:39 +0530, Naga Sureshkumar Relli
<naga.sureshkumar.relli@xilinx.com> wrote:

> Add pl353 static memory controller devicetree binding information.
> 
> Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
> ---
> Changes in v9:
>  - Addressed commens given by Randy Dunlap and Miquel Raynal

Can you please be more specific in your next changelog? I don't
remember what I suggested a few months ago :)

> Changes in v8:
>  - None
> Changes in v7:
> - Corrected clocks description
> - prefixed '#' for address and size cells 
> Changes in v6:
>  - None
> Changes in v5:
>  - Removed timing properties
> Changes in v4:
>  - none
> Changes in v3:
>  - none
> Changes in v2:
>  - modified timing binding info as per onfi timing parameters
>  - add suffix nano second as timing unit
>  - modified the clock names as per the IP spec
> ---
>  .../bindings/memory-controllers/pl353-smc.txt      | 53 ++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> new file mode 100644
> index 0000000..551e66b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> @@ -0,0 +1,53 @@
> +Device tree bindings for ARM PL353 static memory controller
> +
> +PL353 static memory controller supports two kinds of memory
> +interfaces.i.e NAND and SRAM/NOR interfaces.
> +The actual devices are instantiated from the child nodes of pl353 smc node.
> +
> +Required properties:
> +- compatible		: Should be "arm,pl353-smc-r2p1"

I thing Rob prefers:

- compatible: Must be one of:
  * arm, pl353-smc-r2p1

> +- reg			: Controller registers map and length.
> +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
> +			  (See clock bindings for details).
> +- clocks		: Clock phandles (see clock bindings for details).
> +- address-cells		: Address cells, must be 1.
> +- size-cells		: Size cells. Must be 1.

Please avoid padding, just this is enough:

- something: And another thing.

> +
> +Child nodes:
> + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
> +supported as child nodes.
> +
> +Mandatory timing properties for child nodes:
> +- arm,nand-cycle-t0	: Read cycle time(t_rc).
> +- arm,nand-cycle-t1	: Write cycle time(t_wc).
> +- arm,nand-cycle-t2	: re_n assertion delay(t_rea).
> +- arm,nand-cycle-t3	: we_n de-assertion delay(t_wp).
> +- arm,nand-cycle-t4	: Status read time(t_clr)
> +- arm,nand-cycle-t5	: ID read time(t_ar)
> +- arm,nand-cycle-t6	: busy to re_n(t_rr)

I think this has nothing to do in the DT, you should handle timings
from the ->setup_data_interface() hook. If you need, you may use
different compatibles to distinguish different platform data.

> +
> +for nand partition information please refer the below file

s/nand/NAND/

> +Documentation/devicetree/bindings/mtd/partition.txt
> +
> +Example:
> +	pl353smcc_0: pl353smcc@e000e000 {

Why not something more explicit with the '-flash-controller' suffix?

> +			compatible = "arm,pl353-smc-r2p1"
> +			clock-names = "memclk", "aclk";
> +			clocks = <&clkc 11>, <&clkc 44>;
> +			reg = <0xe000e000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			nand_0: nand@e1000000 {
> +				compatible = "arm,pl353-nand-r2p1"

NAND chips do not have their own compatible.

> +				reg = <0xe1000000 0x1000000>;
> +				arm,nand-cycle-t0 = <0x4>;
> +				arm,nand-cycle-t1 = <0x4>;
> +				arm,nand-cycle-t2 = <0x1>;
> +				arm,nand-cycle-t3 = <0x2>;
> +				arm,nand-cycle-t4 = <0x2>;
> +				arm,nand-cycle-t5 = <0x2>;
> +				arm,nand-cycle-t6 = <0x4>;
> +				(...)
> +			};
> +	};


Thanks,
Miquèl

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information
  2018-06-07 15:42   ` Miquel Raynal
@ 2018-06-07 15:47     ` Miquel Raynal
  2018-06-08  5:20     ` Naga Sureshkumar Relli
  1 sibling, 0 replies; 17+ messages in thread
From: Miquel Raynal @ 2018-06-07 15:47 UTC (permalink / raw)
  To: Naga Sureshkumar Relli
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Miquel,

On Thu, 7 Jun 2018 17:42:03 +0200, Miquel Raynal
<miquel.raynal@bootlin.com> wrote:

> Hi Naga,
> 
> On Wed, 6 Jun 2018 13:19:39 +0530, Naga Sureshkumar Relli
> <naga.sureshkumar.relli@xilinx.com> wrote:
> 
> > Add pl353 static memory controller devicetree binding information.
> > 
> > Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
> > ---
> > Changes in v9:
> >  - Addressed commens given by Randy Dunlap and Miquel Raynal  
> 
> Can you please be more specific in your next changelog? I don't
> remember what I suggested a few months ago :)
> 
> > Changes in v8:
> >  - None
> > Changes in v7:
> > - Corrected clocks description
> > - prefixed '#' for address and size cells 
> > Changes in v6:
> >  - None
> > Changes in v5:
> >  - Removed timing properties
> > Changes in v4:
> >  - none
> > Changes in v3:
> >  - none
> > Changes in v2:
> >  - modified timing binding info as per onfi timing parameters
> >  - add suffix nano second as timing unit
> >  - modified the clock names as per the IP spec
> > ---
> >  .../bindings/memory-controllers/pl353-smc.txt      | 53 ++++++++++++++++++++++
> >  1 file changed, 53 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > new file mode 100644
> > index 0000000..551e66b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > @@ -0,0 +1,53 @@
> > +Device tree bindings for ARM PL353 static memory controller
> > +
> > +PL353 static memory controller supports two kinds of memory
> > +interfaces.i.e NAND and SRAM/NOR interfaces.
> > +The actual devices are instantiated from the child nodes of pl353 smc node.
> > +
> > +Required properties:
> > +- compatible		: Should be "arm,pl353-smc-r2p1"  
> 
> I thing Rob prefers:
> 
> - compatible: Must be one of:
>   * arm, pl353-smc-r2p1
> 
> > +- reg			: Controller registers map and length.
> > +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
> > +			  (See clock bindings for details).
> > +- clocks		: Clock phandles (see clock bindings for details).
> > +- address-cells		: Address cells, must be 1.
> > +- size-cells		: Size cells. Must be 1.  
> 
> Please avoid padding, just this is enough:
> 
> - something: And another thing.
> 
> > +
> > +Child nodes:
> > + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
> > +supported as child nodes.
> > +
> > +Mandatory timing properties for child nodes:
> > +- arm,nand-cycle-t0	: Read cycle time(t_rc).
> > +- arm,nand-cycle-t1	: Write cycle time(t_wc).
> > +- arm,nand-cycle-t2	: re_n assertion delay(t_rea).
> > +- arm,nand-cycle-t3	: we_n de-assertion delay(t_wp).
> > +- arm,nand-cycle-t4	: Status read time(t_clr)
> > +- arm,nand-cycle-t5	: ID read time(t_ar)
> > +- arm,nand-cycle-t6	: busy to re_n(t_rr)  
> 
> I think this has nothing to do in the DT, you should handle timings
> from the ->setup_data_interface() hook. If you need, you may use
> different compatibles to distinguish different platform data.

Actually these are NAND-chip dependant and should be derived from the
timings given by the core in the SDR interface structure by
->setup_data_interface().

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static memory controller
  2018-06-06  7:49 ` [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static memory controller Naga Sureshkumar Relli
@ 2018-06-07 16:07   ` Miquel Raynal
  2018-06-19 10:54     ` Naga Sureshkumar Relli
  0 siblings, 1 reply; 17+ messages in thread
From: Miquel Raynal @ 2018-06-07 16:07 UTC (permalink / raw)
  To: Naga Sureshkumar Relli
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Naga,

On Wed, 6 Jun 2018 13:19:40 +0530, Naga Sureshkumar Relli
<naga.sureshkumar.relli@xilinx.com> wrote:

> Add driver for arm pl353 static memory controller. This controller is
> used in xilinx zynq soc for interfacing the nand and nor/sram memory
> devices.

Upper case: Xilinx Zynq, SoC, NAND, NOR, SRAM.

> 
> Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
> ---
> Changes in v9:
>  - Addressed the comments given by Julia Cartwright to the v8 series.
> Changes in v8:
> - None
> Changes in v7:
> - Corrected the kconfig to use tristate selection
> - Corrected the GPL licence ident 
> - Added boundary checks for nand timing parameters 
> Changes in v6:
> - Fixed checkpatch.pl reported warnings
> Changes in v5:
> - Added pl353_smc_get_clkrate function, made pl353_smc_set_cycles as public
>   API
> - Removed nand timing parameter initialization and moved it to nand driver  
> Changes in v4:
> - Modified driver to support multiple instances
> - Used sleep instaed of busywait for delay
> Changes in v3:
> - None
> Changes in v2:
> - Since now the timing parameters are in nano seconds, added logic to convert
>   them to the cycles
> ---
>  drivers/memory/Kconfig                  |   8 +
>  drivers/memory/Makefile                 |   1 +
>  drivers/memory/pl353-smc.c              | 523 ++++++++++++++++++++++++++++++++
>  include/linux/platform_data/pl353-smc.h |  29 ++
>  4 files changed, 561 insertions(+)
>  create mode 100644 drivers/memory/pl353-smc.c
>  create mode 100644 include/linux/platform_data/pl353-smc.h
> 
> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> index 19a0e83..9517da7 100644
> --- a/drivers/memory/Kconfig
> +++ b/drivers/memory/Kconfig
> @@ -153,6 +153,14 @@ config DA8XX_DDRCTL
>  	  Texas Instruments da8xx SoCs. It's used to tweak various memory
>  	  controller configuration options.
>  
> +config PL353_SMC
> +	tristate "ARM PL35X Static Memory Controller(SMC) driver"
> +	default y

This is not restricive at all. If this controller is only on a specific
SoC, you should add another condition to compile the driver?

> +	depends on ARM

Or here             ^

> +	help
> +	  This driver is for the ARM PL351/PL353 Static Memory
> +	  Controller(SMC) module.
> +
>  source "drivers/memory/samsung/Kconfig"
>  source "drivers/memory/tegra/Kconfig"
>  
> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> index 66f5524..58e794d 100644
> --- a/drivers/memory/Makefile
> +++ b/drivers/memory/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
>  obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
>  obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
>  obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
> +obj-$(CONFIG_PL353_SMC)		+= pl353-smc.o
>  
>  obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
>  obj-$(CONFIG_TEGRA_MC)		+= tegra/
> diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c
> new file mode 100644
> index 0000000..8758930
> --- /dev/null
> +++ b/drivers/memory/pl353-smc.c
> @@ -0,0 +1,523 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ARM PL353 SMC driver
> + *
> + * Copyright (C) 2012 Xilinx, Inc
> + * Author: Punnaiah Choudary Kalluri <punnaiah@xilinx.com>
> + * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/platform_data/pl353-smc.h>
> +
> +/* Register definitions */
> +#define PL353_SMC_MEMC_STATUS_OFFS	0	/* Controller status reg, RO */
> +#define PL353_SMC_CFG_CLR_OFFS		0xC	/* Clear config reg, WO */
> +#define PL353_SMC_DIRECT_CMD_OFFS	0x10	/* Direct command reg, WO */
> +#define PL353_SMC_SET_CYCLES_OFFS	0x14	/* Set cycles register, WO */
> +#define PL353_SMC_SET_OPMODE_OFFS	0x18	/* Set opmode register, WO */
> +#define PL353_SMC_ECC_STATUS_OFFS	0x400	/* ECC status register */
> +#define PL353_SMC_ECC_MEMCFG_OFFS	0x404	/* ECC mem config reg */
> +#define PL353_SMC_ECC_MEMCMD1_OFFS	0x408	/* ECC mem cmd1 reg */
> +#define PL353_SMC_ECC_MEMCMD2_OFFS	0x40C	/* ECC mem cmd2 reg */
> +#define PL353_SMC_ECC_VALUE0_OFFS	0x418	/* ECC value 0 reg */
> +
> +/* Controller status register specific constants */
> +#define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT	6
> +
> +/* Clear configuration register specific constants */
> +#define PL353_SMC_CFG_CLR_INT_CLR_1	0x10
> +#define PL353_SMC_CFG_CLR_ECC_INT_DIS_1	0x40
> +#define PL353_SMC_CFG_CLR_INT_DIS_1	0x2
> +#define PL353_SMC_CFG_CLR_DEFAULT_MASK	(PL353_SMC_CFG_CLR_INT_CLR_1 | \
> +					 PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \
> +					 PL353_SMC_CFG_CLR_INT_DIS_1)
> +
> +/* Set cycles register specific constants */
> +#define PL353_SMC_SET_CYCLES_T0_MASK	0xF
> +#define PL353_SMC_SET_CYCLES_T0_SHIFT	0
> +#define PL353_SMC_SET_CYCLES_T1_MASK	0xF
> +#define PL353_SMC_SET_CYCLES_T1_SHIFT	4
> +#define PL353_SMC_SET_CYCLES_T2_MASK	0x7
> +#define PL353_SMC_SET_CYCLES_T2_SHIFT	8
> +#define PL353_SMC_SET_CYCLES_T3_MASK	0x7
> +#define PL353_SMC_SET_CYCLES_T3_SHIFT	11
> +#define PL353_SMC_SET_CYCLES_T4_MASK	0x7
> +#define PL353_SMC_SET_CYCLES_T4_SHIFT	14
> +#define PL353_SMC_SET_CYCLES_T5_MASK	0x7
> +#define PL353_SMC_SET_CYCLES_T5_SHIFT	17
> +#define PL353_SMC_SET_CYCLES_T6_MASK	0xF
> +#define PL353_SMC_SET_CYCLES_T6_SHIFT	20
> +
> +/* ECC status register specific constants */
> +#define PL353_SMC_ECC_STATUS_BUSY	BIT(6)
> +
> +/* ECC memory config register specific constants */
> +#define PL353_SMC_ECC_MEMCFG_MODE_MASK	0xC
> +#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT	2
> +#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK	0xC
> +
> +#define PL353_SMC_DC_UPT_NAND_REGS	((4 << 23) |	/* CS: NAND chip */ \
> +				 (2 << 21))	/* UpdateRegs operation */
> +
> +#define PL353_NAND_ECC_CMD1	((0x80)       |	/* Write command */ \
> +				 (0 << 8)     |	/* Read command */ \
> +				 (0x30 << 16) |	/* Read End command */ \
> +				 (1 << 24))	/* Read End command calid */
> +
> +#define PL353_NAND_ECC_CMD2	((0x85)	      |	/* Write col change cmd */ \
> +				 (5 << 8)     |	/* Read col change cmd */ \
> +				 (0xE0 << 16) |	/* Read col change end cmd */ \
> +				 (1 << 24)) /* Read col change end cmd valid */
> +#define PL353_NAND_ECC_BUSY_TIMEOUT	(1 * HZ)
> +/**
> + * struct pl353_smc_data - Private smc driver structure
> + * @devclk:		Pointer to the peripheral clock
> + * @aperclk:		Pointer to the APER clock
> + */
> +struct pl353_smc_data {
> +	struct clk		*memclk;
> +	struct clk		*aclk;
> +};
> +
> +/* SMC virtual register base */
> +static void __iomem *pl353_smc_base;
> +
> +/**
> + * pl353_smc_set_buswidth - Set memory buswidth
> + * @bw:	Memory buswidth (8 | 16)
> + * Return: 0 on success or negative errno.
> + */
> +int pl353_smc_set_buswidth(unsigned int bw)
> +{
> +	if (bw != PL353_SMC_MEM_WIDTH_8  && bw != PL353_SMC_MEM_WIDTH_16)
> +		return -EINVAL;
> +
> +	writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS);
> +	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
> +	       PL353_SMC_DIRECT_CMD_OFFS);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth);
> +
> +/**
> + * pl353_smc_set_cycles - Set memory timing parameters
> + * @t0:	t_rc		read cycle time
> + * @t1:	t_wc		write cycle time
> + * @t2:	t_rea/t_ceoe	output enable assertion delay
> + * @t3:	t_wp		write enable deassertion delay
> + * @t4:	t_clr/t_pc	page cycle time
> + * @t5:	t_ar/t_ta	ID read time/turnaround time
> + * @t6:	t_rr		busy to RE timing
> + *
> + * Sets NAND chip specific timing parameters.
> + */
> +static void pl353_smc_set_cycles(u32 t0, u32 t1, u32 t2, u32 t3, u32
> +			      t4, u32 t5, u32 t6)
> +{
> +	t0 &= PL353_SMC_SET_CYCLES_T0_MASK;
> +	t1 = (t1 & PL353_SMC_SET_CYCLES_T1_MASK) <<
> +			PL353_SMC_SET_CYCLES_T1_SHIFT;
> +	t2 = (t2 & PL353_SMC_SET_CYCLES_T2_MASK) <<
> +			PL353_SMC_SET_CYCLES_T2_SHIFT;
> +	t3 = (t3 & PL353_SMC_SET_CYCLES_T3_MASK) <<
> +			PL353_SMC_SET_CYCLES_T3_SHIFT;
> +	t4 = (t4 & PL353_SMC_SET_CYCLES_T4_MASK) <<
> +			PL353_SMC_SET_CYCLES_T4_SHIFT;
> +	t5 = (t5 & PL353_SMC_SET_CYCLES_T5_MASK) <<
> +			PL353_SMC_SET_CYCLES_T5_SHIFT;
> +	t6 = (t6 & PL353_SMC_SET_CYCLES_T6_MASK) <<
> +			PL353_SMC_SET_CYCLES_T6_SHIFT;
> +
> +	t0 |= t1 | t2 | t3 | t4 | t5 | t6;
> +
> +	writel(t0, pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS);
> +	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
> +	       PL353_SMC_DIRECT_CMD_OFFS);
> +}
> +
> +/**
> + * pl353_smc_ecc_is_busy - Read ecc busy flag
> + * Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
> + */
> +int pl353_smc_ecc_is_busy(void)
> +{
> +	return !!(readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) &
> +		  PL353_SMC_ECC_STATUS_BUSY);

You can return a bool and avoid the '!!'.

> +}
> +EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy);
> +
> +/**
> + * pl353_smc_get_ecc_val - Read ecc_valueN registers
> + * @ecc_reg:	Index of the ecc_value reg (0..3)
> + * Return: the content of the requested ecc_value register.
> + *
> + * There are four valid ecc_value registers. The argument is truncated to stay
> + * within this valid boundary.
> + */
> +u32 pl353_smc_get_ecc_val(int ecc_reg)
> +{
> +	u32 addr, reg;
> +
> +	ecc_reg &= 3;

This is not readable. Please check for the validity of ecc_reg with
standard '<' '>' operators.

> +	addr = PL353_SMC_ECC_VALUE0_OFFS + (ecc_reg << 2);

2 should be defined

> +	reg = readl(pl353_smc_base + addr);
> +
> +	return reg;
> +}
> +EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val);
> +
> +/**
> + * pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
> + * Return: the raw_int_status1 bit from the memc_status register

If you use kernel-doc format, should be "@return".

> + */
> +int pl353_smc_get_nand_int_status_raw(void)
> +{
> +	u32 reg;
> +
> +	reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS);
> +	reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
> +	reg &= 1;
> +
> +	return reg;
> +}
> +EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw);
> +
> +/**
> + * pl353_smc_clr_nand_int - Clear NAND interrupt
> + */
> +void pl353_smc_clr_nand_int(void)
> +{
> +	writel(PL353_SMC_CFG_CLR_INT_CLR_1,
> +	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
> +}
> +EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int);
> +
> +/**
> + * pl353_smc_set_ecc_mode - Set SMC ECC mode
> + * @mode:	ECC mode (BYPASS, APB, MEM)
> + * Return: 0 on success or negative errno.
> + */
> +int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)
> +{
> +	u32 reg;
> +	int ret = 0;
> +
> +	switch (mode) {
> +	case PL353_SMC_ECCMODE_BYPASS:
> +	case PL353_SMC_ECCMODE_APB:
> +	case PL353_SMC_ECCMODE_MEM:
> +
> +		reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> +		reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK;
> +		reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;
> +		writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> +
> +		break;
> +	default:
> +		ret = -EINVAL;
> +	}
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode);
> +
> +/**
> + * pl353_smc_set_ecc_pg_size - Set SMC ECC page size
> + * @pg_sz:	ECC page size
> + * Return: 0 on success or negative errno.
> + */
> +int pl353_smc_set_ecc_pg_size(unsigned int pg_sz)
> +{
> +	u32 reg, sz;
> +
> +	switch (pg_sz) {
> +	case 0:
> +		sz = 0;
> +		break;
> +	case SZ_512:
> +		sz = 1;
> +		break;
> +	case SZ_1K:
> +		sz = 2;
> +		break;
> +	case SZ_2K:
> +		sz = 3;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> +	reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK;
> +	reg |= sz;
> +	writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size);
> +
> +static int __maybe_unused pl353_smc_suspend(struct device *dev)
> +{
> +	struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
> +
> +	clk_disable(pl353_smc->memclk);
> +	clk_disable(pl353_smc->aclk);

Are you sure you don't need to save any of the configured registers?

> +
> +	return 0;
> +}
> +
> +static int __maybe_unused pl353_smc_resume(struct device *dev)
> +{
> +	int ret;
> +	struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
> +
> +	ret = clk_enable(pl353_smc->aclk);
> +	if (ret) {
> +		dev_err(dev, "Cannot enable axi domain clock.\n");
> +		return ret;
> +	}
> +
> +	ret = clk_enable(pl353_smc->memclk);
> +	if (ret) {
> +		dev_err(dev, "Cannot enable memory clock.\n");
> +		clk_disable(pl353_smc->aclk);
> +		return ret;
> +	}

New line

> +	return ret;
> +}
> +
> +static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
> +			 pl353_smc_resume);
> +
> +/**
> + * pl353_smc_init_nand_interface - Initialize the NAND interface
> + * @pdev:	Pointer to the platform_device struct
> + * @nand_node:	Pointer to the pl353_nand device_node struct
> + */
> +static void pl353_smc_init_nand_interface(struct platform_device *pdev,
> +					  struct device_node *nand_node)
> +{
> +	u32 t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr;
> +	int err;
> +	unsigned long timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;

Maybe this should be defined later in the code.

New line.

> +	/* nand-cycle-<X> property is refer to the NAND flash timing
> +	 * mapping between dts and the NAND flash AC timing
> +	 *  X  : AC timing name
> +	 *  t0 : t_rc
> +	 *  t1 : t_wc
> +	 *  t2 : t_rea
> +	 *  t3 : t_wp
> +	 *  t4 : t_clr
> +	 *  t5 : t_ar
> +	 *  t6 : t_rr
> +	 */
> +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t0", &t_rc);
> +	if (err) {
> +		dev_warn(&pdev->dev, "arm,nand-cycle-t0 not in device tree");
> +		goto default_nand_timing;
> +	}
> +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t1", &t_wc);
> +	if (err) {
> +		dev_warn(&pdev->dev, "arm,nand-cycle-t1 not in device tree");
> +		goto default_nand_timing;
> +	}
> +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t2", &t_rea);
> +	if (err) {
> +		dev_warn(&pdev->dev, "arm,nand-cycle-t2 not in device tree");
> +		goto default_nand_timing;
> +	}
> +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t3", &t_wp);
> +	if (err) {
> +		dev_warn(&pdev->dev, "arm,nand-cycle-t3 not in device tree");
> +		goto default_nand_timing;
> +	}
> +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t4", &t_clr);
> +	if (err) {
> +		dev_warn(&pdev->dev, "arm,nand-cycle-t4 not in device tree");
> +		goto default_nand_timing;
> +	}
> +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t5", &t_ar);
> +	if (err) {
> +		dev_warn(&pdev->dev, "arm,nand-cycle-t5 not in device tree");
> +		goto default_nand_timing;
> +	}
> +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t6", &t_rr);
> +	if (err) {
> +		dev_warn(&pdev->dev, "arm,nand-cycle-t6 not in device tree");
> +		goto default_nand_timing;
> +	}

See the comment in the bindings about this section.

> +
> +default_nand_timing:
> +	/*
> +	 * Default assume 50MHz clock (20ns cycle time) and 3V operation
> +	 * The SET_CYCLES_REG register value depends on the flash device.
> +	 * Look in to the device datasheet and change its value, This value
> +	 * is for 2Gb Numonyx flash.

No :)

The controller is not supposed to work with only one chip, right? So it
should not embed any chip-specific information.

If this chip is not ONFI nor JEDEC and is not supported yet, the right
way to do is to write a manufacturer driver.

> +	 */
> +	if (err) {
> +		/* set default NAND flash timing property */
> +		dev_warn(&pdev->dev, "Using default timing for");
> +		dev_warn(&pdev->dev, "2Gb Numonyx MT29F2G08ABAEAWP NAND flash");
> +		dev_warn(&pdev->dev, "t_wp, t_clr, t_ar are set to 2");
> +		dev_warn(&pdev->dev, "t_rc, t_wc, t_rr are set to 4");
> +		dev_warn(&pdev->dev, "t_rea is set to 1");
> +		t_rc = 4;
> +		t_wc = 4;
> +		t_rr = 4;
> +		t_rea = 1;
> +		t_wp = 2;
> +		t_clr = 2;
> +		t_ar = 2;
> +	}
> +
> +	pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8);
> +	pl353_smc_set_cycles(t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr);
> +	writel(PL353_SMC_CFG_CLR_INT_CLR_1,
> +	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
> +	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
> +	       PL353_SMC_DIRECT_CMD_OFFS);
> +	/* Wait till the ECC operation is complete */
> +	do {
> +		if (pl353_smc_ecc_is_busy())
> +			cpu_relax();
> +		else
> +			break;
> +	} while (!time_after_eq(jiffies, timeout));
> +
> +	if (time_after_eq(jiffies, timeout))
> +		dev_err(&pdev->dev, "nand ecc busy status timed out");
> +
> +	writel(PL353_NAND_ECC_CMD1,
> +	       pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS);
> +	writel(PL353_NAND_ECC_CMD2,
> +	       pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS);
> +}
> +
> +static const struct of_device_id pl353_smc_supported_children[] = {
> +	{ .compatible = "cfi-flash" },
> +	{ .compatible = "arm,pl353-nand-r2p1",
> +	.data = pl353_smc_init_nand_interface },

Please put the compatibles on another line and align data with them.

> +	{}
> +};
> +
> +static int pl353_smc_probe(struct platform_device *pdev)
> +{
> +	struct pl353_smc_data *pl353_smc;
> +	struct device_node *child;
> +	struct resource *res;
> +	int err;
> +	struct device_node *of_node = pdev->dev.of_node;
> +	void (*init)(struct platform_device *pdev,
> +		     struct device_node *nand_node);
> +	const struct of_device_id *match = NULL;
> +
> +	pl353_smc = devm_kzalloc(&pdev->dev, sizeof(*pl353_smc), GFP_KERNEL);
> +	if (!pl353_smc)
> +		return -ENOMEM;
> +
> +	/* Get the NAND controller virtual address */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	pl353_smc_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(pl353_smc_base))
> +		return PTR_ERR(pl353_smc_base);
> +
> +	pl353_smc->aclk = devm_clk_get(&pdev->dev, "aclk");
> +	if (IS_ERR(pl353_smc->aclk)) {
> +		dev_err(&pdev->dev, "aclk clock not found.\n");
> +		return PTR_ERR(pl353_smc->aclk);
> +	}
> +
> +	pl353_smc->memclk = devm_clk_get(&pdev->dev, "memclk");
> +	if (IS_ERR(pl353_smc->memclk)) {
> +		dev_err(&pdev->dev, "memclk clock not found.\n");
> +		return PTR_ERR(pl353_smc->memclk);
> +	}
> +
> +	err = clk_prepare_enable(pl353_smc->aclk);
> +	if (err) {
> +		dev_err(&pdev->dev, "Unable to enable AXI clock.\n");
> +		return err;
> +	}
> +
> +	err = clk_prepare_enable(pl353_smc->memclk);
> +	if (err) {
> +		dev_err(&pdev->dev, "Unable to enable memory clock.\n");
> +		goto out_clk_dis_aper;
> +	}
> +
> +	platform_set_drvdata(pdev, pl353_smc);
> +
> +	/* clear interrupts */
> +	writel(PL353_SMC_CFG_CLR_DEFAULT_MASK,
> +	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
> +
> +	/* Find compatible children. Only a single child is supported */
> +	for_each_available_child_of_node(of_node, child) {
> +		match = of_match_node(pl353_smc_supported_children, child);
> +		if (!match) {
> +			dev_warn(&pdev->dev, "unsupported child node\n");
> +			continue;
> +		}
> +		break;
> +	}
> +	if (!match) {
> +		dev_err(&pdev->dev, "no matching children\n");
> +		goto out_clk_disable;
> +	}
> +
> +	init = match->data;
> +	if (init)
> +		init(pdev, child);
> +	of_platform_device_create(child, NULL, &pdev->dev);
> +
> +	return 0;
> +
> +out_clk_disable:
> +	clk_disable_unprepare(pl353_smc->memclk);
> +out_clk_dis_aper:
> +	clk_disable_unprepare(pl353_smc->aclk);
> +
> +	return err;
> +}
> +
> +static int pl353_smc_remove(struct platform_device *pdev)
> +{
> +	struct pl353_smc_data *pl353_smc = platform_get_drvdata(pdev);
> +
> +	clk_disable_unprepare(pl353_smc->memclk);
> +	clk_disable_unprepare(pl353_smc->aclk);
> +
> +	return 0;
> +}
> +
> +/* Match table for device tree binding */
> +static const struct of_device_id pl353_smc_of_match[] = {
> +	{ .compatible = "arm,pl353-smc-r2p1" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, pl353_smc_of_match);
> +
> +static struct platform_driver pl353_smc_driver = {
> +	.probe		= pl353_smc_probe,
> +	.remove		= pl353_smc_remove,
> +	.driver		= {
> +		.name	= "pl353-smc",
> +		.pm	= &pl353_smc_dev_pm_ops,
> +		.of_match_table = pl353_smc_of_match,
> +	},
> +};
> +
> +module_platform_driver(pl353_smc_driver);
> +
> +MODULE_AUTHOR("Xilinx, Inc.");
> +MODULE_DESCRIPTION("ARM PL353 SMC Driver");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/platform_data/pl353-smc.h b/include/linux/platform_data/pl353-smc.h

I don't think you really need a separate file for these enums? Unless
it is really platform specific?

> new file mode 100644
> index 0000000..fc4129e
> --- /dev/null
> +++ b/include/linux/platform_data/pl353-smc.h
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ARM PL353 SMC Driver Header
> + *
> + * Copyright (C) 2017 Xilinx, Inc
> + */
> +
> +#ifndef __LINUX_MEMORY_PL353_SMC_H
> +#define __LINUX_MEMORY_PL353_SMC_H
> +
> +enum pl353_smc_ecc_mode {
> +	PL353_SMC_ECCMODE_BYPASS = 0,
> +	PL353_SMC_ECCMODE_APB = 1,
> +	PL353_SMC_ECCMODE_MEM = 2
> +};
> +
> +enum pl353_smc_mem_width {
> +	PL353_SMC_MEM_WIDTH_8 = 0,
> +	PL353_SMC_MEM_WIDTH_16 = 1
> +};
> +
> +u32 pl353_smc_get_ecc_val(int ecc_reg);
> +int pl353_smc_ecc_is_busy(void);
> +int pl353_smc_get_nand_int_status_raw(void);
> +void pl353_smc_clr_nand_int(void);
> +int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode);
> +int pl353_smc_set_ecc_pg_size(unsigned int pg_sz);
> +int pl353_smc_set_buswidth(unsigned int bw);
> +#endif

Thanks,
Miquèl

-- 
Miquel Raynal, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface
  2018-06-06  7:49 ` [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface Naga Sureshkumar Relli
@ 2018-06-07 19:59   ` Miquel Raynal
  2018-06-08 12:23     ` Naga Sureshkumar Relli
  0 siblings, 1 reply; 17+ messages in thread
From: Miquel Raynal @ 2018-06-07 19:59 UTC (permalink / raw)
  To: Naga Sureshkumar Relli
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Naga,

This is a partial review, enough for this version, see below.

On Wed, 6 Jun 2018 13:19:42 +0530, Naga Sureshkumar Relli
<naga.sureshkumar.relli@xilinx.com> wrote:

> Add driver for arm pl353 static memory controller nand interface with

s/nand/NAND/

> HW ECC support. This controller is used in xilinx zynq soc for interfacing

s/HW/hardware/

> the nand flash memory.
> 
> Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
> ---
> Changes in v9:
>  - Addressed the below comments given by Miquel
>  - instead of using pl353_nand_write32, use directly writel_relaxed
>  - Fixed check patch warnings
>  - Renamed write_buf/read_buf to write_data_op/read_data_op
>  - use BIT macro instead of 1 << nr
>  - Use NAND_ROW_ADDR_3 flag
>  - Use nand_wait_ready()
>  - Removed swecc functions
>  - Use address cycles as per size, instead of reading it from Parameter page
>  - Instead of writing too many patterns, use optional property
> Changes in v8:
>  - Added exec_op() implementation
>  - Fixed the below v7 review comments
>  - removed mtd_info from pl353_nand_info struct
>  - Corrected ecc layout offsets
>  - Added on-die ecc support
> Changes in v7:
>  - Currently not implemented the memclk rate adjustments. I will
>    look into this later and once the basic driver is accepted.
>  - Fixed GPL licence ident
> Changes in v6:
>  - Fixed the checkpatch.pl reported warnings
>  - Using the address cycles information from the onfi param page
>    earlier it is hardcoded to 5 in driver
> Changes in v5:
>  - Configure the nand timing parameters as per the onfi spec
> Changes in v4:
>  - Updated the driver to sync with pl353_smc driver APIs
> Changes in v3:
>  - implemented the proper error codes
>  - further breakdown this patch to multiple sets
>  - added the controller and driver details to Documentation section
>  - updated the licenece to GPLv2
>  - reorganized the pl353_nand_ecc_init function
> Changes in v2:
>  - use "depends on" rather than "select" option in kconfig
>  - remove unused variable parts
>  - remove dummy helper and use writel_relaxed directly
> ---
> 
>  drivers/mtd/nand/raw/Kconfig      |    7 +
>  drivers/mtd/nand/raw/Makefile     |    3 +
>  drivers/mtd/nand/raw/pl353_nand.c | 1236 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 1246 insertions(+)
>  create mode 100644 drivers/mtd/nand/raw/pl353_nand.c
> 
> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
> index 6871ff0..1c5d528 100644
> --- a/drivers/mtd/nand/raw/Kconfig
> +++ b/drivers/mtd/nand/raw/Kconfig
> @@ -530,4 +530,11 @@ config MTD_NAND_MTK
>  	  Enables support for NAND controller on MTK SoCs.
>  	  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>  
> +config MTD_NAND_PL353
> +	tristate "ARM Pl353 NAND flash driver"
> +	depends on MTD_NAND && ARM
> +	depends on PL353_SMC
> +	help
> +	  Enables support for PrimeCell Static Memory Controller PL353.
> +
>  endif # MTD_NAND
> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
> index 165b7ef..6855a0d 100644
> --- a/drivers/mtd/nand/raw/Makefile
> +++ b/drivers/mtd/nand/raw/Makefile
> @@ -56,7 +56,9 @@ obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
>  obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
>  obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
>  obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
> +obj-$(CONFIG_MTD_NAND_PL353)		+= pl353_nand.o
>  
> +CFLAGS_{nand_base.o} := -DDEBUG

Nope :)

>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>  nand-objs += nand_amd.o
>  nand-objs += nand_hynix.o
> @@ -64,3 +66,4 @@ nand-objs += nand_macronix.o
>  nand-objs += nand_micron.o
>  nand-objs += nand_samsung.o
>  nand-objs += nand_toshiba.o
> +

Extra space here

> diff --git a/drivers/mtd/nand/raw/pl353_nand.c b/drivers/mtd/nand/raw/pl353_nand.c
> new file mode 100644
> index 0000000..a880eade
> --- /dev/null
> +++ b/drivers/mtd/nand/raw/pl353_nand.c
> @@ -0,0 +1,1236 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ARM PL353 NAND flash controller driver
> + *
> + * Copyright (C) 2017 Xilinx, Inc
> + * Author: Punnaiah chowdary kalluri <punnaiah@xilinx.com>
> + * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
> + *
> + */
> +
> +#include <linux/err.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/irq.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/rawnand.h>
> +#include <linux/mtd/nand_ecc.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/platform_data/pl353-smc.h>
> +
> +#define PL353_NAND_DRIVER_NAME "pl353-nand"
> +
> +/* NAND flash driver defines */
> +#define PL353_NAND_CMD_PHASE	1	/* End command valid in command phase */
> +#define PL353_NAND_DATA_PHASE	2	/* End command valid in data phase */
> +#define PL353_NAND_ECC_SIZE	512	/* Size of data for ECC operation */
> +
> +/* Flash memory controller operating parameters */
> +
> +#define PL353_NAND_ECC_CONFIG	(BIT(4)  |	/* ECC read at end of page */ \
> +				 (0 << 5))	/* No Jumping */
> +
> +/* AXI Address definitions */
> +#define START_CMD_SHIFT		3
> +#define END_CMD_SHIFT		11
> +#define END_CMD_VALID_SHIFT	20
> +#define ADDR_CYCLES_SHIFT	21
> +#define CLEAR_CS_SHIFT		21
> +#define ECC_LAST_SHIFT		10
> +#define COMMAND_PHASE		(0 << 19)
> +#define DATA_PHASE		BIT(19)
> +
> +#define PL353_NAND_ECC_LAST	BIT(ECC_LAST_SHIFT)	/* Set ECC_Last */
> +#define PL353_NAND_CLEAR_CS	BIT(CLEAR_CS_SHIFT)	/* Clear chip select */
> +
> +#define ONDIE_ECC_FEATURE_ADDR	0x90
> +#define PL353_NAND_ECC_BUSY_TIMEOUT	(1 * HZ)
> +#define PL353_NAND_DEV_BUSY_TIMEOUT	(1 * HZ)
> +#define PL353_NAND_LAST_TRANSFER_LENGTH	4
> +
> +struct pl353_nfc_op {
> +	u32 cmnds[4];
> +	u32 thirdrow;
> +	u32 type;
> +	u32 end_cmd;
> +	u32 addrs;
> +	bool wait;
> +	u32 len;
> +	u32 naddrs;
> +	unsigned int data_instr_idx;
> +	const struct nand_op_instr *data_instr;
> +	unsigned int rdy_timeout_ms;
> +	unsigned int rdy_delay_ns;
> +	unsigned int data_delay_ns;
> +	unsigned int cle_ale_delay_ns;
> +	u32 addr5;
> +	u32 addr6;
> +};
> +
> +/**
> + * struct pl353_nand_info - Defines the NAND flash driver instance
> + * @chip:		NAND chip information structure
> + * @nand_base:		Virtual address of the NAND flash device
> + * @end_cmd_pending:	End command is pending
> + * @end_cmd:		End command
> + * @row_addr_cycles:	Row address cycles
> + * @col_addr_cycles:	Column address cycles
> + * @address:		Page address
> + * @cmd_pending:	More command is needed
> + */
> +struct pl353_nand_info {
> +	struct nand_chip chip;
> +	void __iomem *nand_base;
> +	unsigned long end_cmd_pending;
> +	unsigned long end_cmd;
> +	u8 addr_cycles;
> +	u32 address;
> +	u32 cmd_pending;
> +	struct completion complete;
> +};
> +
> +static int pl353_ecc_ooblayout16_ecc(struct mtd_info *mtd, int section,
> +				     struct mtd_oob_region *oobregion)
> +{
> +	struct nand_chip *chip = mtd_to_nand(mtd);
> +
> +	if (section >= chip->ecc.steps)
> +		return -ERANGE;
> +
> +	oobregion->offset = (section * chip->ecc.bytes);
> +	oobregion->length = chip->ecc.bytes;
> +
> +	return 0;
> +}
> +
> +static int pl353_ecc_ooblayout16_free(struct mtd_info *mtd, int section,
> +				      struct mtd_oob_region *oobregion)
> +{
> +	struct nand_chip *chip = mtd_to_nand(mtd);
> +
> +	if (section >= chip->ecc.steps)
> +		return -ERANGE;
> +
> +	oobregion->offset = (section * chip->ecc.bytes) + 8;
> +	oobregion->length = 8;
> +
> +	return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops pl353_ecc_ooblayout16_ops = {
> +	.ecc = pl353_ecc_ooblayout16_ecc,
> +	.free = pl353_ecc_ooblayout16_free,
> +};
> +
> +static int pl353_ecc_ooblayout64_ecc(struct mtd_info *mtd, int section,
> +				     struct mtd_oob_region *oobregion)
> +{
> +	struct nand_chip *chip = mtd_to_nand(mtd);
> +
> +	if (section >= chip->ecc.steps)
> +		return -ERANGE;
> +
> +	oobregion->offset = (section * chip->ecc.bytes) + 52;
> +	oobregion->length = chip->ecc.bytes;
> +
> +	return 0;
> +}
> +
> +static int pl353_ecc_ooblayout64_free(struct mtd_info *mtd, int section,
> +				      struct mtd_oob_region *oobregion)
> +{
> +	struct nand_chip *chip = mtd_to_nand(mtd);
> +
> +	if (section)
> +		return -ERANGE;
> +
> +	if (section >= chip->ecc.steps)
> +		return -ERANGE;
> +
> +	oobregion->offset = (section * chip->ecc.bytes) + 2;
> +	oobregion->length = 50;
> +
> +	return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops pl353_ecc_ooblayout64_ops = {
> +	.ecc = pl353_ecc_ooblayout64_ecc,
> +	.free = pl353_ecc_ooblayout64_free,
> +};
> +
> +/* Generic flash bbt decriptors */
> +static u8 bbt_pattern[] = { 'B', 'b', 't', '0' };
> +static u8 mirror_pattern[] = { '1', 't', 'b', 'B' };
> +
> +static struct nand_bbt_descr bbt_main_descr = {
> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> +	.offs = 4,
> +	.len = 4,
> +	.veroffs = 20,
> +	.maxblocks = 4,
> +	.pattern = bbt_pattern
> +};
> +
> +static struct nand_bbt_descr bbt_mirror_descr = {
> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> +	.offs = 4,
> +	.len = 4,
> +	.veroffs = 20,
> +	.maxblocks = 4,
> +	.pattern = mirror_pattern
> +};
> +
> +/**
> + * pl353_nand_read_data_op - read chip data into buffer
> + * @chip:	Pointer to the NAND chip info structure
> + * @in:		Pointer to the buffer to store read data
> + * @len:	Number of bytes to read
> + * Return:	Always return zero
> + */
> +static int pl353_nand_read_data_op(struct nand_chip *chip,
> +				   u8 *in,
> +				   unsigned int len)
> +{
> +	int i;
> +
> +	if (IS_ALIGNED((uint32_t)in, sizeof(uint32_t)) &&
> +	    IS_ALIGNED(len, sizeof(uint32_t))) {
> +		u32 *ptr = (u32 *)in;
> +
> +		len /= 4;
> +		for (i = 0; i < len; i++)
> +			ptr[i] = readl(chip->IO_ADDR_R);
> +	} else {
> +		for (i = 0; i < len; i++)
> +			in[i] = readb(chip->IO_ADDR_R);

I'm not sure you need these IO_ADDR_R/W. Better not to use them in a
new driver.

> +	}
> +
> +	return 0;
> +}
> +
> +/**
> + * pl353_nand_write_buf - write buffer to chip
> + * @mtd:	Pointer to the mtd info structure
> + * @buf:	Pointer to the buffer to store write data
> + * @len:	Number of bytes to write
> + */
> +static void pl353_nand_write_data_op(struct mtd_info *mtd, const u8 *buf,
> +				     int len)
> +{
> +	int i;
> +	struct nand_chip *chip = mtd_to_nand(mtd);
> +
> +	if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
> +	    IS_ALIGNED(len, sizeof(uint32_t))) {
> +		u32 *ptr = (u32 *)buf;
> +
> +		len /= 4;
> +		for (i = 0; i < len; i++)
> +			writel(ptr[i], chip->IO_ADDR_W);
> +	} else {
> +		for (i = 0; i < len; i++)
> +			writeb(buf[i], chip->IO_ADDR_W);
> +	}
> +}
> +
> +/**
> + * pl353_nand_calculate_hwecc - Calculate Hardware ECC
> + * @mtd:	Pointer to the mtd_info structure
> + * @data:	Pointer to the page data
> + * @ecc:	Pointer to the ECC buffer where ECC data needs to be stored
> + *
> + * This function retrieves the Hardware ECC data from the controller and returns
> + * ECC data back to the MTD subsystem.
> + *
> + * Return:	0 on success or error value on failure
> + */
> +static int pl353_nand_calculate_hwecc(struct mtd_info *mtd,
> +				      const u8 *data, u8 *ecc)
> +{
> +	u32 ecc_value, ecc_status;
> +	u8 ecc_reg, ecc_byte;
> +	unsigned long timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
> +	/* Wait till the ECC operation is complete or timeout */
> +	do {
> +		if (pl353_smc_ecc_is_busy())
> +			cpu_relax();
> +		else
> +			break;
> +	} while (!time_after_eq(jiffies, timeout));
> +
> +	if (time_after_eq(jiffies, timeout)) {
> +		pr_err("%s timed out\n", __func__);
> +		return -ETIMEDOUT;
> +	}
> +
> +	for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {

So here you hardcode the fact that there are 5 'blocks'. This is NAND
chip dependent, right?

> +		/* Read ECC value for each block */
> +		ecc_value = pl353_smc_get_ecc_val(ecc_reg);
> +		ecc_status = (ecc_value >> 24) & 0xFF;

Please define all these values.

Make ecc_status a byte if you always need it to be 8-bit. Then you can
drop the & 0xFF.
 
> +		/* ECC value valid */
> +		if (ecc_status & 0x40) {

Please define this 0x40

> +			for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
> +				/* Copy ECC bytes to MTD buffer */
> +				*ecc = ~ecc_value & 0xFF;

This is not a copy, you invert the bytes, I don't really know why.
Perhaps a comment would be appreciated.

> +				ecc_value = ecc_value >> 8;
> +				ecc++;
> +			}
> +		} else {
> +			pr_warn("%s status failed\n", __func__);
> +			return -1;
> +		}
> +	}
> +	return 0;
> +}
> +
> +/**
> + * onehot - onehot function
> + * @value:	Value to check for onehot
> + *
> + * This function checks whether a value is onehot or not.
> + * onehot is if and only if onebit is set.
> + *
> + * Return:	1 if it is onehot else 0
> + */
> +static int onehot(unsigned short value)

Why not returning a boolean?
> +{
> +	return (value & (value - 1)) == 0;
> +}
> +
> +/**
> + * pl353_nand_correct_data - ECC correction function
> + * @mtd:	Pointer to the mtd_info structure
> + * @buf:	Pointer to the page data
> + * @read_ecc:	Pointer to the ECC value read from spare data area
> + * @calc_ecc:	Pointer to the calculated ECC value
> + *
> + * This function corrects the ECC single bit errors & detects 2-bit errors.
> + *
> + * Return:	0 if no ECC errors found
> + *		1 if single bit error found and corrected.
> + *		-1 if multiple ECC errors found.

"multiple uncorrectable ECC errors"

> + */
> +static int pl353_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
> +				   unsigned char *read_ecc,
> +				   unsigned char *calc_ecc)
> +{
> +	unsigned char bit_addr;
> +	unsigned int byte_addr;
> +	unsigned short ecc_odd, ecc_even, read_ecc_lower, read_ecc_upper;
> +	unsigned short calc_ecc_lower, calc_ecc_upper;
> +
> +	read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
> +	read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
> +
> +	calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
> +	calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
> +
> +	ecc_odd = read_ecc_lower ^ calc_ecc_lower;
> +	ecc_even = read_ecc_upper ^ calc_ecc_upper;
> +
> +	/* no error */
> +	if (ecc_odd == 0 && ecc_even == 0)

you can use "!ecc_odd && !ecc_even"

> +		return 0;
> +
> +	if (ecc_odd == (~ecc_even & 0xfff)) {
> +		/* bits [11:3] of error code is byte offset */
> +		byte_addr = (ecc_odd >> 3) & 0x1ff;
> +		/* bits [2:0] of error code is bit offset */
> +		bit_addr = ecc_odd & 0x7;
> +		/* Toggling error bit */
> +		buf[byte_addr] ^= (BIT(bit_addr));
> +		return 1;
> +	}
> +	/* one error in parity */
> +	if (onehot(ecc_odd | ecc_even) == 1)
> +		return 1;
> +
> +	/* Uncorrectable error */
> +	return -1;
> +}
> +
> +static int pl353_dev_timeout(struct mtd_info *mtd, struct nand_chip *chip)
> +{
> +	unsigned long timeout = jiffies + PL353_NAND_DEV_BUSY_TIMEOUT;
> +
> +	do {
> +		if (chip->dev_ready(mtd))
> +			break;
> +		cpu_relax();
> +	} while (!time_after_eq(jiffies, timeout));
> +
> +	if (time_after_eq(jiffies, timeout)) {
> +		pr_err("%s timed out\n", __func__);
> +		return -1;
> +	}
> +
> +	return 0;
> +}
> +
> +static void pl353_prepare_cmd(struct mtd_info *mtd, struct nand_chip *chip,
> +			      int page, int column, int start_cmd, int end_cmd,
> +			      bool read)
> +{
> +	unsigned long data_phase_addr;
> +	u32 end_cmd_valid = 0;
> +	void __iomem *cmd_addr;
> +	unsigned long cmd_phase_addr = 0, cmd_data = 0;
> +
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +
> +	end_cmd_valid = read ? 1 : 0;
> +
> +	cmd_phase_addr = (unsigned long __force)xnand->nand_base +
> +			 ((xnand->addr_cycles
> +			 << ADDR_CYCLES_SHIFT) |
> +			 (end_cmd_valid << END_CMD_VALID_SHIFT) |
> +			 (COMMAND_PHASE) |
> +			 (end_cmd << END_CMD_SHIFT) |
> +			 (start_cmd << START_CMD_SHIFT));
> +	cmd_addr = (void __iomem * __force)cmd_phase_addr;
> +
> +	/* Get the data phase address */
> +	data_phase_addr = (unsigned long __force)xnand->nand_base +
> +			  ((0x0 << CLEAR_CS_SHIFT) |
> +			  (0 << END_CMD_VALID_SHIFT) |
> +			  (DATA_PHASE) |
> +			  (end_cmd << END_CMD_SHIFT) |
> +			  (0x0 << ECC_LAST_SHIFT));
> +
> +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> +	chip->IO_ADDR_W = chip->IO_ADDR_R;
> +	if (chip->options & NAND_BUSWIDTH_16)
> +		column /= 2;
> +	cmd_data = column;
> +	if (mtd->writesize > PL353_NAND_ECC_SIZE) {
> +		cmd_data |= page << 16;
> +		/* Another address cycle for devices > 128MiB */
> +		if (chip->options & NAND_ROW_ADDR_3) {
> +			writel_relaxed(cmd_data, cmd_addr);
> +			cmd_data = (page >> 16);
> +		}
> +	} else {
> +		cmd_data |= page << 8;
> +	}
> +
> +	writel_relaxed(cmd_data, cmd_addr);
> +}
> +
> +/**
> + * pl353_nand_read_oob - [REPLACEABLE] the most common OOB data read function
> + * @mtd:	Pointer to the mtd info structure
> + * @chip:	Pointer to the NAND chip info structure
> + * @page:	Page number to read
> + *
> + * Return:	Always return zero
> + */
> +static int pl353_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
> +			       int page)
> +{
> +	unsigned long data_phase_addr;
> +	u8 *p;
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> +
> +	chip->pagebuf = -1;
> +	if (mtd->writesize < PL353_NAND_ECC_SIZE)
> +		return 0;
> +
> +	pl353_prepare_cmd(mtd, chip, page, mtd->writesize, NAND_CMD_READ0,
> +			  NAND_CMD_READSTART, 1);
> +
> +	ndelay(100);
> +	pl353_dev_timeout(mtd, chip);
> +
> +	p = chip->oob_poi;
> +	pl353_nand_read_data_op(chip, p,
> +				(mtd->oobsize -
> +				PL353_NAND_LAST_TRANSFER_LENGTH));
> +	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> +	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	return 0;
> +}
> +
> +/**
> + * pl353_nand_write_oob - [REPLACEABLE] the most common OOB data write function
> + * @mtd:	Pointer to the mtd info structure
> + * @chip:	Pointer to the NAND chip info structure
> + * @page:	Page number to write
> + *
> + * Return:	Zero on success and EIO on failure
> + */
> +static int pl353_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> +				int page)
> +{
> +	const u8 *buf = chip->oob_poi;
> +	unsigned long data_phase_addr;
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> +	u32 addrcycles = 0;
> +
> +	chip->pagebuf = -1;
> +	addrcycles = xnand->addr_cycles;
> +	pl353_prepare_cmd(mtd, chip, page, mtd->writesize, NAND_CMD_SEQIN,
> +			  NAND_CMD_PAGEPROG, 0);
> +	ndelay(100);
> +	pl353_nand_write_data_op(mtd, buf,
> +				 (mtd->oobsize -
> +				 PL353_NAND_LAST_TRANSFER_LENGTH));
> +	buf += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> +	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
> +	data_phase_addr += nand_offset;

What you do here is unclear and suspect...

> +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> +	pl353_nand_write_data_op(mtd, buf, PL353_NAND_LAST_TRANSFER_LENGTH);
> +	nand_wait_ready(mtd);
> +
> +	return 0;
> +}
> +
> +/**
> + * pl353_nand_read_page_raw - [Intern] read raw page data without ecc
> + * @mtd:		Pointer to the mtd info structure
> + * @chip:		Pointer to the NAND chip info structure
> + * @buf:		Pointer to the data buffer
> + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> + * @page:		Page number to read
> + *
> + * Return:	Always return zero
> + */
> +static int pl353_nand_read_page_raw(struct mtd_info *mtd,
> +				    struct nand_chip *chip,
> +				    u8 *buf, int oob_required, int page)
> +{
> +	unsigned long data_phase_addr;
> +	u8 *p;
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> +
> +	pl353_nand_read_data_op(chip, buf, mtd->writesize);
> +	p = chip->oob_poi;
> +	pl353_nand_read_data_op(chip, p,
> +				(mtd->oobsize -
> +				PL353_NAND_LAST_TRANSFER_LENGTH));
> +	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> +
> +	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	return 0;
> +}
> +
> +/**
> + * pl353_nand_write_page_raw - [Intern] raw page write function
> + * @mtd:		Pointer to the mtd info structure
> + * @chip:		Pointer to the NAND chip info structure
> + * @buf:		Pointer to the data buffer
> + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> + * @page:		Page number to write
> + *
> + * Return:	Always return zero
> + */
> +static int pl353_nand_write_page_raw(struct mtd_info *mtd,
> +				     struct nand_chip *chip,
> +				     const u8 *buf, int oob_required,
> +				     int page)
> +{
> +	unsigned long data_phase_addr;
> +	u8 *p;
> +
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> +
> +	pl353_nand_write_data_op(mtd, buf, mtd->writesize);
> +	p = chip->oob_poi;
> +	pl353_nand_write_data_op(mtd, p,
> +				 (mtd->oobsize -
> +				 PL353_NAND_LAST_TRANSFER_LENGTH));
> +	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> +	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> +
> +	pl353_nand_write_data_op(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> +	ndelay(100);
> +	nand_wait_ready(mtd);
> +	return 0;
> +}
> +
> +/**
> + * nand_write_page_hwecc - Hardware ECC based page write function
> + * @mtd:		Pointer to the mtd info structure
> + * @chip:		Pointer to the NAND chip info structure
> + * @buf:		Pointer to the data buffer
> + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> + * @page:		Page number to write
> + *
> + * This functions writes data and hardware generated ECC values in to the page.
> + *
> + * Return:	Always return zero
> + */
> +static int pl353_nand_write_page_hwecc(struct mtd_info *mtd,
> +				       struct nand_chip *chip,
> +				       const u8 *buf, int oob_required,
> +				       int page)
> +{
> +	int eccsize = chip->ecc.size;
> +	int eccsteps = chip->ecc.steps;
> +	u8 *ecc_calc = chip->ecc.calc_buf;
> +	u8 *oob_ptr;
> +	const u8 *p = buf;
> +	u32 ret;
> +	unsigned long data_phase_addr;
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> +
> +	pl353_prepare_cmd(mtd, chip, page, 0, NAND_CMD_SEQIN,
> +			  NAND_CMD_PAGEPROG, 0);
> +	ndelay(100);
> +	for ( ; (eccsteps - 1); eccsteps--) {
> +		pl353_nand_write_data_op(mtd, p, eccsize);
> +		p += eccsize;
> +	}
> +	pl353_nand_write_data_op(mtd, p,
> +				 (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
> +	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	/* Set ECC Last bit to 1 */
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_ECC_LAST;
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> +	pl353_nand_write_data_op(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	p = buf;
> +	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
> +
> +	/* Wait for ECC to be calculated and read the error values */
> +	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi,
> +					 0, chip->ecc.total);
> +	if (ret)
> +		return ret;

Space

> +	/* Clear ECC last bit */
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr &= ~PL353_NAND_ECC_LAST;
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> +
> +	/* Write the spare area with ECC bytes */
> +	oob_ptr = chip->oob_poi;
> +	pl353_nand_write_data_op(mtd, oob_ptr,
> +				 (mtd->oobsize -
> +				 PL353_NAND_LAST_TRANSFER_LENGTH));
> +
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> +	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> +	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +	pl353_nand_write_data_op(mtd, oob_ptr, PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	/*
> +	 * Apply this short delay always to ensure that we do wait tWB in any
> +	 * case on any machine.
> +	 */
> +	ndelay(100);
> +	nand_wait_ready(mtd);
> +
> +	return 0;
> +}
> +
> +/**
> + * pl353_nand_read_page_hwecc - Hardware ECC based page read function
> + * @mtd:		Pointer to the mtd info structure
> + * @chip:		Pointer to the NAND chip info structure
> + * @buf:		Pointer to the buffer to store read data
> + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> + * @page:		Page number to read
> + *
> + * This functions reads data and checks the data integrity by comparing hardware
> + * generated ECC values and read ECC values from spare area.
> + *
> + * Return:	0 always and updates ECC operation status in to MTD structure
> + */
> +static int pl353_nand_read_page_hwecc(struct mtd_info *mtd,
> +				      struct nand_chip *chip,
> +				      u8 *buf, int oob_required, int page)
> +{
> +	int i, stat, eccsize = chip->ecc.size;
> +	int eccbytes = chip->ecc.bytes;
> +	int eccsteps = chip->ecc.steps;
> +	u8 *p = buf;
> +	u8 *ecc_calc = chip->ecc.calc_buf;
> +	u8 *ecc = chip->ecc.code_buf;
> +	unsigned int max_bitflips = 0;
> +	u8 *oob_ptr;
> +	u32 ret;
> +	unsigned long data_phase_addr;
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> +
> +	pl353_prepare_cmd(mtd, chip, page, 0, NAND_CMD_READ0,
> +			  NAND_CMD_READSTART, 1);
> +	ndelay(100);
> +	pl353_dev_timeout(mtd, chip);
> +
> +	for ( ; (eccsteps - 1); eccsteps--) {
> +		pl353_nand_read_data_op(chip, p, eccsize);
> +		p += eccsize;
> +	}
> +	pl353_nand_read_data_op(chip, p,
> +				(eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
> +	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	/* Set ECC Last bit to 1 */
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_ECC_LAST;
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> +	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	/* Read the calculated ECC value */
> +	p = buf;
> +	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
> +
> +	/* Clear ECC last bit */
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr &= ~PL353_NAND_ECC_LAST;
> +	data_phase_addr += nand_offset;
> +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> +
> +	/* Read the stored ECC value */
> +	oob_ptr = chip->oob_poi;
> +	pl353_nand_read_data_op(chip, oob_ptr,
> +				(mtd->oobsize -
> +				PL353_NAND_LAST_TRANSFER_LENGTH));
> +
> +	/* de-assert chip select */
> +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> +	data_phase_addr -= nand_offset;
> +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> +	data_phase_addr += nand_offset;

Ok, now I am convinced this is not the right way. Please forget about
chip->IO_ADDR_*.

> +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> +
> +	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> +	pl353_nand_read_data_op(chip, oob_ptr, PL353_NAND_LAST_TRANSFER_LENGTH);
> +
> +	ret = mtd_ooblayout_get_eccbytes(mtd, ecc, chip->oob_poi, 0,
> +					 chip->ecc.total);
> +	if (ret)
> +		return ret;
> +
> +	eccsteps = chip->ecc.steps;
> +	p = buf;
> +
> +	/* Check ECC error for all blocks and correct if it is correctable */
> +	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
> +		stat = chip->ecc.correct(mtd, p, &ecc[i], &ecc_calc[i]);
> +		if (stat < 0) {
> +			mtd->ecc_stats.failed++;
> +		} else {
> +			mtd->ecc_stats.corrected += stat;
> +			max_bitflips = max_t(unsigned int, max_bitflips, stat);
> +		}
> +	}
> +
> +	return max_bitflips;
> +}
> +
> +/**
> + * pl353_nand_select_chip - Select the flash device
> + * @mtd:	Pointer to the mtd info structure
> + * @chip:	Pointer to the NAND chip info structure
> + *
> + * This function is empty as the NAND controller handles chip select line
> + * internally based on the chip address passed in command and data phase.
> + */
> +static void pl353_nand_select_chip(struct mtd_info *mtd, int chip)
> +{
> +}
> +
> +/* NAND framework ->exec_op() hooks and related helpers */
> +static void pl353_nfc_parse_instructions(struct nand_chip *chip,
> +					 const struct nand_subop *subop,
> +					 struct pl353_nfc_op *nfc_op)
> +{
> +	const struct nand_op_instr *instr = NULL;
> +	unsigned int op_id, offset, naddrs;
> +	int i, len;
> +	const u8 *addrs;
> +
> +	memset(nfc_op, 0, sizeof(struct pl353_nfc_op));
> +	for (op_id = 0; op_id < subop->ninstrs; op_id++) {
> +		nfc_op->len = nand_subop_get_data_len(subop, op_id);
> +		len = nand_subop_get_data_len(subop, op_id);
> +		instr = &subop->instrs[op_id];
> +		if (subop->ninstrs == 1)
> +			nfc_op->cmnds[0] = -1;
> +		switch (instr->type) {
> +		case NAND_OP_CMD_INSTR:
> +			nfc_op->type = NAND_OP_CMD_INSTR;
> +			if (op_id)
> +				nfc_op->cmnds[1] = instr->ctx.cmd.opcode;
> +			else
> +				nfc_op->cmnds[0] = instr->ctx.cmd.opcode;
> +			nfc_op->cle_ale_delay_ns = instr->delay_ns;
> +			break;
> +
> +		case NAND_OP_ADDR_INSTR:
> +			offset = nand_subop_get_addr_start_off(subop, op_id);
> +			naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
> +			addrs = &instr->ctx.addr.addrs[offset];
> +			nfc_op->addrs = instr->ctx.addr.addrs[offset];
> +			for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) {
> +				nfc_op->addrs |= instr->ctx.addr.addrs[i] <<
> +						 (8 * i);
> +			}
> +
> +			if (naddrs >= 5)
> +				nfc_op->addr5 = addrs[4];
> +			if (naddrs >= 6)
> +				nfc_op->addr6 = addrs[5];
> +			nfc_op->naddrs = nand_subop_get_num_addr_cyc(subop,
> +								     op_id);
> +			nfc_op->cle_ale_delay_ns = instr->delay_ns;
> +			break;
> +
> +		case NAND_OP_DATA_IN_INSTR:
> +			nfc_op->data_instr = instr;
> +			nfc_op->type = NAND_OP_DATA_IN_INSTR;
> +			nfc_op->data_instr_idx = op_id;
> +			nfc_op->data_delay_ns = instr->delay_ns;
> +			break;
> +
> +		case NAND_OP_DATA_OUT_INSTR:
> +			nfc_op->data_instr = instr;
> +			nfc_op->type = NAND_OP_DATA_IN_INSTR;
> +			nfc_op->data_instr_idx = op_id;
> +			nfc_op->data_delay_ns = instr->delay_ns;
> +			break;
> +
> +		case NAND_OP_WAITRDY_INSTR:
> +			nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
> +			nfc_op->rdy_delay_ns = instr->delay_ns;
> +			nfc_op->wait = true;
> +			break;
> +		}
> +	}
> +}
> +
> +static void cond_delay(unsigned int ns)
> +{
> +	if (!ns)
> +		return;
> +
> +	if (ns < 10000)
> +		ndelay(ns);
> +	else
> +		udelay(DIV_ROUND_UP(ns, 1000));
> +}
> +
> +/**
> + * pl353_nand_cmd_function - Send command to NAND device
> + * @chip:	Pointer to the NAND chip info structure
> + * @subop:	Pointer to array of instructions
> + * Return:	Always return zero
> + */
> +static int pl353_nand_cmd_function(struct nand_chip *chip,
> +				   const struct nand_subop *subop)
> +{
> +	struct mtd_info *mtd = nand_to_mtd(chip);
> +	const struct nand_op_instr *instr;
> +	struct pl353_nfc_op nfc_op = {};
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +	void __iomem *cmd_addr;
> +	unsigned long cmd_data = 0, end_cmd_valid = 0;
> +	unsigned long cmd_phase_addr, data_phase_addr, end_cmd;
> +	unsigned int op_id, len, offset;
> +	bool reading;
> +
> +	pl353_nfc_parse_instructions(chip, subop, &nfc_op);
> +	instr = nfc_op.data_instr;
> +	op_id = nfc_op.data_instr_idx;
> +	len = nand_subop_get_data_len(subop, op_id);
> +	offset = nand_subop_get_data_start_off(subop, op_id);
> +
> +	if (nfc_op.cmnds[0] != -1) {
> +		pl353_smc_clr_nand_int();
> +		/* Get the command phase address */
> +		if (nfc_op.cmnds[1] != 0) {
> +			if (nfc_op.cmnds[0] == NAND_CMD_SEQIN)
> +				end_cmd_valid = 0;
> +			else
> +				end_cmd_valid = 1;
> +			end_cmd = nfc_op.cmnds[1];
> +		}  else {
> +			end_cmd = 0x0;
> +		}
> +		cmd_phase_addr = (unsigned long __force)xnand->nand_base +
> +				 ((nfc_op.naddrs << ADDR_CYCLES_SHIFT) |
> +				 (end_cmd_valid << END_CMD_VALID_SHIFT) |
> +				 (COMMAND_PHASE) |
> +				 (end_cmd << END_CMD_SHIFT) |
> +				 (nfc_op.cmnds[0] << START_CMD_SHIFT));
> +
> +		cmd_addr = (void __iomem * __force)cmd_phase_addr;
> +		/* Get the data phase address */
> +		end_cmd_valid = 0;
> +
> +		data_phase_addr = (unsigned long __force)xnand->nand_base +
> +				  ((0x0 << CLEAR_CS_SHIFT) |
> +				  (end_cmd_valid << END_CMD_VALID_SHIFT) |
> +				  (DATA_PHASE) |
> +				  (end_cmd << END_CMD_SHIFT) |
> +				  (0x0 << ECC_LAST_SHIFT));
> +		chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> +		chip->IO_ADDR_W = chip->IO_ADDR_R;
> +		/* Command phase AXI Read & Write */
> +		if (nfc_op.naddrs >= 5) {
> +			if (mtd->writesize > PL353_NAND_ECC_SIZE) {
> +				cmd_data = nfc_op.addrs;
> +				/* Another address cycle for devices > 128MiB */
> +				if (chip->options & NAND_ROW_ADDR_3) {
> +					writel_relaxed(cmd_data, cmd_addr);
> +					cmd_data = nfc_op.addr5;
> +					if (nfc_op.naddrs >= 6)
> +						cmd_data |= (nfc_op.addr6 << 8);
> +				}
> +			}
> +		}  else {
> +			if (nfc_op.addrs != -1) {
> +				int column = nfc_op.addrs;
> +				/*
> +				 * Change read/write column, read id etc
> +				 * Adjust columns for 16 bit bus width
> +				 */
> +				if ((chip->options & NAND_BUSWIDTH_16) &&
> +				    (nfc_op.cmnds[0] == NAND_CMD_READ0 ||
> +					nfc_op.cmnds[0] == NAND_CMD_SEQIN ||
> +					nfc_op.cmnds[0] == NAND_CMD_RNDOUT ||
> +					nfc_op.cmnds[0] == NAND_CMD_RNDIN)) {
> +					column >>= 1;
> +				}
> +				cmd_data = column;
> +			}
> +		}
> +		writel_relaxed(cmd_data, cmd_addr);
> +	ndelay(100);
> +	}
> +
> +	cond_delay(nfc_op.cle_ale_delay_ns);
> +	if (!nfc_op.data_instr)
> +		return 0;
> +
> +	reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
> +	udelay(1000);

What is this delay ?

> +
> +	if (!reading) {
> +		cond_delay(nfc_op.rdy_delay_ns);
> +
> +		if (nfc_op.cmnds[0] == NAND_CMD_SEQIN &&
> +		    nfc_op.cmnds[1] == NAND_CMD_PAGEPROG) {
> +			pl353_nand_write_page_raw(mtd, chip,
> +						  instr->ctx.data.buf.out, 0,
> +						  nfc_op.addrs);
> +		} else {
> +			pl353_nand_write_data_op(mtd, instr->ctx.data.buf.out,
> +						 len);
> +		}
> +	}
> +
> +	else if (reading) {
> +		cond_delay(nfc_op.rdy_delay_ns);
> +		pl353_nand_read_data_op(chip, instr->ctx.data.buf.in, len);
> +	}
> +	cond_delay(nfc_op.data_delay_ns);
> +
> +	return 0;
> +}
> +
> +static const struct nand_op_parser pl353_nfc_op_parser = NAND_OP_PARSER
> +	(NAND_OP_PARSER_PATTERN
> +		(pl353_nand_cmd_function,
> +		NAND_OP_PARSER_PAT_CMD_ELEM(true),
> +		NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
> +		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 2048)),
> +	NAND_OP_PARSER_PATTERN
> +		(pl353_nand_cmd_function,
> +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> +		NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7),
> +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> +		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false),
> +		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 2048)),
> +	NAND_OP_PARSER_PATTERN
> +		(pl353_nand_cmd_function,
> +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> +		NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
> +		NAND_OP_PARSER_PAT_CMD_ELEM(true),
> +		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
> +	NAND_OP_PARSER_PATTERN
> +		(pl353_nand_cmd_function,
> +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> +		NAND_OP_PARSER_PAT_ADDR_ELEM(false, 8),
> +		NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 2048),
> +		NAND_OP_PARSER_PAT_CMD_ELEM(true),
> +		NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
> +	NAND_OP_PARSER_PATTERN
> +		(pl353_nand_cmd_function,
> +		NAND_OP_PARSER_PAT_CMD_ELEM(false)),
> +	);
> +
> +static int pl353_nfc_exec_op(struct nand_chip *chip,
> +			     const struct nand_operation *op,
> +			     bool check_only)
> +{
> +	return nand_op_parser_exec_op(chip, &pl353_nfc_op_parser,
> +					      op, check_only);
> +}
> +
> +/**
> + * pl353_nand_device_ready - Check device ready/busy line
> + * @mtd:	Pointer to the mtd_info structure
> + *
> + * Return:	0 on busy or 1 on ready state
> + */
> +static int pl353_nand_device_ready(struct mtd_info *mtd)
> +{
> +	if (pl353_smc_get_nand_int_status_raw()) {
> +		pl353_smc_clr_nand_int();

A clear is really needed here?

> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +
> +/**
> + * pl353_nand_ecc_init - Initialize the ecc information as per the ecc mode
> + * @mtd:	Pointer to the mtd_info structure
> + * @ecc:	Pointer to ECC control structure
> + * @ecc_mode:	ondie ecc status
> + *
> + * This function initializes the ecc block and functional pointers as per the
> + * ecc mode
> + */
> +static void pl353_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
> +				int ecc_mode)
> +{
> +	struct nand_chip *chip = mtd_to_nand(mtd);
> +	struct pl353_nand_info *xnand =
> +		container_of(chip, struct pl353_nand_info, chip);
> +
> +
> +	if (ecc_mode == NAND_ECC_ON_DIE) {
> +		pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_BYPASS);
> +		/*
> +		 * On-Die ECC spare bytes offset 8 is used for ECC codes
> +		 * Use the BBT pattern descriptors
> +		 */
> +		chip->bbt_td = &bbt_main_descr;
> +		chip->bbt_md = &bbt_mirror_descr;
> +		bitmap_set(chip->parameters.get_feature_list,
> +			   ONFI_FEATURE_ON_DIE_ECC, ONFI_FEATURE_ON_DIE_ECC_EN);
> +		bitmap_set(chip->parameters.set_feature_list,
> +			   ONFI_FEATURE_ON_DIE_ECC, ONFI_FEATURE_ON_DIE_ECC_EN);
> +	} else {
> +		ecc->read_oob = pl353_nand_read_oob;
> +		ecc->write_oob = pl353_nand_write_oob;
> +
> +		ecc->mode = NAND_ECC_HW;
> +		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
> +		ecc->bytes = 3;
> +		ecc->strength = 1;
> +		ecc->calculate = pl353_nand_calculate_hwecc;

I'm not sure you need this calculate()...

> +		ecc->correct = pl353_nand_correct_data;
> +		ecc->hwctl = NULL;

You can drop the line.

> +		ecc->read_page = pl353_nand_read_page_hwecc;
> +		ecc->size = PL353_NAND_ECC_SIZE;
> +		ecc->write_page = pl353_nand_write_page_hwecc;
> +		pl353_smc_set_ecc_pg_size(mtd->writesize);
> +		switch (mtd->writesize) {
> +		case SZ_512:
> +		case SZ_1K:
> +		case SZ_2K:
> +			pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_APB);
> +			break;
> +		default:
> +			/*
> +			 * The software ECC routines won't work with the
> +			 * SMC controller
> +			 */
> +			ecc->calculate = nand_calculate_ecc;
> +			ecc->correct = nand_correct_data;
> +			ecc->size = 256;
> +			break;
> +		}
> +		if (mtd->writesize <= SZ_512)
> +			xnand->addr_cycles = 1;
> +		else
> +			xnand->addr_cycles = 2;
> +
> +		if (chip->options & NAND_ROW_ADDR_3)
> +			xnand->addr_cycles += 3;
> +		else
> +			xnand->addr_cycles += 2;
> +
> +		if (mtd->oobsize == 16)
> +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout16_ops);
> +		else if (mtd->oobsize == 64)
> +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout64_ops);

else?

> +	}
> +}
> +
> +/**
> + * pl353_nand_probe - Probe method for the NAND driver
> + * @pdev:	Pointer to the platform_device structure
> + *
> + * This function initializes the driver data structures and the hardware.
> + *
> + * Return:	0 on success or error value on failure
> + */
> +static int pl353_nand_probe(struct platform_device *pdev)
> +{
> +	struct pl353_nand_info *xnand;

xnand is a strange name, more and more because its a bout NAND
controller data, not NAND chip.

> +	struct mtd_info *mtd;
> +	struct nand_chip *nand_chip;

This one you can call it just "nand" or "chip".

> +	struct resource *res;
> +
> +	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
> +	if (!xnand)
> +		return -ENOMEM;
> +
> +	/* Map physical address of NAND flash */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	xnand->nand_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(xnand->nand_base))
> +		return PTR_ERR(xnand->nand_base);
> +
> +	nand_chip = &xnand->chip;
> +	mtd = nand_to_mtd(nand_chip);
> +	nand_chip->exec_op = pl353_nfc_exec_op;
> +	nand_set_controller_data(nand_chip, xnand);
> +	mtd->priv = nand_chip;
> +	mtd->owner = THIS_MODULE;
> +	mtd->name = PL353_NAND_DRIVER_NAME;

A label property in the DT might overwrite this value.

> +	nand_set_flash_node(nand_chip, pdev->dev.of_node);
> +
> +	/* Set address of NAND IO lines */
> +	nand_chip->IO_ADDR_R = xnand->nand_base;
> +	nand_chip->IO_ADDR_W = xnand->nand_base;
> +	/* Set the driver entry points for MTD */
> +	nand_chip->dev_ready = pl353_nand_device_ready;
> +	nand_chip->select_chip = pl353_nand_select_chip;
> +	/* If we don't set this delay driver sets 20us by default */
> +	nand_chip->chip_delay = 30;

And why 30 is better?

I suppose you mean the core, not the driver. The driver is this file.

> +
> +	/* Set the device option and flash width */
> +	nand_chip->options = NAND_BUSWIDTH_AUTO;
> +	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
> +	platform_set_drvdata(pdev, xnand);
> +
> +	/* first scan to find the device and get the page size */
> +	if (nand_scan_ident(mtd, 1, NULL)) {
> +		dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
> +		return -ENXIO;
> +	}
> +	pl353_nand_ecc_init(mtd, &nand_chip->ecc, nand_chip->ecc.mode);
> +	if (nand_chip->options & NAND_BUSWIDTH_16)
> +		pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_16);
> +	/* second phase scan */
> +	if (nand_scan_tail(mtd)) {
> +		dev_err(&pdev->dev, "nand_scan_tail for NAND failed\n");
> +		return -ENXIO;
> +	}
> +
> +	mtd_device_register(mtd, NULL, 0);
> +
> +	return 0;
> +}
> +
> +/**
> + * pl353_nand_remove - Remove method for the NAND driver
> + * @pdev:	Pointer to the platform_device structure
> + *
> + * This function is called if the driver module is being unloaded. It frees all
> + * resources allocated to the device.
> + *
> + * Return:	0 on success or error value on failure
> + */
> +static int pl353_nand_remove(struct platform_device *pdev)
> +{
> +	struct pl353_nand_info *xnand = platform_get_drvdata(pdev);
> +	struct mtd_info *mtd = nand_to_mtd(&xnand->chip);
> +
> +	/* Release resources, unregister device */
> +	nand_release(mtd);
> +
> +	return 0;
> +}
> +
> +/* Match table for device tree binding */
> +static const struct of_device_id pl353_nand_of_match[] = {
> +	{ .compatible = "arm,pl353-nand-r2p1" },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, pl353_nand_of_match);
> +
> +/*
> + * pl353_nand_driver - This structure defines the NAND subsystem platform driver
> + */
> +static struct platform_driver pl353_nand_driver = {
> +	.probe		= pl353_nand_probe,
> +	.remove		= pl353_nand_remove,
> +	.driver		= {
> +		.name	= PL353_NAND_DRIVER_NAME,
> +		.of_match_table = pl353_nand_of_match,
> +	},
> +};
> +
> +module_platform_driver(pl353_nand_driver);
> +
> +MODULE_AUTHOR("Xilinx, Inc.");
> +MODULE_ALIAS("platform:" PL353_NAND_DRIVER_NAME);
> +MODULE_DESCRIPTION("ARM PL353 NAND Flash Driver");
> +MODULE_LICENSE("GPL");

Thanks,
Miquèl

-- 
Miquel Raynal, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 17+ messages in thread

* RE: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information
  2018-06-07 15:42   ` Miquel Raynal
  2018-06-07 15:47     ` Miquel Raynal
@ 2018-06-08  5:20     ` Naga Sureshkumar Relli
  2018-06-08  5:51       ` Boris Brezillon
  2018-06-08  7:23       ` Miquel Raynal
  1 sibling, 2 replies; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-08  5:20 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Miquel,

Thanks for the review.

> -----Original Message-----
> From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> Sent: Thursday, June 7, 2018 9:12 PM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> Cc: boris.brezillon@bootlin.com; richard@nod.at; wmw2@infradead.org;
> computersforpeace@gmail.com; marek.vasut@gmail.com; f.fainelli@gmail.com;
> mmayer@broadcom.com; rogerq@ti.com; ladis@linux-mips.org; ada@thorsis.com;
> honghui.zhang@mediatek.com; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> nagasureshkumarrelli@gmail.com
> Subject: Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree
> binding information
> 
> Hi Naga,
> 
> On Wed, 6 Jun 2018 13:19:39 +0530, Naga Sureshkumar Relli
> <naga.sureshkumar.relli@xilinx.com> wrote:
> 
> > Add pl353 static memory controller devicetree binding information.
> >
> > Signed-off-by: Naga Sureshkumar Relli
> > <naga.sureshkumar.relli@xilinx.com>
> > ---
> > Changes in v9:
> >  - Addressed commens given by Randy Dunlap and Miquel Raynal
> 
> Can you please be more specific in your next changelog? I don't remember what I suggested a
> few months ago :)
Ok, I will update.

> 
> > Changes in v8:
> >  - None
> > Changes in v7:
> > - Corrected clocks description
> > - prefixed '#' for address and size cells Changes in v6:
> >  - None
> > Changes in v5:
> >  - Removed timing properties
> > Changes in v4:
> >  - none
> > Changes in v3:
> >  - none
> > Changes in v2:
> >  - modified timing binding info as per onfi timing parameters
> >  - add suffix nano second as timing unit
> >  - modified the clock names as per the IP spec
> > ---
> >  .../bindings/memory-controllers/pl353-smc.txt      | 53
> ++++++++++++++++++++++
> >  1 file changed, 53 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > new file mode 100644
> > index 0000000..551e66b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.t
> > +++ xt
> > @@ -0,0 +1,53 @@
> > +Device tree bindings for ARM PL353 static memory controller
> > +
> > +PL353 static memory controller supports two kinds of memory
> > +interfaces.i.e NAND and SRAM/NOR interfaces.
> > +The actual devices are instantiated from the child nodes of pl353 smc node.
> > +
> > +Required properties:
> > +- compatible		: Should be "arm,pl353-smc-r2p1"
> 
> I thing Rob prefers:
> 
> - compatible: Must be one of:
>   * arm, pl353-smc-r2p1
Are you suggesting any other compatibles?
Or just a change from "should be to Must be one of"?
> 
> > +- reg			: Controller registers map and length.
> > +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
> > +			  (See clock bindings for details).
> > +- clocks		: Clock phandles (see clock bindings for details).
> > +- address-cells		: Address cells, must be 1.
> > +- size-cells		: Size cells. Must be 1.
> 
> Please avoid padding, just this is enough:
> 
> - something: And another thing.
Ok, I will update it.

> 
> > +
> > +Child nodes:
> > + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash"
> > +drivers are supported as child nodes.
> > +
> > +Mandatory timing properties for child nodes:
> > +- arm,nand-cycle-t0	: Read cycle time(t_rc).
> > +- arm,nand-cycle-t1	: Write cycle time(t_wc).
> > +- arm,nand-cycle-t2	: re_n assertion delay(t_rea).
> > +- arm,nand-cycle-t3	: we_n de-assertion delay(t_wp).
> > +- arm,nand-cycle-t4	: Status read time(t_clr)
> > +- arm,nand-cycle-t5	: ID read time(t_ar)
> > +- arm,nand-cycle-t6	: busy to re_n(t_rr)
> 
> I think this has nothing to do in the DT, you should handle timings from the -
> >setup_data_interface() hook. If you need, you may use different compatibles to distinguish
> different platform data.
> 
This controller is applicable only to Zynq platform. No other platform will use this.
Basically pl353-smc.c and pl353-nand.c, both are different drivers.
And this data_interface hook is in nand, and to set this timings if we read it from setup_data_interface(), then
We need to make call from nand to smc driver.
Let me try this.

> > +
> > +for nand partition information please refer the below file
> 
> s/nand/NAND/
I will update in next version.

> 
> > +Documentation/devicetree/bindings/mtd/partition.txt
> > +
> > +Example:
> > +	pl353smcc_0: pl353smcc@e000e000 {
> 
> Why not something more explicit with the '-flash-controller' suffix?
Is this ok?
smcc: memory-controller@e000e000 {}

> 
> > +			compatible = "arm,pl353-smc-r2p1"
> > +			clock-names = "memclk", "aclk";
> > +			clocks = <&clkc 11>, <&clkc 44>;
> > +			reg = <0xe000e000 0x1000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +			nand_0: nand@e1000000 {
> > +				compatible = "arm,pl353-nand-r2p1"
> 
> NAND chips do not have their own compatible.
As I said above, SMCC controller has two interface(NAND, NOR/SRAM).
So to differentiate which interface is selected, we added the compatible.
The dts node looks below.
smcc: memory-controller@e000e000 {
			#address-cells = <1>;
			#size-cells = <1>;
			clock-names = "memclk", "aclk";
			clocks = <&clkc 11>, <&clkc 44>;
			compatible = "arm,pl353-smc-r2p1";
			interrupt-parent = <&intc>;
			interrupts = <0 18 4>;
			ranges ;
			reg = <0xe000e000 0x1000>;
			nand0: flash@e1000000 {
				compatible = "arm,pl353-nand-r2p1";
				reg = <0xe1000000 0x1000000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
			};
			nor0: flash@e2000000 {
				compatible = "cfi-flash";
				reg = <0xe2000000 0x2000000>;
				#address-cells = <1>;
				#size-cells = <1>;
			};
		};
> 
> > +				reg = <0xe1000000 0x1000000>;
> > +				arm,nand-cycle-t0 = <0x4>;
> > +				arm,nand-cycle-t1 = <0x4>;
> > +				arm,nand-cycle-t2 = <0x1>;
> > +				arm,nand-cycle-t3 = <0x2>;
> > +				arm,nand-cycle-t4 = <0x2>;
> > +				arm,nand-cycle-t5 = <0x2>;
> > +				arm,nand-cycle-t6 = <0x4>;
> > +				(...)
> > +			};
> > +	};
> 
> 
> Thanks,
> Miquèl

Thanks,
Naga Sureshkumar Relli.

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information
  2018-06-08  5:20     ` Naga Sureshkumar Relli
@ 2018-06-08  5:51       ` Boris Brezillon
  2018-06-08  8:01         ` Naga Sureshkumar Relli
  2018-06-08  7:23       ` Miquel Raynal
  1 sibling, 1 reply; 17+ messages in thread
From: Boris Brezillon @ 2018-06-08  5:51 UTC (permalink / raw)
  To: Naga Sureshkumar Relli
  Cc: Miquel Raynal, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

On Fri, 8 Jun 2018 05:20:33 +0000
Naga Sureshkumar Relli <nagasure@xilinx.com> wrote:

> Hi Miquel,
> 
> Thanks for the review.
> 
> > -----Original Message-----
> > From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> > Sent: Thursday, June 7, 2018 9:12 PM
> > To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> > Cc: boris.brezillon@bootlin.com; richard@nod.at; wmw2@infradead.org;
> > computersforpeace@gmail.com; marek.vasut@gmail.com; f.fainelli@gmail.com;
> > mmayer@broadcom.com; rogerq@ti.com; ladis@linux-mips.org; ada@thorsis.com;
> > honghui.zhang@mediatek.com; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> > nagasureshkumarrelli@gmail.com
> > Subject: Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree
> > binding information
> > 
> > Hi Naga,
> > 
> > On Wed, 6 Jun 2018 13:19:39 +0530, Naga Sureshkumar Relli
> > <naga.sureshkumar.relli@xilinx.com> wrote:
> >   
> > > Add pl353 static memory controller devicetree binding information.
> > >
> > > Signed-off-by: Naga Sureshkumar Relli
> > > <naga.sureshkumar.relli@xilinx.com>
> > > ---
> > > Changes in v9:
> > >  - Addressed commens given by Randy Dunlap and Miquel Raynal  
> > 
> > Can you please be more specific in your next changelog? I don't remember what I suggested a
> > few months ago :)  
> Ok, I will update.
> 
> >   
> > > Changes in v8:
> > >  - None
> > > Changes in v7:
> > > - Corrected clocks description
> > > - prefixed '#' for address and size cells Changes in v6:
> > >  - None
> > > Changes in v5:
> > >  - Removed timing properties
> > > Changes in v4:
> > >  - none
> > > Changes in v3:
> > >  - none
> > > Changes in v2:
> > >  - modified timing binding info as per onfi timing parameters
> > >  - add suffix nano second as timing unit
> > >  - modified the clock names as per the IP spec
> > > ---
> > >  .../bindings/memory-controllers/pl353-smc.txt      | 53  
> > ++++++++++++++++++++++  
> > >  1 file changed, 53 insertions(+)
> > >  create mode 100644
> > > Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > > b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > > new file mode 100644
> > > index 0000000..551e66b
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.t
> > > +++ xt
> > > @@ -0,0 +1,53 @@
> > > +Device tree bindings for ARM PL353 static memory controller
> > > +
> > > +PL353 static memory controller supports two kinds of memory
> > > +interfaces.i.e NAND and SRAM/NOR interfaces.
> > > +The actual devices are instantiated from the child nodes of pl353 smc node.
> > > +
> > > +Required properties:
> > > +- compatible		: Should be "arm,pl353-smc-r2p1"  
> > 
> > I thing Rob prefers:
> > 
> > - compatible: Must be one of:
> >   * arm, pl353-smc-r2p1  
> Are you suggesting any other compatibles?
> Or just a change from "should be to Must be one of"?
> >   
> > > +- reg			: Controller registers map and length.
> > > +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
> > > +			  (See clock bindings for details).
> > > +- clocks		: Clock phandles (see clock bindings for details).
> > > +- address-cells		: Address cells, must be 1.
> > > +- size-cells		: Size cells. Must be 1.  
> > 
> > Please avoid padding, just this is enough:
> > 
> > - something: And another thing.  
> Ok, I will update it.
> 
> >   
> > > +
> > > +Child nodes:
> > > + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash"
> > > +drivers are supported as child nodes.
> > > +
> > > +Mandatory timing properties for child nodes:
> > > +- arm,nand-cycle-t0	: Read cycle time(t_rc).
> > > +- arm,nand-cycle-t1	: Write cycle time(t_wc).
> > > +- arm,nand-cycle-t2	: re_n assertion delay(t_rea).
> > > +- arm,nand-cycle-t3	: we_n de-assertion delay(t_wp).
> > > +- arm,nand-cycle-t4	: Status read time(t_clr)
> > > +- arm,nand-cycle-t5	: ID read time(t_ar)
> > > +- arm,nand-cycle-t6	: busy to re_n(t_rr)  
> > 
> > I think this has nothing to do in the DT, you should handle timings from the -  
> > >setup_data_interface() hook. If you need, you may use different compatibles to distinguish  
> > different platform data.
> >   
> This controller is applicable only to Zynq platform. No other platform will use this.
> Basically pl353-smc.c and pl353-nand.c, both are different drivers.
> And this data_interface hook is in nand, and to set this timings if we read it from setup_data_interface(), then
> We need to make call from nand to smc driver.
> Let me try this.
> 
> > > +
> > > +for nand partition information please refer the below file  
> > 
> > s/nand/NAND/  
> I will update in next version.
> 
> >   
> > > +Documentation/devicetree/bindings/mtd/partition.txt
> > > +
> > > +Example:
> > > +	pl353smcc_0: pl353smcc@e000e000 {  
> > 
> > Why not something more explicit with the '-flash-controller' suffix?  
> Is this ok?
> smcc: memory-controller@e000e000 {}
> 
> >   
> > > +			compatible = "arm,pl353-smc-r2p1"
> > > +			clock-names = "memclk", "aclk";
> > > +			clocks = <&clkc 11>, <&clkc 44>;
> > > +			reg = <0xe000e000 0x1000>;
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			ranges;
> > > +			nand_0: nand@e1000000 {
> > > +				compatible = "arm,pl353-nand-r2p1"  
> > 
> > NAND chips do not have their own compatible.  
> As I said above, SMCC controller has two interface(NAND, NOR/SRAM).
> So to differentiate which interface is selected, we added the compatible.
> The dts node looks below.
> smcc: memory-controller@e000e000 {
> 			#address-cells = <1>;
> 			#size-cells = <1>;
> 			clock-names = "memclk", "aclk";
> 			clocks = <&clkc 11>, <&clkc 44>;
> 			compatible = "arm,pl353-smc-r2p1";
> 			interrupt-parent = <&intc>;
> 			interrupts = <0 18 4>;
> 			ranges ;
> 			reg = <0xe000e000 0x1000>;
> 			nand0: flash@e1000000 {
> 				compatible = "arm,pl353-nand-r2p1";
> 				reg = <0xe1000000 0x1000000>;
> 				#address-cells = <0x1>;
> 				#size-cells = <0x1>;
> 			};
> 			nor0: flash@e2000000 {
> 				compatible = "cfi-flash";
> 				reg = <0xe2000000 0x2000000>;
> 				#address-cells = <1>;
> 				#size-cells = <1>;
> 			};
> 		};

This looks similar to what we have on at91 SoC with one memory
controller and inside this memory controller a dedicated logic for NAND
devices. We used a representation where the NAND controller logic is
described as a subnode of the memory controller and then NAND chips are
defined under this subnode [1].

[1]https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/mtd/atmel-nand.txt#L84

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information
  2018-06-08  5:20     ` Naga Sureshkumar Relli
  2018-06-08  5:51       ` Boris Brezillon
@ 2018-06-08  7:23       ` Miquel Raynal
  1 sibling, 0 replies; 17+ messages in thread
From: Miquel Raynal @ 2018-06-08  7:23 UTC (permalink / raw)
  To: Naga Sureshkumar Relli
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Naga,

On Fri, 8 Jun 2018 05:20:33 +0000, Naga Sureshkumar Relli
<nagasure@xilinx.com> wrote:

> Hi Miquel,
> 
> Thanks for the review.
> 
> > -----Original Message-----
> > From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> > Sent: Thursday, June 7, 2018 9:12 PM
> > To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> > Cc: boris.brezillon@bootlin.com; richard@nod.at; wmw2@infradead.org;
> > computersforpeace@gmail.com; marek.vasut@gmail.com; f.fainelli@gmail.com;
> > mmayer@broadcom.com; rogerq@ti.com; ladis@linux-mips.org; ada@thorsis.com;
> > honghui.zhang@mediatek.com; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> > nagasureshkumarrelli@gmail.com
> > Subject: Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree
> > binding information
> > 
> > Hi Naga,
> > 
> > On Wed, 6 Jun 2018 13:19:39 +0530, Naga Sureshkumar Relli
> > <naga.sureshkumar.relli@xilinx.com> wrote:
> >   
> > > Add pl353 static memory controller devicetree binding information.
> > >
> > > Signed-off-by: Naga Sureshkumar Relli
> > > <naga.sureshkumar.relli@xilinx.com>
> > > ---
> > > Changes in v9:
> > >  - Addressed commens given by Randy Dunlap and Miquel Raynal  
> > 
> > Can you please be more specific in your next changelog? I don't remember what I suggested a
> > few months ago :)  
> Ok, I will update.
> 
> >   
> > > Changes in v8:
> > >  - None
> > > Changes in v7:
> > > - Corrected clocks description
> > > - prefixed '#' for address and size cells Changes in v6:
> > >  - None
> > > Changes in v5:
> > >  - Removed timing properties
> > > Changes in v4:
> > >  - none
> > > Changes in v3:
> > >  - none
> > > Changes in v2:
> > >  - modified timing binding info as per onfi timing parameters
> > >  - add suffix nano second as timing unit
> > >  - modified the clock names as per the IP spec
> > > ---
> > >  .../bindings/memory-controllers/pl353-smc.txt      | 53  
> > ++++++++++++++++++++++  
> > >  1 file changed, 53 insertions(+)
> > >  create mode 100644
> > > Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > > b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > > new file mode 100644
> > > index 0000000..551e66b
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.t
> > > +++ xt
> > > @@ -0,0 +1,53 @@
> > > +Device tree bindings for ARM PL353 static memory controller
> > > +
> > > +PL353 static memory controller supports two kinds of memory
> > > +interfaces.i.e NAND and SRAM/NOR interfaces.
> > > +The actual devices are instantiated from the child nodes of pl353 smc node.
> > > +
> > > +Required properties:
> > > +- compatible		: Should be "arm,pl353-smc-r2p1"  
> > 
> > I thing Rob prefers:
> > 
> > - compatible: Must be one of:
> >   * arm, pl353-smc-r2p1  
> Are you suggesting any other compatibles?
> Or just a change from "should be to Must be one of"?
> >   

Just the rewording + making it a list in case we need to add new
compatibles in the future.

Thanks,
Miquèl

^ permalink raw reply	[flat|nested] 17+ messages in thread

* RE: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information
  2018-06-08  5:51       ` Boris Brezillon
@ 2018-06-08  8:01         ` Naga Sureshkumar Relli
  0 siblings, 0 replies; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-08  8:01 UTC (permalink / raw)
  To: Boris Brezillon
  Cc: Miquel Raynal, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Boris,

Thanks for letting us know the similar stuff.
I will look into it and if any update is required, I will update as per that.

Thanks,
Naga Sureshkumar Relli

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Friday, June 8, 2018 11:22 AM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> Cc: Miquel Raynal <miquel.raynal@bootlin.com>; richard@nod.at; wmw2@infradead.org;
> computersforpeace@gmail.com; marek.vasut@gmail.com; f.fainelli@gmail.com;
> mmayer@broadcom.com; rogerq@ti.com; ladis@linux-mips.org; ada@thorsis.com;
> honghui.zhang@mediatek.com; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> nagasureshkumarrelli@gmail.com
> Subject: Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree
> binding information
> 
> On Fri, 8 Jun 2018 05:20:33 +0000
> Naga Sureshkumar Relli <nagasure@xilinx.com> wrote:
> 
> > Hi Miquel,
> >
> > Thanks for the review.
> >
> > > -----Original Message-----
> > > From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> > > Sent: Thursday, June 7, 2018 9:12 PM
> > > To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> > > Cc: boris.brezillon@bootlin.com; richard@nod.at; wmw2@infradead.org;
> > > computersforpeace@gmail.com; marek.vasut@gmail.com;
> > > f.fainelli@gmail.com; mmayer@broadcom.com; rogerq@ti.com;
> > > ladis@linux-mips.org; ada@thorsis.com; honghui.zhang@mediatek.com;
> > > linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> > > nagasureshkumarrelli@gmail.com
> > > Subject: Re: [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc
> > > controller devicetree binding information
> > >
> > > Hi Naga,
> > >
> > > On Wed, 6 Jun 2018 13:19:39 +0530, Naga Sureshkumar Relli
> > > <naga.sureshkumar.relli@xilinx.com> wrote:
> > >
> > > > Add pl353 static memory controller devicetree binding information.
> > > >
> > > > Signed-off-by: Naga Sureshkumar Relli
> > > > <naga.sureshkumar.relli@xilinx.com>
> > > > ---
> > > > Changes in v9:
> > > >  - Addressed commens given by Randy Dunlap and Miquel Raynal
> > >
> > > Can you please be more specific in your next changelog? I don't
> > > remember what I suggested a few months ago :)
> > Ok, I will update.
> >
> > >
> > > > Changes in v8:
> > > >  - None
> > > > Changes in v7:
> > > > - Corrected clocks description
> > > > - prefixed '#' for address and size cells Changes in v6:
> > > >  - None
> > > > Changes in v5:
> > > >  - Removed timing properties
> > > > Changes in v4:
> > > >  - none
> > > > Changes in v3:
> > > >  - none
> > > > Changes in v2:
> > > >  - modified timing binding info as per onfi timing parameters
> > > >  - add suffix nano second as timing unit
> > > >  - modified the clock names as per the IP spec
> > > > ---
> > > >  .../bindings/memory-controllers/pl353-smc.txt      | 53
> > > ++++++++++++++++++++++
> > > >  1 file changed, 53 insertions(+)
> > > >  create mode 100644
> > > > Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.t
> > > > xt
> > > > b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.t
> > > > xt
> > > > new file mode 100644
> > > > index 0000000..551e66b
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-s
> > > > +++ mc.t
> > > > +++ xt
> > > > @@ -0,0 +1,53 @@
> > > > +Device tree bindings for ARM PL353 static memory controller
> > > > +
> > > > +PL353 static memory controller supports two kinds of memory
> > > > +interfaces.i.e NAND and SRAM/NOR interfaces.
> > > > +The actual devices are instantiated from the child nodes of pl353 smc node.
> > > > +
> > > > +Required properties:
> > > > +- compatible		: Should be "arm,pl353-smc-r2p1"
> > >
> > > I thing Rob prefers:
> > >
> > > - compatible: Must be one of:
> > >   * arm, pl353-smc-r2p1
> > Are you suggesting any other compatibles?
> > Or just a change from "should be to Must be one of"?
> > >
> > > > +- reg			: Controller registers map and length.
> > > > +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
> > > > +			  (See clock bindings for details).
> > > > +- clocks		: Clock phandles (see clock bindings for details).
> > > > +- address-cells		: Address cells, must be 1.
> > > > +- size-cells		: Size cells. Must be 1.
> > >
> > > Please avoid padding, just this is enough:
> > >
> > > - something: And another thing.
> > Ok, I will update it.
> >
> > >
> > > > +
> > > > +Child nodes:
> > > > + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash"
> > > > +drivers are supported as child nodes.
> > > > +
> > > > +Mandatory timing properties for child nodes:
> > > > +- arm,nand-cycle-t0	: Read cycle time(t_rc).
> > > > +- arm,nand-cycle-t1	: Write cycle time(t_wc).
> > > > +- arm,nand-cycle-t2	: re_n assertion delay(t_rea).
> > > > +- arm,nand-cycle-t3	: we_n de-assertion delay(t_wp).
> > > > +- arm,nand-cycle-t4	: Status read time(t_clr)
> > > > +- arm,nand-cycle-t5	: ID read time(t_ar)
> > > > +- arm,nand-cycle-t6	: busy to re_n(t_rr)
> > >
> > > I think this has nothing to do in the DT, you should handle timings
> > > from the -
> > > >setup_data_interface() hook. If you need, you may use different
> > > >compatibles to distinguish
> > > different platform data.
> > >
> > This controller is applicable only to Zynq platform. No other platform will use this.
> > Basically pl353-smc.c and pl353-nand.c, both are different drivers.
> > And this data_interface hook is in nand, and to set this timings if we
> > read it from setup_data_interface(), then We need to make call from nand to smc driver.
> > Let me try this.
> >
> > > > +
> > > > +for nand partition information please refer the below file
> > >
> > > s/nand/NAND/
> > I will update in next version.
> >
> > >
> > > > +Documentation/devicetree/bindings/mtd/partition.txt
> > > > +
> > > > +Example:
> > > > +	pl353smcc_0: pl353smcc@e000e000 {
> > >
> > > Why not something more explicit with the '-flash-controller' suffix?
> > Is this ok?
> > smcc: memory-controller@e000e000 {}
> >
> > >
> > > > +			compatible = "arm,pl353-smc-r2p1"
> > > > +			clock-names = "memclk", "aclk";
> > > > +			clocks = <&clkc 11>, <&clkc 44>;
> > > > +			reg = <0xe000e000 0x1000>;
> > > > +			#address-cells = <1>;
> > > > +			#size-cells = <1>;
> > > > +			ranges;
> > > > +			nand_0: nand@e1000000 {
> > > > +				compatible = "arm,pl353-nand-r2p1"
> > >
> > > NAND chips do not have their own compatible.
> > As I said above, SMCC controller has two interface(NAND, NOR/SRAM).
> > So to differentiate which interface is selected, we added the compatible.
> > The dts node looks below.
> > smcc: memory-controller@e000e000 {
> > 			#address-cells = <1>;
> > 			#size-cells = <1>;
> > 			clock-names = "memclk", "aclk";
> > 			clocks = <&clkc 11>, <&clkc 44>;
> > 			compatible = "arm,pl353-smc-r2p1";
> > 			interrupt-parent = <&intc>;
> > 			interrupts = <0 18 4>;
> > 			ranges ;
> > 			reg = <0xe000e000 0x1000>;
> > 			nand0: flash@e1000000 {
> > 				compatible = "arm,pl353-nand-r2p1";
> > 				reg = <0xe1000000 0x1000000>;
> > 				#address-cells = <0x1>;
> > 				#size-cells = <0x1>;
> > 			};
> > 			nor0: flash@e2000000 {
> > 				compatible = "cfi-flash";
> > 				reg = <0xe2000000 0x2000000>;
> > 				#address-cells = <1>;
> > 				#size-cells = <1>;
> > 			};
> > 		};
> 
> This looks similar to what we have on at91 SoC with one memory controller and inside this
> memory controller a dedicated logic for NAND devices. We used a representation where the
> NAND controller logic is described as a subnode of the memory controller and then NAND
> chips are defined under this subnode [1].
> 
> [1]https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/mtd/
> atmel-nand.txt#L84

^ permalink raw reply	[flat|nested] 17+ messages in thread

* RE: [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface
  2018-06-07 19:59   ` Miquel Raynal
@ 2018-06-08 12:23     ` Naga Sureshkumar Relli
  2018-06-08 12:35       ` Miquel Raynal
  0 siblings, 1 reply; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-08 12:23 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Miquel,

> -----Original Message-----
> From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> Sent: Friday, June 8, 2018 1:30 AM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> Cc: boris.brezillon@bootlin.com; richard@nod.at; wmw2@infradead.org;
> computersforpeace@gmail.com; marek.vasut@gmail.com; f.fainelli@gmail.com;
> mmayer@broadcom.com; rogerq@ti.com; ladis@linux-mips.org; ada@thorsis.com;
> honghui.zhang@mediatek.com; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> nagasureshkumarrelli@gmail.com
> Subject: Re: [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353
> smc nand interface
> 
> Hi Naga,
> 
> This is a partial review, enough for this version, see below.
Ok, Thanks.

> 
> On Wed, 6 Jun 2018 13:19:42 +0530, Naga Sureshkumar Relli
> <naga.sureshkumar.relli@xilinx.com> wrote:
> 
> > Add driver for arm pl353 static memory controller nand interface with
> 
> s/nand/NAND/
Ok I will update.
> 
> > HW ECC support. This controller is used in xilinx zynq soc for
> > interfacing
> 
> s/HW/hardware/
Ok I will update.
> 
> > the nand flash memory.
> >
> > Signed-off-by: Naga Sureshkumar Relli
> > <naga.sureshkumar.relli@xilinx.com>
> > ---
> > Changes in v9:
> >  - Addressed the below comments given by Miquel
> >  - instead of using pl353_nand_write32, use directly writel_relaxed
> >  - Fixed check patch warnings
> >  - Renamed write_buf/read_buf to write_data_op/read_data_op
> >  - use BIT macro instead of 1 << nr
> >  - Use NAND_ROW_ADDR_3 flag
> >  - Use nand_wait_ready()
> >  - Removed swecc functions
> >  - Use address cycles as per size, instead of reading it from
> > Parameter page
> >  - Instead of writing too many patterns, use optional property Changes
> > in v8:
> >  - Added exec_op() implementation
> >  - Fixed the below v7 review comments
> >  - removed mtd_info from pl353_nand_info struct
> >  - Corrected ecc layout offsets
> >  - Added on-die ecc support
> > Changes in v7:
> >  - Currently not implemented the memclk rate adjustments. I will
> >    look into this later and once the basic driver is accepted.
> >  - Fixed GPL licence ident
> > Changes in v6:
> >  - Fixed the checkpatch.pl reported warnings
> >  - Using the address cycles information from the onfi param page
> >    earlier it is hardcoded to 5 in driver Changes in v5:
> >  - Configure the nand timing parameters as per the onfi spec Changes
> > in v4:
> >  - Updated the driver to sync with pl353_smc driver APIs Changes in
> > v3:
> >  - implemented the proper error codes
> >  - further breakdown this patch to multiple sets
> >  - added the controller and driver details to Documentation section
> >  - updated the licenece to GPLv2
> >  - reorganized the pl353_nand_ecc_init function Changes in v2:
> >  - use "depends on" rather than "select" option in kconfig
> >  - remove unused variable parts
> >  - remove dummy helper and use writel_relaxed directly
> > ---
> >
> >  drivers/mtd/nand/raw/Kconfig      |    7 +
> >  drivers/mtd/nand/raw/Makefile     |    3 +
> >  drivers/mtd/nand/raw/pl353_nand.c | 1236
> > +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 1246 insertions(+)
> >  create mode 100644 drivers/mtd/nand/raw/pl353_nand.c
> >
> > diff --git a/drivers/mtd/nand/raw/Kconfig
> > b/drivers/mtd/nand/raw/Kconfig index 6871ff0..1c5d528 100644
> > --- a/drivers/mtd/nand/raw/Kconfig
> > +++ b/drivers/mtd/nand/raw/Kconfig
> > @@ -530,4 +530,11 @@ config MTD_NAND_MTK
> >  	  Enables support for NAND controller on MTK SoCs.
> >  	  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
> >
> > +config MTD_NAND_PL353
> > +	tristate "ARM Pl353 NAND flash driver"
> > +	depends on MTD_NAND && ARM
> > +	depends on PL353_SMC
> > +	help
> > +	  Enables support for PrimeCell Static Memory Controller PL353.
> > +
> >  endif # MTD_NAND
> > diff --git a/drivers/mtd/nand/raw/Makefile
> > b/drivers/mtd/nand/raw/Makefile index 165b7ef..6855a0d 100644
> > --- a/drivers/mtd/nand/raw/Makefile
> > +++ b/drivers/mtd/nand/raw/Makefile
> > @@ -56,7 +56,9 @@ obj-$(CONFIG_MTD_NAND_HISI504)	        +=
> hisi504_nand.o
> >  obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
> >  obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
> >  obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
> > +obj-$(CONFIG_MTD_NAND_PL353)		+= pl353_nand.o
> >
> > +CFLAGS_{nand_base.o} := -DDEBUG
> 
> Nope :)
For some reason I put this, I will remove this in next version.
> 
> >  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
> > nand-objs += nand_amd.o  nand-objs += nand_hynix.o @@ -64,3 +66,4 @@
> > nand-objs += nand_macronix.o  nand-objs += nand_micron.o  nand-objs +=
> > nand_samsung.o  nand-objs += nand_toshiba.o
> > +
> 
> Extra space here
Ok I will update.
> 
> > diff --git a/drivers/mtd/nand/raw/pl353_nand.c
> > b/drivers/mtd/nand/raw/pl353_nand.c
> > new file mode 100644
> > index 0000000..a880eade
> > --- /dev/null
> > +++ b/drivers/mtd/nand/raw/pl353_nand.c
> > @@ -0,0 +1,1236 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * ARM PL353 NAND flash controller driver
> > + *
> > + * Copyright (C) 2017 Xilinx, Inc
> > + * Author: Punnaiah chowdary kalluri <punnaiah@xilinx.com>
> > + * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
> > + *
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/ioport.h>
> > +#include <linux/irq.h>
> > +#include <linux/module.h>
> > +#include <linux/moduleparam.h>
> > +#include <linux/mtd/mtd.h>
> > +#include <linux/mtd/rawnand.h>
> > +#include <linux/mtd/nand_ecc.h>
> > +#include <linux/mtd/partitions.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/platform_data/pl353-smc.h>
> > +
> > +#define PL353_NAND_DRIVER_NAME "pl353-nand"
> > +
> > +/* NAND flash driver defines */
> > +#define PL353_NAND_CMD_PHASE	1	/* End command valid in command
> phase */
> > +#define PL353_NAND_DATA_PHASE	2	/* End command valid in data phase
> */
> > +#define PL353_NAND_ECC_SIZE	512	/* Size of data for ECC operation */
> > +
> > +/* Flash memory controller operating parameters */
> > +
> > +#define PL353_NAND_ECC_CONFIG	(BIT(4)  |	/* ECC read at end of page */
> \
> > +				 (0 << 5))	/* No Jumping */
> > +
> > +/* AXI Address definitions */
> > +#define START_CMD_SHIFT		3
> > +#define END_CMD_SHIFT		11
> > +#define END_CMD_VALID_SHIFT	20
> > +#define ADDR_CYCLES_SHIFT	21
> > +#define CLEAR_CS_SHIFT		21
> > +#define ECC_LAST_SHIFT		10
> > +#define COMMAND_PHASE		(0 << 19)
> > +#define DATA_PHASE		BIT(19)
> > +
> > +#define PL353_NAND_ECC_LAST	BIT(ECC_LAST_SHIFT)	/* Set
> ECC_Last */
> > +#define PL353_NAND_CLEAR_CS	BIT(CLEAR_CS_SHIFT)	/* Clear chip
> select */
> > +
> > +#define ONDIE_ECC_FEATURE_ADDR	0x90
> > +#define PL353_NAND_ECC_BUSY_TIMEOUT	(1 * HZ)
> > +#define PL353_NAND_DEV_BUSY_TIMEOUT	(1 * HZ)
> > +#define PL353_NAND_LAST_TRANSFER_LENGTH	4
> > +
> > +struct pl353_nfc_op {
> > +	u32 cmnds[4];
> > +	u32 thirdrow;
> > +	u32 type;
> > +	u32 end_cmd;
> > +	u32 addrs;
> > +	bool wait;
> > +	u32 len;
> > +	u32 naddrs;
> > +	unsigned int data_instr_idx;
> > +	const struct nand_op_instr *data_instr;
> > +	unsigned int rdy_timeout_ms;
> > +	unsigned int rdy_delay_ns;
> > +	unsigned int data_delay_ns;
> > +	unsigned int cle_ale_delay_ns;
> > +	u32 addr5;
> > +	u32 addr6;
> > +};
> > +
> > +/**
> > + * struct pl353_nand_info - Defines the NAND flash driver instance
> > + * @chip:		NAND chip information structure
> > + * @nand_base:		Virtual address of the NAND flash device
> > + * @end_cmd_pending:	End command is pending
> > + * @end_cmd:		End command
> > + * @row_addr_cycles:	Row address cycles
> > + * @col_addr_cycles:	Column address cycles
> > + * @address:		Page address
> > + * @cmd_pending:	More command is needed
> > + */
> > +struct pl353_nand_info {
> > +	struct nand_chip chip;
> > +	void __iomem *nand_base;
> > +	unsigned long end_cmd_pending;
> > +	unsigned long end_cmd;
> > +	u8 addr_cycles;
> > +	u32 address;
> > +	u32 cmd_pending;
> > +	struct completion complete;
> > +};
> > +
> > +static int pl353_ecc_ooblayout16_ecc(struct mtd_info *mtd, int section,
> > +				     struct mtd_oob_region *oobregion) {
> > +	struct nand_chip *chip = mtd_to_nand(mtd);
> > +
> > +	if (section >= chip->ecc.steps)
> > +		return -ERANGE;
> > +
> > +	oobregion->offset = (section * chip->ecc.bytes);
> > +	oobregion->length = chip->ecc.bytes;
> > +
> > +	return 0;
> > +}
> > +
> > +static int pl353_ecc_ooblayout16_free(struct mtd_info *mtd, int section,
> > +				      struct mtd_oob_region *oobregion) {
> > +	struct nand_chip *chip = mtd_to_nand(mtd);
> > +
> > +	if (section >= chip->ecc.steps)
> > +		return -ERANGE;
> > +
> > +	oobregion->offset = (section * chip->ecc.bytes) + 8;
> > +	oobregion->length = 8;
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct mtd_ooblayout_ops pl353_ecc_ooblayout16_ops = {
> > +	.ecc = pl353_ecc_ooblayout16_ecc,
> > +	.free = pl353_ecc_ooblayout16_free,
> > +};
> > +
> > +static int pl353_ecc_ooblayout64_ecc(struct mtd_info *mtd, int section,
> > +				     struct mtd_oob_region *oobregion) {
> > +	struct nand_chip *chip = mtd_to_nand(mtd);
> > +
> > +	if (section >= chip->ecc.steps)
> > +		return -ERANGE;
> > +
> > +	oobregion->offset = (section * chip->ecc.bytes) + 52;
> > +	oobregion->length = chip->ecc.bytes;
> > +
> > +	return 0;
> > +}
> > +
> > +static int pl353_ecc_ooblayout64_free(struct mtd_info *mtd, int section,
> > +				      struct mtd_oob_region *oobregion) {
> > +	struct nand_chip *chip = mtd_to_nand(mtd);
> > +
> > +	if (section)
> > +		return -ERANGE;
> > +
> > +	if (section >= chip->ecc.steps)
> > +		return -ERANGE;
> > +
> > +	oobregion->offset = (section * chip->ecc.bytes) + 2;
> > +	oobregion->length = 50;
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct mtd_ooblayout_ops pl353_ecc_ooblayout64_ops = {
> > +	.ecc = pl353_ecc_ooblayout64_ecc,
> > +	.free = pl353_ecc_ooblayout64_free,
> > +};
> > +
> > +/* Generic flash bbt decriptors */
> > +static u8 bbt_pattern[] = { 'B', 'b', 't', '0' }; static u8
> > +mirror_pattern[] = { '1', 't', 'b', 'B' };
> > +
> > +static struct nand_bbt_descr bbt_main_descr = {
> > +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
> NAND_BBT_WRITE
> > +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> > +	.offs = 4,
> > +	.len = 4,
> > +	.veroffs = 20,
> > +	.maxblocks = 4,
> > +	.pattern = bbt_pattern
> > +};
> > +
> > +static struct nand_bbt_descr bbt_mirror_descr = {
> > +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
> NAND_BBT_WRITE
> > +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> > +	.offs = 4,
> > +	.len = 4,
> > +	.veroffs = 20,
> > +	.maxblocks = 4,
> > +	.pattern = mirror_pattern
> > +};
> > +
> > +/**
> > + * pl353_nand_read_data_op - read chip data into buffer
> > + * @chip:	Pointer to the NAND chip info structure
> > + * @in:		Pointer to the buffer to store read data
> > + * @len:	Number of bytes to read
> > + * Return:	Always return zero
> > + */
> > +static int pl353_nand_read_data_op(struct nand_chip *chip,
> > +				   u8 *in,
> > +				   unsigned int len)
> > +{
> > +	int i;
> > +
> > +	if (IS_ALIGNED((uint32_t)in, sizeof(uint32_t)) &&
> > +	    IS_ALIGNED(len, sizeof(uint32_t))) {
> > +		u32 *ptr = (u32 *)in;
> > +
> > +		len /= 4;
> > +		for (i = 0; i < len; i++)
> > +			ptr[i] = readl(chip->IO_ADDR_R);
> > +	} else {
> > +		for (i = 0; i < len; i++)
> > +			in[i] = readb(chip->IO_ADDR_R);
> 
> I'm not sure you need these IO_ADDR_R/W. Better not to use them in a new driver.
I am just continuing it from older driver. I will remove this in new driver
> 
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_write_buf - write buffer to chip
> > + * @mtd:	Pointer to the mtd info structure
> > + * @buf:	Pointer to the buffer to store write data
> > + * @len:	Number of bytes to write
> > + */
> > +static void pl353_nand_write_data_op(struct mtd_info *mtd, const u8 *buf,
> > +				     int len)
> > +{
> > +	int i;
> > +	struct nand_chip *chip = mtd_to_nand(mtd);
> > +
> > +	if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
> > +	    IS_ALIGNED(len, sizeof(uint32_t))) {
> > +		u32 *ptr = (u32 *)buf;
> > +
> > +		len /= 4;
> > +		for (i = 0; i < len; i++)
> > +			writel(ptr[i], chip->IO_ADDR_W);
> > +	} else {
> > +		for (i = 0; i < len; i++)
> > +			writeb(buf[i], chip->IO_ADDR_W);
> > +	}
> > +}
> > +
> > +/**
> > + * pl353_nand_calculate_hwecc - Calculate Hardware ECC
> > + * @mtd:	Pointer to the mtd_info structure
> > + * @data:	Pointer to the page data
> > + * @ecc:	Pointer to the ECC buffer where ECC data needs to be stored
> > + *
> > + * This function retrieves the Hardware ECC data from the controller
> > +and returns
> > + * ECC data back to the MTD subsystem.
> > + *
> > + * Return:	0 on success or error value on failure
> > + */
> > +static int pl353_nand_calculate_hwecc(struct mtd_info *mtd,
> > +				      const u8 *data, u8 *ecc)
> > +{
> > +	u32 ecc_value, ecc_status;
> > +	u8 ecc_reg, ecc_byte;
> > +	unsigned long timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
> > +	/* Wait till the ECC operation is complete or timeout */
> > +	do {
> > +		if (pl353_smc_ecc_is_busy())
> > +			cpu_relax();
> > +		else
> > +			break;
> > +	} while (!time_after_eq(jiffies, timeout));
> > +
> > +	if (time_after_eq(jiffies, timeout)) {
> > +		pr_err("%s timed out\n", __func__);
> > +		return -ETIMEDOUT;
> > +	}
> > +
> > +	for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
> 
> So here you hardcode the fact that there are 5 'blocks'. This is NAND chip dependent, right?
Yes. Not 5 but 4.

> 
> > +		/* Read ECC value for each block */
> > +		ecc_value = pl353_smc_get_ecc_val(ecc_reg);
> > +		ecc_status = (ecc_value >> 24) & 0xFF;
> 
> Please define all these values.
Ok I will update.
> 
> Make ecc_status a byte if you always need it to be 8-bit. Then you can drop the & 0xFF.
Ok I will update.
> 
> > +		/* ECC value valid */
> > +		if (ecc_status & 0x40) {
> 
> Please define this 0x40
Ok I will update.
> 
> > +			for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
> > +				/* Copy ECC bytes to MTD buffer */
> > +				*ecc = ~ecc_value & 0xFF;
> 
> This is not a copy, you invert the bytes, I don't really know why.
> Perhaps a comment would be appreciated.

When programming NAND, the SMC controller adds an inversion of 
the ECC code if the number of ones is odd.
To match the hardware behavior, software should add an inversion of the ECC code.
I will add this in a comment.

> > +				ecc_value = ecc_value >> 8;
> > +				ecc++;
> > +			}
> > +		} else {
> > +			pr_warn("%s status failed\n", __func__);
> > +			return -1;
> > +		}
> > +	}
> > +	return 0;
> > +}
> > +
> > +/**
> > + * onehot - onehot function
> > + * @value:	Value to check for onehot
> > + *
> > + * This function checks whether a value is onehot or not.
> > + * onehot is if and only if onebit is set.
> > + *
> > + * Return:	1 if it is onehot else 0
> > + */
> > +static int onehot(unsigned short value)
> 
> Why not returning a boolean?
Yes. I will update it.

> > +{
> > +	return (value & (value - 1)) == 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_correct_data - ECC correction function
> > + * @mtd:	Pointer to the mtd_info structure
> > + * @buf:	Pointer to the page data
> > + * @read_ecc:	Pointer to the ECC value read from spare data area
> > + * @calc_ecc:	Pointer to the calculated ECC value
> > + *
> > + * This function corrects the ECC single bit errors & detects 2-bit errors.
> > + *
> > + * Return:	0 if no ECC errors found
> > + *		1 if single bit error found and corrected.
> > + *		-1 if multiple ECC errors found.
> 
> "multiple uncorrectable ECC errors"
Ok, I will update

> 
> > + */
> > +static int pl353_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
> > +				   unsigned char *read_ecc,
> > +				   unsigned char *calc_ecc)
> > +{
> > +	unsigned char bit_addr;
> > +	unsigned int byte_addr;
> > +	unsigned short ecc_odd, ecc_even, read_ecc_lower, read_ecc_upper;
> > +	unsigned short calc_ecc_lower, calc_ecc_upper;
> > +
> > +	read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
> > +	read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
> > +
> > +	calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
> > +	calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
> > +
> > +	ecc_odd = read_ecc_lower ^ calc_ecc_lower;
> > +	ecc_even = read_ecc_upper ^ calc_ecc_upper;
> > +
> > +	/* no error */
> > +	if (ecc_odd == 0 && ecc_even == 0)
> 
> you can use "!ecc_odd && !ecc_even"
Ok I will update.

> 
> > +		return 0;
> > +
> > +	if (ecc_odd == (~ecc_even & 0xfff)) {
> > +		/* bits [11:3] of error code is byte offset */
> > +		byte_addr = (ecc_odd >> 3) & 0x1ff;
> > +		/* bits [2:0] of error code is bit offset */
> > +		bit_addr = ecc_odd & 0x7;
> > +		/* Toggling error bit */
> > +		buf[byte_addr] ^= (BIT(bit_addr));
> > +		return 1;
> > +	}
> > +	/* one error in parity */
> > +	if (onehot(ecc_odd | ecc_even) == 1)
> > +		return 1;
> > +
> > +	/* Uncorrectable error */
> > +	return -1;
> > +}
> > +
> > +static int pl353_dev_timeout(struct mtd_info *mtd, struct nand_chip
> > +*chip) {
> > +	unsigned long timeout = jiffies + PL353_NAND_DEV_BUSY_TIMEOUT;
> > +
> > +	do {
> > +		if (chip->dev_ready(mtd))
> > +			break;
> > +		cpu_relax();
> > +	} while (!time_after_eq(jiffies, timeout));
> > +
> > +	if (time_after_eq(jiffies, timeout)) {
> > +		pr_err("%s timed out\n", __func__);
> > +		return -1;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static void pl353_prepare_cmd(struct mtd_info *mtd, struct nand_chip *chip,
> > +			      int page, int column, int start_cmd, int end_cmd,
> > +			      bool read)
> > +{
> > +	unsigned long data_phase_addr;
> > +	u32 end_cmd_valid = 0;
> > +	void __iomem *cmd_addr;
> > +	unsigned long cmd_phase_addr = 0, cmd_data = 0;
> > +
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +
> > +	end_cmd_valid = read ? 1 : 0;
> > +
> > +	cmd_phase_addr = (unsigned long __force)xnand->nand_base +
> > +			 ((xnand->addr_cycles
> > +			 << ADDR_CYCLES_SHIFT) |
> > +			 (end_cmd_valid << END_CMD_VALID_SHIFT) |
> > +			 (COMMAND_PHASE) |
> > +			 (end_cmd << END_CMD_SHIFT) |
> > +			 (start_cmd << START_CMD_SHIFT));
> > +	cmd_addr = (void __iomem * __force)cmd_phase_addr;
> > +
> > +	/* Get the data phase address */
> > +	data_phase_addr = (unsigned long __force)xnand->nand_base +
> > +			  ((0x0 << CLEAR_CS_SHIFT) |
> > +			  (0 << END_CMD_VALID_SHIFT) |
> > +			  (DATA_PHASE) |
> > +			  (end_cmd << END_CMD_SHIFT) |
> > +			  (0x0 << ECC_LAST_SHIFT));
> > +
> > +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> > +	chip->IO_ADDR_W = chip->IO_ADDR_R;
> > +	if (chip->options & NAND_BUSWIDTH_16)
> > +		column /= 2;
> > +	cmd_data = column;
> > +	if (mtd->writesize > PL353_NAND_ECC_SIZE) {
> > +		cmd_data |= page << 16;
> > +		/* Another address cycle for devices > 128MiB */
> > +		if (chip->options & NAND_ROW_ADDR_3) {
> > +			writel_relaxed(cmd_data, cmd_addr);
> > +			cmd_data = (page >> 16);
> > +		}
> > +	} else {
> > +		cmd_data |= page << 8;
> > +	}
> > +
> > +	writel_relaxed(cmd_data, cmd_addr);
> > +}
> > +
> > +/**
> > + * pl353_nand_read_oob - [REPLACEABLE] the most common OOB data read function
> > + * @mtd:	Pointer to the mtd info structure
> > + * @chip:	Pointer to the NAND chip info structure
> > + * @page:	Page number to read
> > + *
> > + * Return:	Always return zero
> > + */
> > +static int pl353_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
> > +			       int page)
> > +{
> > +	unsigned long data_phase_addr;
> > +	u8 *p;
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> > +
> > +	chip->pagebuf = -1;
> > +	if (mtd->writesize < PL353_NAND_ECC_SIZE)
> > +		return 0;
> > +
> > +	pl353_prepare_cmd(mtd, chip, page, mtd->writesize, NAND_CMD_READ0,
> > +			  NAND_CMD_READSTART, 1);
> > +
> > +	ndelay(100);
> > +	pl353_dev_timeout(mtd, chip);
> > +
> > +	p = chip->oob_poi;
> > +	pl353_nand_read_data_op(chip, p,
> > +				(mtd->oobsize -
> > +				PL353_NAND_LAST_TRANSFER_LENGTH));
> > +	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> > +	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_write_oob - [REPLACEABLE] the most common OOB data write
> function
> > + * @mtd:	Pointer to the mtd info structure
> > + * @chip:	Pointer to the NAND chip info structure
> > + * @page:	Page number to write
> > + *
> > + * Return:	Zero on success and EIO on failure
> > + */
> > +static int pl353_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> > +				int page)
> > +{
> > +	const u8 *buf = chip->oob_poi;
> > +	unsigned long data_phase_addr;
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> > +	u32 addrcycles = 0;
> > +
> > +	chip->pagebuf = -1;
> > +	addrcycles = xnand->addr_cycles;
> > +	pl353_prepare_cmd(mtd, chip, page, mtd->writesize, NAND_CMD_SEQIN,
> > +			  NAND_CMD_PAGEPROG, 0);
> > +	ndelay(100);
> > +	pl353_nand_write_data_op(mtd, buf,
> > +				 (mtd->oobsize -
> > +				 PL353_NAND_LAST_TRANSFER_LENGTH));
> > +	buf += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> > +	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
> > +	data_phase_addr += nand_offset;
> 
> What you do here is unclear and suspect...
> 
> > +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> > +	pl353_nand_write_data_op(mtd, buf,
> PL353_NAND_LAST_TRANSFER_LENGTH);
> > +	nand_wait_ready(mtd);
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_read_page_raw - [Intern] read raw page data without ecc
> > + * @mtd:		Pointer to the mtd info structure
> > + * @chip:		Pointer to the NAND chip info structure
> > + * @buf:		Pointer to the data buffer
> > + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> > + * @page:		Page number to read
> > + *
> > + * Return:	Always return zero
> > + */
> > +static int pl353_nand_read_page_raw(struct mtd_info *mtd,
> > +				    struct nand_chip *chip,
> > +				    u8 *buf, int oob_required, int page) {
> > +	unsigned long data_phase_addr;
> > +	u8 *p;
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> > +
> > +	pl353_nand_read_data_op(chip, buf, mtd->writesize);
> > +	p = chip->oob_poi;
> > +	pl353_nand_read_data_op(chip, p,
> > +				(mtd->oobsize -
> > +				PL353_NAND_LAST_TRANSFER_LENGTH));
> > +	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> > +
> > +	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_write_page_raw - [Intern] raw page write function
> > + * @mtd:		Pointer to the mtd info structure
> > + * @chip:		Pointer to the NAND chip info structure
> > + * @buf:		Pointer to the data buffer
> > + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> > + * @page:		Page number to write
> > + *
> > + * Return:	Always return zero
> > + */
> > +static int pl353_nand_write_page_raw(struct mtd_info *mtd,
> > +				     struct nand_chip *chip,
> > +				     const u8 *buf, int oob_required,
> > +				     int page)
> > +{
> > +	unsigned long data_phase_addr;
> > +	u8 *p;
> > +
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> > +
> > +	pl353_nand_write_data_op(mtd, buf, mtd->writesize);
> > +	p = chip->oob_poi;
> > +	pl353_nand_write_data_op(mtd, p,
> > +				 (mtd->oobsize -
> > +				 PL353_NAND_LAST_TRANSFER_LENGTH));
> > +	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> > +	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> > +
> > +	pl353_nand_write_data_op(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> > +	ndelay(100);
> > +	nand_wait_ready(mtd);
> > +	return 0;
> > +}
> > +
> > +/**
> > + * nand_write_page_hwecc - Hardware ECC based page write function
> > + * @mtd:		Pointer to the mtd info structure
> > + * @chip:		Pointer to the NAND chip info structure
> > + * @buf:		Pointer to the data buffer
> > + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> > + * @page:		Page number to write
> > + *
> > + * This functions writes data and hardware generated ECC values in to the page.
> > + *
> > + * Return:	Always return zero
> > + */
> > +static int pl353_nand_write_page_hwecc(struct mtd_info *mtd,
> > +				       struct nand_chip *chip,
> > +				       const u8 *buf, int oob_required,
> > +				       int page)
> > +{
> > +	int eccsize = chip->ecc.size;
> > +	int eccsteps = chip->ecc.steps;
> > +	u8 *ecc_calc = chip->ecc.calc_buf;
> > +	u8 *oob_ptr;
> > +	const u8 *p = buf;
> > +	u32 ret;
> > +	unsigned long data_phase_addr;
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> > +
> > +	pl353_prepare_cmd(mtd, chip, page, 0, NAND_CMD_SEQIN,
> > +			  NAND_CMD_PAGEPROG, 0);
> > +	ndelay(100);
> > +	for ( ; (eccsteps - 1); eccsteps--) {
> > +		pl353_nand_write_data_op(mtd, p, eccsize);
> > +		p += eccsize;
> > +	}
> > +	pl353_nand_write_data_op(mtd, p,
> > +				 (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
> > +	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	/* Set ECC Last bit to 1 */
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_ECC_LAST;
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> > +	pl353_nand_write_data_op(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	p = buf;
> > +	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
> > +
> > +	/* Wait for ECC to be calculated and read the error values */
> > +	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi,
> > +					 0, chip->ecc.total);
> > +	if (ret)
> > +		return ret;
> 
> Space
Will correct it.

> 
> > +	/* Clear ECC last bit */
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr &= ~PL353_NAND_ECC_LAST;
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> > +
> > +	/* Write the spare area with ECC bytes */
> > +	oob_ptr = chip->oob_poi;
> > +	pl353_nand_write_data_op(mtd, oob_ptr,
> > +				 (mtd->oobsize -
> > +				 PL353_NAND_LAST_TRANSFER_LENGTH));
> > +
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> > +	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
> > +	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +	pl353_nand_write_data_op(mtd, oob_ptr,
> > +PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	/*
> > +	 * Apply this short delay always to ensure that we do wait tWB in any
> > +	 * case on any machine.
> > +	 */
> > +	ndelay(100);
> > +	nand_wait_ready(mtd);
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_read_page_hwecc - Hardware ECC based page read function
> > + * @mtd:		Pointer to the mtd info structure
> > + * @chip:		Pointer to the NAND chip info structure
> > + * @buf:		Pointer to the buffer to store read data
> > + * @oob_required:	Caller requires OOB data read to chip->oob_poi
> > + * @page:		Page number to read
> > + *
> > + * This functions reads data and checks the data integrity by
> > +comparing hardware
> > + * generated ECC values and read ECC values from spare area.
> > + *
> > + * Return:	0 always and updates ECC operation status in to MTD structure
> > + */
> > +static int pl353_nand_read_page_hwecc(struct mtd_info *mtd,
> > +				      struct nand_chip *chip,
> > +				      u8 *buf, int oob_required, int page) {
> > +	int i, stat, eccsize = chip->ecc.size;
> > +	int eccbytes = chip->ecc.bytes;
> > +	int eccsteps = chip->ecc.steps;
> > +	u8 *p = buf;
> > +	u8 *ecc_calc = chip->ecc.calc_buf;
> > +	u8 *ecc = chip->ecc.code_buf;
> > +	unsigned int max_bitflips = 0;
> > +	u8 *oob_ptr;
> > +	u32 ret;
> > +	unsigned long data_phase_addr;
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +	unsigned long nand_offset = (unsigned long __force)xnand->nand_base;
> > +
> > +	pl353_prepare_cmd(mtd, chip, page, 0, NAND_CMD_READ0,
> > +			  NAND_CMD_READSTART, 1);
> > +	ndelay(100);
> > +	pl353_dev_timeout(mtd, chip);
> > +
> > +	for ( ; (eccsteps - 1); eccsteps--) {
> > +		pl353_nand_read_data_op(chip, p, eccsize);
> > +		p += eccsize;
> > +	}
> > +	pl353_nand_read_data_op(chip, p,
> > +				(eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
> > +	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	/* Set ECC Last bit to 1 */
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_ECC_LAST;
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> > +	pl353_nand_read_data_op(chip, p, PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	/* Read the calculated ECC value */
> > +	p = buf;
> > +	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
> > +
> > +	/* Clear ECC last bit */
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr &= ~PL353_NAND_ECC_LAST;
> > +	data_phase_addr += nand_offset;
> > +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> > +
> > +	/* Read the stored ECC value */
> > +	oob_ptr = chip->oob_poi;
> > +	pl353_nand_read_data_op(chip, oob_ptr,
> > +				(mtd->oobsize -
> > +				PL353_NAND_LAST_TRANSFER_LENGTH));
> > +
> > +	/* de-assert chip select */
> > +	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
> > +	data_phase_addr -= nand_offset;
> > +	data_phase_addr |= PL353_NAND_CLEAR_CS;
> > +	data_phase_addr += nand_offset;
> 
> Ok, now I am convinced this is not the right way. Please forget about
> chip->IO_ADDR_*.
Ok. I will update it.
> 
> > +	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> > +
> > +	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
> > +	pl353_nand_read_data_op(chip, oob_ptr,
> > +PL353_NAND_LAST_TRANSFER_LENGTH);
> > +
> > +	ret = mtd_ooblayout_get_eccbytes(mtd, ecc, chip->oob_poi, 0,
> > +					 chip->ecc.total);
> > +	if (ret)
> > +		return ret;
> > +
> > +	eccsteps = chip->ecc.steps;
> > +	p = buf;
> > +
> > +	/* Check ECC error for all blocks and correct if it is correctable */
> > +	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
> > +		stat = chip->ecc.correct(mtd, p, &ecc[i], &ecc_calc[i]);
> > +		if (stat < 0) {
> > +			mtd->ecc_stats.failed++;
> > +		} else {
> > +			mtd->ecc_stats.corrected += stat;
> > +			max_bitflips = max_t(unsigned int, max_bitflips, stat);
> > +		}
> > +	}
> > +
> > +	return max_bitflips;
> > +}
> > +
> > +/**
> > + * pl353_nand_select_chip - Select the flash device
> > + * @mtd:	Pointer to the mtd info structure
> > + * @chip:	Pointer to the NAND chip info structure
> > + *
> > + * This function is empty as the NAND controller handles chip select
> > +line
> > + * internally based on the chip address passed in command and data phase.
> > + */
> > +static void pl353_nand_select_chip(struct mtd_info *mtd, int chip) {
> > +}
> > +
> > +/* NAND framework ->exec_op() hooks and related helpers */ static
> > +void pl353_nfc_parse_instructions(struct nand_chip *chip,
> > +					 const struct nand_subop *subop,
> > +					 struct pl353_nfc_op *nfc_op)
> > +{
> > +	const struct nand_op_instr *instr = NULL;
> > +	unsigned int op_id, offset, naddrs;
> > +	int i, len;
> > +	const u8 *addrs;
> > +
> > +	memset(nfc_op, 0, sizeof(struct pl353_nfc_op));
> > +	for (op_id = 0; op_id < subop->ninstrs; op_id++) {
> > +		nfc_op->len = nand_subop_get_data_len(subop, op_id);
> > +		len = nand_subop_get_data_len(subop, op_id);
> > +		instr = &subop->instrs[op_id];
> > +		if (subop->ninstrs == 1)
> > +			nfc_op->cmnds[0] = -1;
> > +		switch (instr->type) {
> > +		case NAND_OP_CMD_INSTR:
> > +			nfc_op->type = NAND_OP_CMD_INSTR;
> > +			if (op_id)
> > +				nfc_op->cmnds[1] = instr->ctx.cmd.opcode;
> > +			else
> > +				nfc_op->cmnds[0] = instr->ctx.cmd.opcode;
> > +			nfc_op->cle_ale_delay_ns = instr->delay_ns;
> > +			break;
> > +
> > +		case NAND_OP_ADDR_INSTR:
> > +			offset = nand_subop_get_addr_start_off(subop, op_id);
> > +			naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
> > +			addrs = &instr->ctx.addr.addrs[offset];
> > +			nfc_op->addrs = instr->ctx.addr.addrs[offset];
> > +			for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) {
> > +				nfc_op->addrs |= instr->ctx.addr.addrs[i] <<
> > +						 (8 * i);
> > +			}
> > +
> > +			if (naddrs >= 5)
> > +				nfc_op->addr5 = addrs[4];
> > +			if (naddrs >= 6)
> > +				nfc_op->addr6 = addrs[5];
> > +			nfc_op->naddrs = nand_subop_get_num_addr_cyc(subop,
> > +								     op_id);
> > +			nfc_op->cle_ale_delay_ns = instr->delay_ns;
> > +			break;
> > +
> > +		case NAND_OP_DATA_IN_INSTR:
> > +			nfc_op->data_instr = instr;
> > +			nfc_op->type = NAND_OP_DATA_IN_INSTR;
> > +			nfc_op->data_instr_idx = op_id;
> > +			nfc_op->data_delay_ns = instr->delay_ns;
> > +			break;
> > +
> > +		case NAND_OP_DATA_OUT_INSTR:
> > +			nfc_op->data_instr = instr;
> > +			nfc_op->type = NAND_OP_DATA_IN_INSTR;
> > +			nfc_op->data_instr_idx = op_id;
> > +			nfc_op->data_delay_ns = instr->delay_ns;
> > +			break;
> > +
> > +		case NAND_OP_WAITRDY_INSTR:
> > +			nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
> > +			nfc_op->rdy_delay_ns = instr->delay_ns;
> > +			nfc_op->wait = true;
> > +			break;
> > +		}
> > +	}
> > +}
> > +
> > +static void cond_delay(unsigned int ns) {
> > +	if (!ns)
> > +		return;
> > +
> > +	if (ns < 10000)
> > +		ndelay(ns);
> > +	else
> > +		udelay(DIV_ROUND_UP(ns, 1000));
> > +}
> > +
> > +/**
> > + * pl353_nand_cmd_function - Send command to NAND device
> > + * @chip:	Pointer to the NAND chip info structure
> > + * @subop:	Pointer to array of instructions
> > + * Return:	Always return zero
> > + */
> > +static int pl353_nand_cmd_function(struct nand_chip *chip,
> > +				   const struct nand_subop *subop) {
> > +	struct mtd_info *mtd = nand_to_mtd(chip);
> > +	const struct nand_op_instr *instr;
> > +	struct pl353_nfc_op nfc_op = {};
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +	void __iomem *cmd_addr;
> > +	unsigned long cmd_data = 0, end_cmd_valid = 0;
> > +	unsigned long cmd_phase_addr, data_phase_addr, end_cmd;
> > +	unsigned int op_id, len, offset;
> > +	bool reading;
> > +
> > +	pl353_nfc_parse_instructions(chip, subop, &nfc_op);
> > +	instr = nfc_op.data_instr;
> > +	op_id = nfc_op.data_instr_idx;
> > +	len = nand_subop_get_data_len(subop, op_id);
> > +	offset = nand_subop_get_data_start_off(subop, op_id);
> > +
> > +	if (nfc_op.cmnds[0] != -1) {
> > +		pl353_smc_clr_nand_int();
> > +		/* Get the command phase address */
> > +		if (nfc_op.cmnds[1] != 0) {
> > +			if (nfc_op.cmnds[0] == NAND_CMD_SEQIN)
> > +				end_cmd_valid = 0;
> > +			else
> > +				end_cmd_valid = 1;
> > +			end_cmd = nfc_op.cmnds[1];
> > +		}  else {
> > +			end_cmd = 0x0;
> > +		}
> > +		cmd_phase_addr = (unsigned long __force)xnand->nand_base +
> > +				 ((nfc_op.naddrs << ADDR_CYCLES_SHIFT) |
> > +				 (end_cmd_valid << END_CMD_VALID_SHIFT) |
> > +				 (COMMAND_PHASE) |
> > +				 (end_cmd << END_CMD_SHIFT) |
> > +				 (nfc_op.cmnds[0] << START_CMD_SHIFT));
> > +
> > +		cmd_addr = (void __iomem * __force)cmd_phase_addr;
> > +		/* Get the data phase address */
> > +		end_cmd_valid = 0;
> > +
> > +		data_phase_addr = (unsigned long __force)xnand->nand_base +
> > +				  ((0x0 << CLEAR_CS_SHIFT) |
> > +				  (end_cmd_valid << END_CMD_VALID_SHIFT) |
> > +				  (DATA_PHASE) |
> > +				  (end_cmd << END_CMD_SHIFT) |
> > +				  (0x0 << ECC_LAST_SHIFT));
> > +		chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
> > +		chip->IO_ADDR_W = chip->IO_ADDR_R;
> > +		/* Command phase AXI Read & Write */
> > +		if (nfc_op.naddrs >= 5) {
> > +			if (mtd->writesize > PL353_NAND_ECC_SIZE) {
> > +				cmd_data = nfc_op.addrs;
> > +				/* Another address cycle for devices > 128MiB */
> > +				if (chip->options & NAND_ROW_ADDR_3) {
> > +					writel_relaxed(cmd_data, cmd_addr);
> > +					cmd_data = nfc_op.addr5;
> > +					if (nfc_op.naddrs >= 6)
> > +						cmd_data |= (nfc_op.addr6 << 8);
> > +				}
> > +			}
> > +		}  else {
> > +			if (nfc_op.addrs != -1) {
> > +				int column = nfc_op.addrs;
> > +				/*
> > +				 * Change read/write column, read id etc
> > +				 * Adjust columns for 16 bit bus width
> > +				 */
> > +				if ((chip->options & NAND_BUSWIDTH_16) &&
> > +				    (nfc_op.cmnds[0] == NAND_CMD_READ0 ||
> > +					nfc_op.cmnds[0] == NAND_CMD_SEQIN ||
> > +					nfc_op.cmnds[0] == NAND_CMD_RNDOUT ||
> > +					nfc_op.cmnds[0] == NAND_CMD_RNDIN)) {
> > +					column >>= 1;
> > +				}
> > +				cmd_data = column;
> > +			}
> > +		}
> > +		writel_relaxed(cmd_data, cmd_addr);
> > +	ndelay(100);
> > +	}
> > +
> > +	cond_delay(nfc_op.cle_ale_delay_ns);
> > +	if (!nfc_op.data_instr)
> > +		return 0;
> > +
> > +	reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
> > +	udelay(1000);
> 
> What is this delay ?
I tried removing this, But with out this delay the driver is throwing timeouts.
> 
> > +
> > +	if (!reading) {
> > +		cond_delay(nfc_op.rdy_delay_ns);
> > +
> > +		if (nfc_op.cmnds[0] == NAND_CMD_SEQIN &&
> > +		    nfc_op.cmnds[1] == NAND_CMD_PAGEPROG) {
> > +			pl353_nand_write_page_raw(mtd, chip,
> > +						  instr->ctx.data.buf.out, 0,
> > +						  nfc_op.addrs);
> > +		} else {
> > +			pl353_nand_write_data_op(mtd, instr->ctx.data.buf.out,
> > +						 len);
> > +		}
> > +	}
> > +
> > +	else if (reading) {
> > +		cond_delay(nfc_op.rdy_delay_ns);
> > +		pl353_nand_read_data_op(chip, instr->ctx.data.buf.in, len);
> > +	}
> > +	cond_delay(nfc_op.data_delay_ns);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct nand_op_parser pl353_nfc_op_parser = NAND_OP_PARSER
> > +	(NAND_OP_PARSER_PATTERN
> > +		(pl353_nand_cmd_function,
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(true),
> > +		NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
> > +		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 2048)),
> > +	NAND_OP_PARSER_PATTERN
> > +		(pl353_nand_cmd_function,
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> > +		NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7),
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> > +		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false),
> > +		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 2048)),
> > +	NAND_OP_PARSER_PATTERN
> > +		(pl353_nand_cmd_function,
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> > +		NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(true),
> > +		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
> > +	NAND_OP_PARSER_PATTERN
> > +		(pl353_nand_cmd_function,
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(false),
> > +		NAND_OP_PARSER_PAT_ADDR_ELEM(false, 8),
> > +		NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 2048),
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(true),
> > +		NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
> > +	NAND_OP_PARSER_PATTERN
> > +		(pl353_nand_cmd_function,
> > +		NAND_OP_PARSER_PAT_CMD_ELEM(false)),
> > +	);
> > +
> > +static int pl353_nfc_exec_op(struct nand_chip *chip,
> > +			     const struct nand_operation *op,
> > +			     bool check_only)
> > +{
> > +	return nand_op_parser_exec_op(chip, &pl353_nfc_op_parser,
> > +					      op, check_only);
> > +}
> > +
> > +/**
> > + * pl353_nand_device_ready - Check device ready/busy line
> > + * @mtd:	Pointer to the mtd_info structure
> > + *
> > + * Return:	0 on busy or 1 on ready state
> > + */
> > +static int pl353_nand_device_ready(struct mtd_info *mtd) {
> > +	if (pl353_smc_get_nand_int_status_raw()) {
> > +		pl353_smc_clr_nand_int();
> 
> A clear is really needed here?
Yes, cfg_clr register is write only, so when ever an interrupt hits, then it needs to be cleared.
> 
> > +		return 1;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_ecc_init - Initialize the ecc information as per the ecc mode
> > + * @mtd:	Pointer to the mtd_info structure
> > + * @ecc:	Pointer to ECC control structure
> > + * @ecc_mode:	ondie ecc status
> > + *
> > + * This function initializes the ecc block and functional pointers as
> > +per the
> > + * ecc mode
> > + */
> > +static void pl353_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
> > +				int ecc_mode)
> > +{
> > +	struct nand_chip *chip = mtd_to_nand(mtd);
> > +	struct pl353_nand_info *xnand =
> > +		container_of(chip, struct pl353_nand_info, chip);
> > +
> > +
> > +	if (ecc_mode == NAND_ECC_ON_DIE) {
> > +		pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_BYPASS);
> > +		/*
> > +		 * On-Die ECC spare bytes offset 8 is used for ECC codes
> > +		 * Use the BBT pattern descriptors
> > +		 */
> > +		chip->bbt_td = &bbt_main_descr;
> > +		chip->bbt_md = &bbt_mirror_descr;
> > +		bitmap_set(chip->parameters.get_feature_list,
> > +			   ONFI_FEATURE_ON_DIE_ECC,
> ONFI_FEATURE_ON_DIE_ECC_EN);
> > +		bitmap_set(chip->parameters.set_feature_list,
> > +			   ONFI_FEATURE_ON_DIE_ECC,
> ONFI_FEATURE_ON_DIE_ECC_EN);
> > +	} else {
> > +		ecc->read_oob = pl353_nand_read_oob;
> > +		ecc->write_oob = pl353_nand_write_oob;
> > +
> > +		ecc->mode = NAND_ECC_HW;
> > +		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
> > +		ecc->bytes = 3;
> > +		ecc->strength = 1;
> > +		ecc->calculate = pl353_nand_calculate_hwecc;
> 
> I'm not sure you need this calculate()...
The ECC calculation is specific to this controller, hence a separate hwecc calculation is needed.
> 
> > +		ecc->correct = pl353_nand_correct_data;
> > +		ecc->hwctl = NULL;
> 
> You can drop the line.
Ok, I will update in next version.
> 
> > +		ecc->read_page = pl353_nand_read_page_hwecc;
> > +		ecc->size = PL353_NAND_ECC_SIZE;
> > +		ecc->write_page = pl353_nand_write_page_hwecc;
> > +		pl353_smc_set_ecc_pg_size(mtd->writesize);
> > +		switch (mtd->writesize) {
> > +		case SZ_512:
> > +		case SZ_1K:
> > +		case SZ_2K:
> > +			pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_APB);
> > +			break;
> > +		default:
> > +			/*
> > +			 * The software ECC routines won't work with the
> > +			 * SMC controller
> > +			 */
> > +			ecc->calculate = nand_calculate_ecc;
> > +			ecc->correct = nand_correct_data;
> > +			ecc->size = 256;
> > +			break;
> > +		}
> > +		if (mtd->writesize <= SZ_512)
> > +			xnand->addr_cycles = 1;
> > +		else
> > +			xnand->addr_cycles = 2;
> > +
> > +		if (chip->options & NAND_ROW_ADDR_3)
> > +			xnand->addr_cycles += 3;
> > +		else
> > +			xnand->addr_cycles += 2;
> > +
> > +		if (mtd->oobsize == 16)
> > +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout16_ops);
> > +		else if (mtd->oobsize == 64)
> > +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout64_ops);
> 
> else?
You mean to say, add an error condition?
> 
> > +	}
> > +}
> > +
> > +/**
> > + * pl353_nand_probe - Probe method for the NAND driver
> > + * @pdev:	Pointer to the platform_device structure
> > + *
> > + * This function initializes the driver data structures and the hardware.
> > + *
> > + * Return:	0 on success or error value on failure
> > + */
> > +static int pl353_nand_probe(struct platform_device *pdev) {
> > +	struct pl353_nand_info *xnand;
> 
> xnand is a strange name, more and more because its a bout NAND controller data, not NAND
> chip.
We added this name to represent Xilinx Nand(xnand), 
> 
> > +	struct mtd_info *mtd;
> > +	struct nand_chip *nand_chip;
> 
> This one you can call it just "nand" or "chip".
Ok, I will update.

> 
> > +	struct resource *res;
> > +
> > +	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
> > +	if (!xnand)
> > +		return -ENOMEM;
> > +
> > +	/* Map physical address of NAND flash */
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	xnand->nand_base = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(xnand->nand_base))
> > +		return PTR_ERR(xnand->nand_base);
> > +
> > +	nand_chip = &xnand->chip;
> > +	mtd = nand_to_mtd(nand_chip);
> > +	nand_chip->exec_op = pl353_nfc_exec_op;
> > +	nand_set_controller_data(nand_chip, xnand);
> > +	mtd->priv = nand_chip;
> > +	mtd->owner = THIS_MODULE;
> > +	mtd->name = PL353_NAND_DRIVER_NAME;
> 
> A label property in the DT might overwrite this value.
Could you please explain a bit more ?

> 
> > +	nand_set_flash_node(nand_chip, pdev->dev.of_node);
> > +
> > +	/* Set address of NAND IO lines */
> > +	nand_chip->IO_ADDR_R = xnand->nand_base;
> > +	nand_chip->IO_ADDR_W = xnand->nand_base;
> > +	/* Set the driver entry points for MTD */
> > +	nand_chip->dev_ready = pl353_nand_device_ready;
> > +	nand_chip->select_chip = pl353_nand_select_chip;
> > +	/* If we don't set this delay driver sets 20us by default */
> > +	nand_chip->chip_delay = 30;
> 
> And why 30 is better?
Let me get back to you on this.
> 
> I suppose you mean the core, not the driver. The driver is this file.
Yes, I will update
> 
> > +
> > +	/* Set the device option and flash width */
> > +	nand_chip->options = NAND_BUSWIDTH_AUTO;
> > +	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
> > +	platform_set_drvdata(pdev, xnand);
> > +
> > +	/* first scan to find the device and get the page size */
> > +	if (nand_scan_ident(mtd, 1, NULL)) {
> > +		dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
> > +		return -ENXIO;
> > +	}
> > +	pl353_nand_ecc_init(mtd, &nand_chip->ecc, nand_chip->ecc.mode);
> > +	if (nand_chip->options & NAND_BUSWIDTH_16)
> > +		pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_16);
> > +	/* second phase scan */
> > +	if (nand_scan_tail(mtd)) {
> > +		dev_err(&pdev->dev, "nand_scan_tail for NAND failed\n");
> > +		return -ENXIO;
> > +	}
> > +
> > +	mtd_device_register(mtd, NULL, 0);
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * pl353_nand_remove - Remove method for the NAND driver
> > + * @pdev:	Pointer to the platform_device structure
> > + *
> > + * This function is called if the driver module is being unloaded. It
> > +frees all
> > + * resources allocated to the device.
> > + *
> > + * Return:	0 on success or error value on failure
> > + */
> > +static int pl353_nand_remove(struct platform_device *pdev) {
> > +	struct pl353_nand_info *xnand = platform_get_drvdata(pdev);
> > +	struct mtd_info *mtd = nand_to_mtd(&xnand->chip);
> > +
> > +	/* Release resources, unregister device */
> > +	nand_release(mtd);
> > +
> > +	return 0;
> > +}
> > +
> > +/* Match table for device tree binding */ static const struct
> > +of_device_id pl353_nand_of_match[] = {
> > +	{ .compatible = "arm,pl353-nand-r2p1" },
> > +	{},
> > +};
> > +MODULE_DEVICE_TABLE(of, pl353_nand_of_match);
> > +
> > +/*
> > + * pl353_nand_driver - This structure defines the NAND subsystem
> > +platform driver  */ static struct platform_driver pl353_nand_driver =
> > +{
> > +	.probe		= pl353_nand_probe,
> > +	.remove		= pl353_nand_remove,
> > +	.driver		= {
> > +		.name	= PL353_NAND_DRIVER_NAME,
> > +		.of_match_table = pl353_nand_of_match,
> > +	},
> > +};
> > +
> > +module_platform_driver(pl353_nand_driver);
> > +
> > +MODULE_AUTHOR("Xilinx, Inc.");
> > +MODULE_ALIAS("platform:" PL353_NAND_DRIVER_NAME);
> > +MODULE_DESCRIPTION("ARM PL353 NAND Flash Driver");
> > +MODULE_LICENSE("GPL");
> 
> Thanks,
> Miquèl
> 
> --
> Miquel Raynal, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering
> https://bootlin.com

Thanks,
Naga Sureshkumar Relli.

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface
  2018-06-08 12:23     ` Naga Sureshkumar Relli
@ 2018-06-08 12:35       ` Miquel Raynal
  2018-06-08 13:08         ` Naga Sureshkumar Relli
  0 siblings, 1 reply; 17+ messages in thread
From: Miquel Raynal @ 2018-06-08 12:35 UTC (permalink / raw)
  To: Naga Sureshkumar Relli
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Naga,

> > > +		ecc->read_page = pl353_nand_read_page_hwecc;
> > > +		ecc->size = PL353_NAND_ECC_SIZE;
> > > +		ecc->write_page = pl353_nand_write_page_hwecc;
> > > +		pl353_smc_set_ecc_pg_size(mtd->writesize);
> > > +		switch (mtd->writesize) {
> > > +		case SZ_512:
> > > +		case SZ_1K:
> > > +		case SZ_2K:
> > > +			pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_APB);
> > > +			break;
> > > +		default:
> > > +			/*
> > > +			 * The software ECC routines won't work with the
> > > +			 * SMC controller
> > > +			 */
> > > +			ecc->calculate = nand_calculate_ecc;
> > > +			ecc->correct = nand_correct_data;
> > > +			ecc->size = 256;
> > > +			break;
> > > +		}
> > > +		if (mtd->writesize <= SZ_512)
> > > +			xnand->addr_cycles = 1;
> > > +		else
> > > +			xnand->addr_cycles = 2;
> > > +
> > > +		if (chip->options & NAND_ROW_ADDR_3)
> > > +			xnand->addr_cycles += 3;
> > > +		else
> > > +			xnand->addr_cycles += 2;
> > > +
> > > +		if (mtd->oobsize == 16)
> > > +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout16_ops);
> > > +		else if (mtd->oobsize == 64)
> > > +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout64_ops);  
> > 
> > else?  
> You mean to say, add an error condition?

I do.

> >   
> > > +	}
> > > +}
> > > +
> > > +/**
> > > + * pl353_nand_probe - Probe method for the NAND driver
> > > + * @pdev:	Pointer to the platform_device structure
> > > + *
> > > + * This function initializes the driver data structures and the hardware.
> > > + *
> > > + * Return:	0 on success or error value on failure
> > > + */
> > > +static int pl353_nand_probe(struct platform_device *pdev) {
> > > +	struct pl353_nand_info *xnand;  
> > 
> > xnand is a strange name, more and more because its a bout NAND controller data, not NAND
> > chip.  
> We added this name to represent Xilinx Nand(xnand), 
> >   

I see where the x comes from.

Maybe just nfc (for NAND flash controller) or xnfc if you prefer. What
I want is to clearly make the distinction between what is a NAND chip,
what is a NAND controller.

> > > +	struct mtd_info *mtd;
> > > +	struct nand_chip *nand_chip;  
> > 
> > This one you can call it just "nand" or "chip".  
> Ok, I will update.
> 
> >   
> > > +	struct resource *res;
> > > +
> > > +	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
> > > +	if (!xnand)
> > > +		return -ENOMEM;
> > > +
> > > +	/* Map physical address of NAND flash */
> > > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > +	xnand->nand_base = devm_ioremap_resource(&pdev->dev, res);
> > > +	if (IS_ERR(xnand->nand_base))
> > > +		return PTR_ERR(xnand->nand_base);
> > > +
> > > +	nand_chip = &xnand->chip;
> > > +	mtd = nand_to_mtd(nand_chip);
> > > +	nand_chip->exec_op = pl353_nfc_exec_op;
> > > +	nand_set_controller_data(nand_chip, xnand);
> > > +	mtd->priv = nand_chip;
> > > +	mtd->owner = THIS_MODULE;
> > > +	mtd->name = PL353_NAND_DRIVER_NAME;  
> > 
> > A label property in the DT might overwrite this value.  
> Could you please explain a bit more ?
> 

I meant something like this:

https://elixir.bootlin.com/linux/latest/source/drivers/mtd/nand/raw/marvell_nand.c#L2515

Thanks,
Miquèl

^ permalink raw reply	[flat|nested] 17+ messages in thread

* RE: [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface
  2018-06-08 12:35       ` Miquel Raynal
@ 2018-06-08 13:08         ` Naga Sureshkumar Relli
  0 siblings, 0 replies; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-08 13:08 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Miquel,

> -----Original Message-----
> From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> Sent: Friday, June 8, 2018 6:06 PM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> Cc: boris.brezillon@bootlin.com; richard@nod.at; wmw2@infradead.org;
> computersforpeace@gmail.com; marek.vasut@gmail.com; f.fainelli@gmail.com;
> mmayer@broadcom.com; rogerq@ti.com; ladis@linux-mips.org; ada@thorsis.com;
> honghui.zhang@mediatek.com; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> nagasureshkumarrelli@gmail.com
> Subject: Re: [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353
> smc nand interface
> 
> Hi Naga,
> 
> > > > +		ecc->read_page = pl353_nand_read_page_hwecc;
> > > > +		ecc->size = PL353_NAND_ECC_SIZE;
> > > > +		ecc->write_page = pl353_nand_write_page_hwecc;
> > > > +		pl353_smc_set_ecc_pg_size(mtd->writesize);
> > > > +		switch (mtd->writesize) {
> > > > +		case SZ_512:
> > > > +		case SZ_1K:
> > > > +		case SZ_2K:
> > > > +			pl353_smc_set_ecc_mode(PL353_SMC_ECCMODE_APB);
> > > > +			break;
> > > > +		default:
> > > > +			/*
> > > > +			 * The software ECC routines won't work with the
> > > > +			 * SMC controller
> > > > +			 */
> > > > +			ecc->calculate = nand_calculate_ecc;
> > > > +			ecc->correct = nand_correct_data;
> > > > +			ecc->size = 256;
> > > > +			break;
> > > > +		}
> > > > +		if (mtd->writesize <= SZ_512)
> > > > +			xnand->addr_cycles = 1;
> > > > +		else
> > > > +			xnand->addr_cycles = 2;
> > > > +
> > > > +		if (chip->options & NAND_ROW_ADDR_3)
> > > > +			xnand->addr_cycles += 3;
> > > > +		else
> > > > +			xnand->addr_cycles += 2;
> > > > +
> > > > +		if (mtd->oobsize == 16)
> > > > +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout16_ops);
> > > > +		else if (mtd->oobsize == 64)
> > > > +			mtd_set_ooblayout(mtd, &pl353_ecc_ooblayout64_ops);
> > >
> > > else?
> > You mean to say, add an error condition?
> 
> I do.
Ok, I will add it in next version.
> 
> > >
> > > > +	}
> > > > +}
> > > > +
> > > > +/**
> > > > + * pl353_nand_probe - Probe method for the NAND driver
> > > > + * @pdev:	Pointer to the platform_device structure
> > > > + *
> > > > + * This function initializes the driver data structures and the hardware.
> > > > + *
> > > > + * Return:	0 on success or error value on failure
> > > > + */
> > > > +static int pl353_nand_probe(struct platform_device *pdev) {
> > > > +	struct pl353_nand_info *xnand;
> > >
> > > xnand is a strange name, more and more because its a bout NAND
> > > controller data, not NAND chip.
> > We added this name to represent Xilinx Nand(xnand),
> > >
> 
> I see where the x comes from.
> 
> Maybe just nfc (for NAND flash controller) or xnfc if you prefer. What
> I want is to clearly make the distinction between what is a NAND chip,
> what is a NAND controller.
Ok, got it. I will update like xnfc.
> 
> > > > +	struct mtd_info *mtd;
> > > > +	struct nand_chip *nand_chip;
> > >
> > > This one you can call it just "nand" or "chip".
> > Ok, I will update.
> >
> > >
> > > > +	struct resource *res;
> > > > +
> > > > +	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
> > > > +	if (!xnand)
> > > > +		return -ENOMEM;
> > > > +
> > > > +	/* Map physical address of NAND flash */
> > > > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > +	xnand->nand_base = devm_ioremap_resource(&pdev->dev, res);
> > > > +	if (IS_ERR(xnand->nand_base))
> > > > +		return PTR_ERR(xnand->nand_base);
> > > > +
> > > > +	nand_chip = &xnand->chip;
> > > > +	mtd = nand_to_mtd(nand_chip);
> > > > +	nand_chip->exec_op = pl353_nfc_exec_op;
> > > > +	nand_set_controller_data(nand_chip, xnand);
> > > > +	mtd->priv = nand_chip;
> > > > +	mtd->owner = THIS_MODULE;
> > > > +	mtd->name = PL353_NAND_DRIVER_NAME;
> > >
> > > A label property in the DT might overwrite this value.
> > Could you please explain a bit more ?
> >
> 
> I meant something like this:
> 
> https://elixir.bootlin.com/linux/latest/source/drivers/mtd/nand/raw/marvell_nand.c#L251
> 5
Understood. Thanks.
I will update in next version.

Thanks,
Naga Sureshkumar Relli.
> 
> Thanks,
> Miquèl

^ permalink raw reply	[flat|nested] 17+ messages in thread

* RE: [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static memory controller
  2018-06-07 16:07   ` Miquel Raynal
@ 2018-06-19 10:54     ` Naga Sureshkumar Relli
  0 siblings, 0 replies; 17+ messages in thread
From: Naga Sureshkumar Relli @ 2018-06-19 10:54 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: boris.brezillon, richard, wmw2, computersforpeace, marek.vasut,
	f.fainelli, mmayer, rogerq, ladis, ada, honghui.zhang, linux-mtd,
	linux-kernel, nagasureshkumarrelli

Hi Miquel,

Sorry for the late reply.
Currently I am addressing the comments that you gave to  pl353_nand driver.
And done with those, but this is pending.

> -----Original Message-----
> From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> Sent: Thursday, June 7, 2018 9:37 PM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> Cc: boris.brezillon@bootlin.com; richard@nod.at; wmw2@infradead.org;
> computersforpeace@gmail.com; marek.vasut@gmail.com; f.fainelli@gmail.com;
> mmayer@broadcom.com; rogerq@ti.com; ladis@linux-mips.org; ada@thorsis.com;
> honghui.zhang@mediatek.com; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> nagasureshkumarrelli@gmail.com
> Subject: Re: [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static
> memory controller
> 
> Hi Naga,
> 
> On Wed, 6 Jun 2018 13:19:40 +0530, Naga Sureshkumar Relli
> <naga.sureshkumar.relli@xilinx.com> wrote:
> 
> > Add driver for arm pl353 static memory controller. This controller is
> > used in xilinx zynq soc for interfacing the nand and nor/sram memory
> > devices.
> 
> Upper case: Xilinx Zynq, SoC, NAND, NOR, SRAM.
Ok, I will update it in next version.

> 
> >
> > Signed-off-by: Naga Sureshkumar Relli
> > <naga.sureshkumar.relli@xilinx.com>
> > ---
> > Changes in v9:
> >  - Addressed the comments given by Julia Cartwright to the v8 series.
> > Changes in v8:
> > - None
> > Changes in v7:
> > - Corrected the kconfig to use tristate selection
> > - Corrected the GPL licence ident
> > - Added boundary checks for nand timing parameters Changes in v6:
> > - Fixed checkpatch.pl reported warnings Changes in v5:
> > - Added pl353_smc_get_clkrate function, made pl353_smc_set_cycles as public
> >   API
> > - Removed nand timing parameter initialization and moved it to nand
> > driver Changes in v4:
> > - Modified driver to support multiple instances
> > - Used sleep instaed of busywait for delay Changes in v3:
> > - None
> > Changes in v2:
> > - Since now the timing parameters are in nano seconds, added logic to convert
> >   them to the cycles
> > ---
> >  drivers/memory/Kconfig                  |   8 +
> >  drivers/memory/Makefile                 |   1 +
> >  drivers/memory/pl353-smc.c              | 523
> ++++++++++++++++++++++++++++++++
> >  include/linux/platform_data/pl353-smc.h |  29 ++
> >  4 files changed, 561 insertions(+)
> >  create mode 100644 drivers/memory/pl353-smc.c  create mode 100644
> > include/linux/platform_data/pl353-smc.h
> >
> > diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index
> > 19a0e83..9517da7 100644
> > --- a/drivers/memory/Kconfig
> > +++ b/drivers/memory/Kconfig
> > @@ -153,6 +153,14 @@ config DA8XX_DDRCTL
> >  	  Texas Instruments da8xx SoCs. It's used to tweak various memory
> >  	  controller configuration options.
> >
> > +config PL353_SMC
> > +	tristate "ARM PL35X Static Memory Controller(SMC) driver"
> > +	default y
> 
> This is not restricive at all. If this controller is only on a specific SoC, you should add another
> condition to compile the driver?
Can I add some thing like this?
depends on  ARCH_ZYNQ
depends on  ARM
> 
> > +	depends on ARM
> 
> Or here             ^
> 
> > +	help
> > +	  This driver is for the ARM PL351/PL353 Static Memory
> > +	  Controller(SMC) module.
> > +
> >  source "drivers/memory/samsung/Kconfig"
> >  source "drivers/memory/tegra/Kconfig"
> >
> > diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index
> > 66f5524..58e794d 100644
> > --- a/drivers/memory/Makefile
> > +++ b/drivers/memory/Makefile
> > @@ -20,6 +20,7 @@ obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
> >  obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
> >  obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
> >  obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
> > +obj-$(CONFIG_PL353_SMC)		+= pl353-smc.o
> >
> >  obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
> >  obj-$(CONFIG_TEGRA_MC)		+= tegra/
> > diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c
> > new file mode 100644 index 0000000..8758930
> > --- /dev/null
> > +++ b/drivers/memory/pl353-smc.c
> > @@ -0,0 +1,523 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * ARM PL353 SMC driver
> > + *
> > + * Copyright (C) 2012 Xilinx, Inc
> > + * Author: Punnaiah Choudary Kalluri <punnaiah@xilinx.com>
> > + * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
> > + *
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/platform_data/pl353-smc.h>
> > +
> > +/* Register definitions */
> > +#define PL353_SMC_MEMC_STATUS_OFFS	0	/* Controller status reg, RO
> */
> > +#define PL353_SMC_CFG_CLR_OFFS		0xC	/* Clear config reg, WO */
> > +#define PL353_SMC_DIRECT_CMD_OFFS	0x10	/* Direct command reg, WO
> */
> > +#define PL353_SMC_SET_CYCLES_OFFS	0x14	/* Set cycles register, WO */
> > +#define PL353_SMC_SET_OPMODE_OFFS	0x18	/* Set opmode register, WO */
> > +#define PL353_SMC_ECC_STATUS_OFFS	0x400	/* ECC status register */
> > +#define PL353_SMC_ECC_MEMCFG_OFFS	0x404	/* ECC mem config reg */
> > +#define PL353_SMC_ECC_MEMCMD1_OFFS	0x408	/* ECC mem cmd1 reg */
> > +#define PL353_SMC_ECC_MEMCMD2_OFFS	0x40C	/* ECC mem cmd2 reg */
> > +#define PL353_SMC_ECC_VALUE0_OFFS	0x418	/* ECC value 0 reg */
> > +
> > +/* Controller status register specific constants */
> > +#define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT	6
> > +
> > +/* Clear configuration register specific constants */
> > +#define PL353_SMC_CFG_CLR_INT_CLR_1	0x10
> > +#define PL353_SMC_CFG_CLR_ECC_INT_DIS_1	0x40
> > +#define PL353_SMC_CFG_CLR_INT_DIS_1	0x2
> > +#define PL353_SMC_CFG_CLR_DEFAULT_MASK
> 	(PL353_SMC_CFG_CLR_INT_CLR_1 | \
> > +					 PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \
> > +					 PL353_SMC_CFG_CLR_INT_DIS_1)
> > +
> > +/* Set cycles register specific constants */
> > +#define PL353_SMC_SET_CYCLES_T0_MASK	0xF
> > +#define PL353_SMC_SET_CYCLES_T0_SHIFT	0
> > +#define PL353_SMC_SET_CYCLES_T1_MASK	0xF
> > +#define PL353_SMC_SET_CYCLES_T1_SHIFT	4
> > +#define PL353_SMC_SET_CYCLES_T2_MASK	0x7
> > +#define PL353_SMC_SET_CYCLES_T2_SHIFT	8
> > +#define PL353_SMC_SET_CYCLES_T3_MASK	0x7
> > +#define PL353_SMC_SET_CYCLES_T3_SHIFT	11
> > +#define PL353_SMC_SET_CYCLES_T4_MASK	0x7
> > +#define PL353_SMC_SET_CYCLES_T4_SHIFT	14
> > +#define PL353_SMC_SET_CYCLES_T5_MASK	0x7
> > +#define PL353_SMC_SET_CYCLES_T5_SHIFT	17
> > +#define PL353_SMC_SET_CYCLES_T6_MASK	0xF
> > +#define PL353_SMC_SET_CYCLES_T6_SHIFT	20
> > +
> > +/* ECC status register specific constants */
> > +#define PL353_SMC_ECC_STATUS_BUSY	BIT(6)
> > +
> > +/* ECC memory config register specific constants */
> > +#define PL353_SMC_ECC_MEMCFG_MODE_MASK	0xC
> > +#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT	2
> > +#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK	0xC
> > +
> > +#define PL353_SMC_DC_UPT_NAND_REGS	((4 << 23) |	/* CS: NAND chip */
> \
> > +				 (2 << 21))	/* UpdateRegs operation */
> > +
> > +#define PL353_NAND_ECC_CMD1	((0x80)       |	/* Write command */ \
> > +				 (0 << 8)     |	/* Read command */ \
> > +				 (0x30 << 16) |	/* Read End command */ \
> > +				 (1 << 24))	/* Read End command calid */
> > +
> > +#define PL353_NAND_ECC_CMD2	((0x85)	      |	/* Write col change cmd */ \
> > +				 (5 << 8)     |	/* Read col change cmd */ \
> > +				 (0xE0 << 16) |	/* Read col change end cmd */ \
> > +				 (1 << 24)) /* Read col change end cmd valid */
> > +#define PL353_NAND_ECC_BUSY_TIMEOUT	(1 * HZ)
> > +/**
> > + * struct pl353_smc_data - Private smc driver structure
> > + * @devclk:		Pointer to the peripheral clock
> > + * @aperclk:		Pointer to the APER clock
> > + */
> > +struct pl353_smc_data {
> > +	struct clk		*memclk;
> > +	struct clk		*aclk;
> > +};
> > +
> > +/* SMC virtual register base */
> > +static void __iomem *pl353_smc_base;
> > +
> > +/**
> > + * pl353_smc_set_buswidth - Set memory buswidth
> > + * @bw:	Memory buswidth (8 | 16)
> > + * Return: 0 on success or negative errno.
> > + */
> > +int pl353_smc_set_buswidth(unsigned int bw) {
> > +	if (bw != PL353_SMC_MEM_WIDTH_8  && bw !=
> PL353_SMC_MEM_WIDTH_16)
> > +		return -EINVAL;
> > +
> > +	writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS);
> > +	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
> > +	       PL353_SMC_DIRECT_CMD_OFFS);
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth);
> > +
> > +/**
> > + * pl353_smc_set_cycles - Set memory timing parameters
> > + * @t0:	t_rc		read cycle time
> > + * @t1:	t_wc		write cycle time
> > + * @t2:	t_rea/t_ceoe	output enable assertion delay
> > + * @t3:	t_wp		write enable deassertion delay
> > + * @t4:	t_clr/t_pc	page cycle time
> > + * @t5:	t_ar/t_ta	ID read time/turnaround time
> > + * @t6:	t_rr		busy to RE timing
> > + *
> > + * Sets NAND chip specific timing parameters.
> > + */
> > +static void pl353_smc_set_cycles(u32 t0, u32 t1, u32 t2, u32 t3, u32
> > +			      t4, u32 t5, u32 t6)
> > +{
> > +	t0 &= PL353_SMC_SET_CYCLES_T0_MASK;
> > +	t1 = (t1 & PL353_SMC_SET_CYCLES_T1_MASK) <<
> > +			PL353_SMC_SET_CYCLES_T1_SHIFT;
> > +	t2 = (t2 & PL353_SMC_SET_CYCLES_T2_MASK) <<
> > +			PL353_SMC_SET_CYCLES_T2_SHIFT;
> > +	t3 = (t3 & PL353_SMC_SET_CYCLES_T3_MASK) <<
> > +			PL353_SMC_SET_CYCLES_T3_SHIFT;
> > +	t4 = (t4 & PL353_SMC_SET_CYCLES_T4_MASK) <<
> > +			PL353_SMC_SET_CYCLES_T4_SHIFT;
> > +	t5 = (t5 & PL353_SMC_SET_CYCLES_T5_MASK) <<
> > +			PL353_SMC_SET_CYCLES_T5_SHIFT;
> > +	t6 = (t6 & PL353_SMC_SET_CYCLES_T6_MASK) <<
> > +			PL353_SMC_SET_CYCLES_T6_SHIFT;
> > +
> > +	t0 |= t1 | t2 | t3 | t4 | t5 | t6;
> > +
> > +	writel(t0, pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS);
> > +	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
> > +	       PL353_SMC_DIRECT_CMD_OFFS);
> > +}
> > +
> > +/**
> > + * pl353_smc_ecc_is_busy - Read ecc busy flag
> > + * Return: the ecc_status bit from the ecc_status register. 1 = busy,
> > +0 = idle  */ int pl353_smc_ecc_is_busy(void) {
> > +	return !!(readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) &
> > +		  PL353_SMC_ECC_STATUS_BUSY);
> 
> You can return a bool and avoid the '!!'.
Ok, I will update in next version.
> 
> > +}
> > +EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy);
> > +
> > +/**
> > + * pl353_smc_get_ecc_val - Read ecc_valueN registers
> > + * @ecc_reg:	Index of the ecc_value reg (0..3)
> > + * Return: the content of the requested ecc_value register.
> > + *
> > + * There are four valid ecc_value registers. The argument is
> > +truncated to stay
> > + * within this valid boundary.
> > + */
> > +u32 pl353_smc_get_ecc_val(int ecc_reg) {
> > +	u32 addr, reg;
> > +
> > +	ecc_reg &= 3;
> 
> This is not readable. Please check for the validity of ecc_reg with standard '<' '>' operators.
Ok, I will change it.
> 
> > +	addr = PL353_SMC_ECC_VALUE0_OFFS + (ecc_reg << 2);
> 
> 2 should be defined
> 
> > +	reg = readl(pl353_smc_base + addr);
> > +
> > +	return reg;
> > +}
> > +EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val);
> > +
> > +/**
> > + * pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
> > + * Return: the raw_int_status1 bit from the memc_status register
> 
> If you use kernel-doc format, should be "@return".
Ok, I will update it.
> 
> > + */
> > +int pl353_smc_get_nand_int_status_raw(void)
> > +{
> > +	u32 reg;
> > +
> > +	reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS);
> > +	reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
> > +	reg &= 1;
> > +
> > +	return reg;
> > +}
> > +EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw);
> > +
> > +/**
> > + * pl353_smc_clr_nand_int - Clear NAND interrupt  */ void
> > +pl353_smc_clr_nand_int(void) {
> > +	writel(PL353_SMC_CFG_CLR_INT_CLR_1,
> > +	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS); }
> > +EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int);
> > +
> > +/**
> > + * pl353_smc_set_ecc_mode - Set SMC ECC mode
> > + * @mode:	ECC mode (BYPASS, APB, MEM)
> > + * Return: 0 on success or negative errno.
> > + */
> > +int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)
> > +{
> > +	u32 reg;
> > +	int ret = 0;
> > +
> > +	switch (mode) {
> > +	case PL353_SMC_ECCMODE_BYPASS:
> > +	case PL353_SMC_ECCMODE_APB:
> > +	case PL353_SMC_ECCMODE_MEM:
> > +
> > +		reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> > +		reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK;
> > +		reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;
> > +		writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> > +
> > +		break;
> > +	default:
> > +		ret = -EINVAL;
> > +	}
> > +
> > +	return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode);
> > +
> > +/**
> > + * pl353_smc_set_ecc_pg_size - Set SMC ECC page size
> > + * @pg_sz:	ECC page size
> > + * Return: 0 on success or negative errno.
> > + */
> > +int pl353_smc_set_ecc_pg_size(unsigned int pg_sz)
> > +{
> > +	u32 reg, sz;
> > +
> > +	switch (pg_sz) {
> > +	case 0:
> > +		sz = 0;
> > +		break;
> > +	case SZ_512:
> > +		sz = 1;
> > +		break;
> > +	case SZ_1K:
> > +		sz = 2;
> > +		break;
> > +	case SZ_2K:
> > +		sz = 3;
> > +		break;
> > +	default:
> > +		return -EINVAL;
> > +	}
> > +
> > +	reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> > +	reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK;
> > +	reg |= sz;
> > +	writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size);
> > +
> > +static int __maybe_unused pl353_smc_suspend(struct device *dev)
> > +{
> > +	struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
> > +
> > +	clk_disable(pl353_smc->memclk);
> > +	clk_disable(pl353_smc->aclk);
> 
> Are you sure you don't need to save any of the configured registers?
Yes
> 
> > +
> > +	return 0;
> > +}
> > +
> > +static int __maybe_unused pl353_smc_resume(struct device *dev)
> > +{
> > +	int ret;
> > +	struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
> > +
> > +	ret = clk_enable(pl353_smc->aclk);
> > +	if (ret) {
> > +		dev_err(dev, "Cannot enable axi domain clock.\n");
> > +		return ret;
> > +	}
> > +
> > +	ret = clk_enable(pl353_smc->memclk);
> > +	if (ret) {
> > +		dev_err(dev, "Cannot enable memory clock.\n");
> > +		clk_disable(pl353_smc->aclk);
> > +		return ret;
> > +	}
> 
> New line
Ok, I will update
> 
> > +	return ret;
> > +}
> > +
> > +static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
> > +			 pl353_smc_resume);
> > +
> > +/**
> > + * pl353_smc_init_nand_interface - Initialize the NAND interface
> > + * @pdev:	Pointer to the platform_device struct
> > + * @nand_node:	Pointer to the pl353_nand device_node struct
> > + */
> > +static void pl353_smc_init_nand_interface(struct platform_device *pdev,
> > +					  struct device_node *nand_node)
> > +{
> > +	u32 t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr;
> > +	int err;
> > +	unsigned long timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
> 
> Maybe this should be defined later in the code.
I will update in next version.
> 
> New line.
> 
> > +	/* nand-cycle-<X> property is refer to the NAND flash timing
> > +	 * mapping between dts and the NAND flash AC timing
> > +	 *  X  : AC timing name
> > +	 *  t0 : t_rc
> > +	 *  t1 : t_wc
> > +	 *  t2 : t_rea
> > +	 *  t3 : t_wp
> > +	 *  t4 : t_clr
> > +	 *  t5 : t_ar
> > +	 *  t6 : t_rr
> > +	 */
> > +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t0", &t_rc);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "arm,nand-cycle-t0 not in device tree");
> > +		goto default_nand_timing;
> > +	}
> > +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t1", &t_wc);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "arm,nand-cycle-t1 not in device tree");
> > +		goto default_nand_timing;
> > +	}
> > +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t2", &t_rea);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "arm,nand-cycle-t2 not in device tree");
> > +		goto default_nand_timing;
> > +	}
> > +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t3", &t_wp);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "arm,nand-cycle-t3 not in device tree");
> > +		goto default_nand_timing;
> > +	}
> > +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t4", &t_clr);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "arm,nand-cycle-t4 not in device tree");
> > +		goto default_nand_timing;
> > +	}
> > +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t5", &t_ar);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "arm,nand-cycle-t5 not in device tree");
> > +		goto default_nand_timing;
> > +	}
> > +	err = of_property_read_u32(nand_node, "arm,nand-cycle-t6", &t_rr);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "arm,nand-cycle-t6 not in device tree");
> > +		goto default_nand_timing;
> > +	}
> 
> See the comment in the bindings about this section.
Any way I am removing the above parameters reading as per your comment.
I will implement setup_data_interface() hook to get the timings. And this 
Applies to below comments as well.
> 
> > +
> > +default_nand_timing:
> > +	/*
> > +	 * Default assume 50MHz clock (20ns cycle time) and 3V operation
> > +	 * The SET_CYCLES_REG register value depends on the flash device.
> > +	 * Look in to the device datasheet and change its value, This value
> > +	 * is for 2Gb Numonyx flash.
> 
> No :)
> 
> The controller is not supposed to work with only one chip, right? So it
> should not embed any chip-specific information.
> 
> If this chip is not ONFI nor JEDEC and is not supported yet, the right
> way to do is to write a manufacturer driver.
> 
> > +	 */
> > +	if (err) {
> > +		/* set default NAND flash timing property */
> > +		dev_warn(&pdev->dev, "Using default timing for");
> > +		dev_warn(&pdev->dev, "2Gb Numonyx MT29F2G08ABAEAWP NAND
> flash");
> > +		dev_warn(&pdev->dev, "t_wp, t_clr, t_ar are set to 2");
> > +		dev_warn(&pdev->dev, "t_rc, t_wc, t_rr are set to 4");
> > +		dev_warn(&pdev->dev, "t_rea is set to 1");
> > +		t_rc = 4;
> > +		t_wc = 4;
> > +		t_rr = 4;
> > +		t_rea = 1;
> > +		t_wp = 2;
> > +		t_clr = 2;
> > +		t_ar = 2;
> > +	}
> > +
> > +	pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8);
> > +	pl353_smc_set_cycles(t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr);
> > +	writel(PL353_SMC_CFG_CLR_INT_CLR_1,
> > +	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
> > +	writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
> > +	       PL353_SMC_DIRECT_CMD_OFFS);
> > +	/* Wait till the ECC operation is complete */
> > +	do {
> > +		if (pl353_smc_ecc_is_busy())
> > +			cpu_relax();
> > +		else
> > +			break;
> > +	} while (!time_after_eq(jiffies, timeout));
> > +
> > +	if (time_after_eq(jiffies, timeout))
> > +		dev_err(&pdev->dev, "nand ecc busy status timed out");
> > +
> > +	writel(PL353_NAND_ECC_CMD1,
> > +	       pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS);
> > +	writel(PL353_NAND_ECC_CMD2,
> > +	       pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS);
> > +}
> > +
> > +static const struct of_device_id pl353_smc_supported_children[] = {
> > +	{ .compatible = "cfi-flash" },
> > +	{ .compatible = "arm,pl353-nand-r2p1",
> > +	.data = pl353_smc_init_nand_interface },
> 
> Please put the compatibles on another line and align data with them.
Ok, I will update it next version.

> 
> > +	{}
> > +};
> > +
> > +static int pl353_smc_probe(struct platform_device *pdev)
> > +{
> > +	struct pl353_smc_data *pl353_smc;
> > +	struct device_node *child;
> > +	struct resource *res;
> > +	int err;
> > +	struct device_node *of_node = pdev->dev.of_node;
> > +	void (*init)(struct platform_device *pdev,
> > +		     struct device_node *nand_node);
> > +	const struct of_device_id *match = NULL;
> > +
> > +	pl353_smc = devm_kzalloc(&pdev->dev, sizeof(*pl353_smc), GFP_KERNEL);
> > +	if (!pl353_smc)
> > +		return -ENOMEM;
> > +
> > +	/* Get the NAND controller virtual address */
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	pl353_smc_base = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(pl353_smc_base))
> > +		return PTR_ERR(pl353_smc_base);
> > +
> > +	pl353_smc->aclk = devm_clk_get(&pdev->dev, "aclk");
> > +	if (IS_ERR(pl353_smc->aclk)) {
> > +		dev_err(&pdev->dev, "aclk clock not found.\n");
> > +		return PTR_ERR(pl353_smc->aclk);
> > +	}
> > +
> > +	pl353_smc->memclk = devm_clk_get(&pdev->dev, "memclk");
> > +	if (IS_ERR(pl353_smc->memclk)) {
> > +		dev_err(&pdev->dev, "memclk clock not found.\n");
> > +		return PTR_ERR(pl353_smc->memclk);
> > +	}
> > +
> > +	err = clk_prepare_enable(pl353_smc->aclk);
> > +	if (err) {
> > +		dev_err(&pdev->dev, "Unable to enable AXI clock.\n");
> > +		return err;
> > +	}
> > +
> > +	err = clk_prepare_enable(pl353_smc->memclk);
> > +	if (err) {
> > +		dev_err(&pdev->dev, "Unable to enable memory clock.\n");
> > +		goto out_clk_dis_aper;
> > +	}
> > +
> > +	platform_set_drvdata(pdev, pl353_smc);
> > +
> > +	/* clear interrupts */
> > +	writel(PL353_SMC_CFG_CLR_DEFAULT_MASK,
> > +	       pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
> > +
> > +	/* Find compatible children. Only a single child is supported */
> > +	for_each_available_child_of_node(of_node, child) {
> > +		match = of_match_node(pl353_smc_supported_children, child);
> > +		if (!match) {
> > +			dev_warn(&pdev->dev, "unsupported child node\n");
> > +			continue;
> > +		}
> > +		break;
> > +	}
> > +	if (!match) {
> > +		dev_err(&pdev->dev, "no matching children\n");
> > +		goto out_clk_disable;
> > +	}
> > +
> > +	init = match->data;
> > +	if (init)
> > +		init(pdev, child);
> > +	of_platform_device_create(child, NULL, &pdev->dev);
> > +
> > +	return 0;
> > +
> > +out_clk_disable:
> > +	clk_disable_unprepare(pl353_smc->memclk);
> > +out_clk_dis_aper:
> > +	clk_disable_unprepare(pl353_smc->aclk);
> > +
> > +	return err;
> > +}
> > +
> > +static int pl353_smc_remove(struct platform_device *pdev)
> > +{
> > +	struct pl353_smc_data *pl353_smc = platform_get_drvdata(pdev);
> > +
> > +	clk_disable_unprepare(pl353_smc->memclk);
> > +	clk_disable_unprepare(pl353_smc->aclk);
> > +
> > +	return 0;
> > +}
> > +
> > +/* Match table for device tree binding */
> > +static const struct of_device_id pl353_smc_of_match[] = {
> > +	{ .compatible = "arm,pl353-smc-r2p1" },
> > +	{ },
> > +};
> > +MODULE_DEVICE_TABLE(of, pl353_smc_of_match);
> > +
> > +static struct platform_driver pl353_smc_driver = {
> > +	.probe		= pl353_smc_probe,
> > +	.remove		= pl353_smc_remove,
> > +	.driver		= {
> > +		.name	= "pl353-smc",
> > +		.pm	= &pl353_smc_dev_pm_ops,
> > +		.of_match_table = pl353_smc_of_match,
> > +	},
> > +};
> > +
> > +module_platform_driver(pl353_smc_driver);
> > +
> > +MODULE_AUTHOR("Xilinx, Inc.");
> > +MODULE_DESCRIPTION("ARM PL353 SMC Driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/include/linux/platform_data/pl353-smc.h b/include/linux/platform_data/pl353-
> smc.h
> 
> I don't think you really need a separate file for these enums? Unless
> it is really platform specific?
The issue here is I have to include this in pl353_nand driver.
And I just referred " include/linux/platform_data/mtd-nand-pxa3xx.h", hence
I added like this.
> 
> > new file mode 100644
> > index 0000000..fc4129e
> > --- /dev/null
> > +++ b/include/linux/platform_data/pl353-smc.h
> > @@ -0,0 +1,29 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * ARM PL353 SMC Driver Header
> > + *
> > + * Copyright (C) 2017 Xilinx, Inc
> > + */
> > +
> > +#ifndef __LINUX_MEMORY_PL353_SMC_H
> > +#define __LINUX_MEMORY_PL353_SMC_H
> > +
> > +enum pl353_smc_ecc_mode {
> > +	PL353_SMC_ECCMODE_BYPASS = 0,
> > +	PL353_SMC_ECCMODE_APB = 1,
> > +	PL353_SMC_ECCMODE_MEM = 2
> > +};
> > +
> > +enum pl353_smc_mem_width {
> > +	PL353_SMC_MEM_WIDTH_8 = 0,
> > +	PL353_SMC_MEM_WIDTH_16 = 1
> > +};
> > +
> > +u32 pl353_smc_get_ecc_val(int ecc_reg);
> > +int pl353_smc_ecc_is_busy(void);
> > +int pl353_smc_get_nand_int_status_raw(void);
> > +void pl353_smc_clr_nand_int(void);
> > +int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode);
> > +int pl353_smc_set_ecc_pg_size(unsigned int pg_sz);
> > +int pl353_smc_set_buswidth(unsigned int bw);
> > +#endif
> 
> Thanks,
> Miquèl
> 
> --
> Miquel Raynal, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> https://bootlin.com

Thanks,
Naga Sureshkumar Relli

^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2018-06-19 10:54 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-06  7:49 [LINUX PATCH v9 0/4] Add arm pl353 smc memory and nand driver for xilinx zynq soc Naga Sureshkumar Relli
2018-06-06  7:49 ` [LINUX PATCH v9 1/4] Devicetree: Add pl353 smc controller devicetree binding information Naga Sureshkumar Relli
2018-06-07 15:42   ` Miquel Raynal
2018-06-07 15:47     ` Miquel Raynal
2018-06-08  5:20     ` Naga Sureshkumar Relli
2018-06-08  5:51       ` Boris Brezillon
2018-06-08  8:01         ` Naga Sureshkumar Relli
2018-06-08  7:23       ` Miquel Raynal
2018-06-06  7:49 ` [LINUX PATCH v9 2/4] memory: pl353: Add driver for arm pl353 static memory controller Naga Sureshkumar Relli
2018-06-07 16:07   ` Miquel Raynal
2018-06-19 10:54     ` Naga Sureshkumar Relli
2018-06-06  7:49 ` [LINUX PATCH v9 3/4] Documentation: nand: pl353: Add documentation for controller and driver Naga Sureshkumar Relli
2018-06-06  7:49 ` [LINUX PATCH v9 4/4] mtd: rawnand: pl353: Add basic driver for arm pl353 smc nand interface Naga Sureshkumar Relli
2018-06-07 19:59   ` Miquel Raynal
2018-06-08 12:23     ` Naga Sureshkumar Relli
2018-06-08 12:35       ` Miquel Raynal
2018-06-08 13:08         ` Naga Sureshkumar Relli

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