LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: Tony Lindgren <tony@atomide.com>
To: Christina Quast <cquast@hanoverdisplays.com>
Cc: bcousson@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com,
	mpfj@newflow.co.uk, linux-omap@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] ARM: dts: am335x: Replace numeric pinmux address with macro defines
Date: Thu, 14 Mar 2019 07:59:30 -0700	[thread overview]
Message-ID: <20190314145930.GA19425@atomide.com> (raw)
In-Reply-To: <20190313142724.27446-2-cquast@hanoverdisplays.com>

Hi,

* Christina Quast <cquast@hanoverdisplays.com> [190313 14:28]:
> The values are extraced from the "AM335x SitaraTM Processors Technical
> Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the
> file autogenerated by TI PinMux.

Thanks for updating this series. Few comments below.

> diff --git a/include/dt-bindings/pinctrl/am335x.h b/include/dt-bindings/pinctrl/am335x.h
> new file mode 100644
> index 000000000000..033a44efdc1e
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/am335x.h

I think these defines should be just added to the existing
include/dt-bindings/pinctrl/am33xx.h. That is assuming the
padconf registers are the same for all the variants.

> +#define PIN_MODE(mode)		(mode)
> +#define PIN_PULL_UD_EN		(0x1U << 3U)
> +#define	PIN_PULL_TYPE_SEL	(0x1U << 4U)
> +#define	PIN_RX_ACTIVE		(0x1U << 5U)
> +#define PIN_SLEW_SLOW		(0x1U << 6U)

Hmm so in include/dt-bindings/pinctrl/am33xx.h we already have
these defined but with different names?

> +#define AM335X_PIN_OFFSET_MIN			0x0800U

You should leave out the generic control module registers
defines. So starting below..

> +#define AM335X_CONTROL_REVISION			0x0
> +#define AM335X_CONTROL_HWINFO			0x4
> +#define AM335X_CONTROL_SYSCONFIG		0x10
> +#define AM335X_CONTROL_STATUS			0x40
> +#define AM335X_CONTROL_EMIF_SDRAM_CONFIG	0x110
...
> +#define AM335X_BB_SCALE				0x7d0
> +#define AM335X_USB_VID_PID			0x7f4
> +#define AM335X_EFUSE_SMA			0x7fc

.. all the way here. This header should only have the
padconf area registers that should all have PIN in the
name. So only keep the ones from below..

> +#define AM335X_PIN_GPMC_AD0			0x800
> +#define AM335X_PIN_GPMC_AD1			0x804
> +#define AM335X_PIN_GPMC_AD2			0x808
...
> +#define AM335X_PIN_USB0_DRVVBUS			0xa1c
> +#define AM335X_PIN_USB1_DRVVBUS			0xa34

.. to here. Then also drop the defines from here..

> +#define AM335X_CQDETECT_STATUS			0xe00
> +#define AM335X_DDR_IO_CTRL			0xe04
> +#define AM335X_VTP_CTRL				0xe0c
...
> +#define AM335X_DDR_CMD2_IOCTRL			0x140c
> +#define AM335X_DDR_DATA0_IOCTRL			0x1440
> +#define AM335X_DDR_DATA1_IOCTRL			0x1444

.. to here.

> +#define AM335X_PIN_OFFSET_MAX			0x1320U

And then adjust the AM335X_PIN_OFFSET_MAX accordingly
if that is needed.

Note that the padconf range is specified in am33xx-l4.dtsi
for pinmux@800 in the reg range so this header should
contain the same registers. Some SoCs have multiple padconf
ranges but am335x only has one.

Regards,

Tony

  reply	other threads:[~2019-03-14 14:59 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-13 14:27 [PATCH 0/2] " Christina Quast
2019-03-13 14:27 ` [PATCH 1/2] " Christina Quast
2019-03-14 14:59   ` Tony Lindgren [this message]
2019-03-13 14:27 ` [PATCH 2/2] ARM: dts: am335x: Replaced register offsets with defines Christina Quast
2019-03-14 15:05   ` Tony Lindgren
     [not found]     ` <4FA4A861EC9F6744BE8446EF2CDFAFE11FF8885D@mail.hanover.local>
2019-03-14 16:12       ` Tony Lindgren
  -- strict thread matches above, loose matches on Subject: below --
2018-04-30 11:20 [PATCH 0/2] Add macro defines for AM335x Christina Quast
2018-04-30 11:20 ` [PATCH 1/2] ARM: dts: am335x: Replace numeric pinmux address with macro defines Christina Quast
2018-04-30 17:31   ` Tony Lindgren
2018-05-03 15:52     ` Grygorii Strashko
2018-05-03 16:19       ` Tony Lindgren
2018-05-03 18:25         ` Grygorii Strashko

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190314145930.GA19425@atomide.com \
    --to=tony@atomide.com \
    --cc=bcousson@baylibre.com \
    --cc=cquast@hanoverdisplays.com \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-omap@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=mpfj@newflow.co.uk \
    --cc=robh+dt@kernel.org \
    --subject='Re: [PATCH 1/2] ARM: dts: am335x: Replace numeric pinmux address with macro defines' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).