Re: [PATCH] pinctrl: intel: save HOSTSW_OWN register over suspend/resume

[Mika Westerberg <mika.westerberg@linux.intel.com>]

On Thu, Mar 28, 2019 at 08:19:59PM +0800, Chris Chiu wrote:
> On Thu, Mar 28, 2019 at 5:38 PM Daniel Drake <drake@endlessm.com> wrote:
> >
> > On Thu, Mar 28, 2019 at 5:17 PM Andy Shevchenko
> > <andriy.shevchenko@intel.com> wrote:
> > > Hmm... Can you confirm that laptop you declared as a fixed case and the
> > > mentioned here is the same one?
> >
> > They are definitely not the same exact unit - originally we had a
> > pre-production sample, and now we briefly diagnosed a real production
> > unit that was sold to a customer. There could be subtle motherboard
> > variations as you mention.
> >
> > > If it's the case, I recommend to ping Asus again and make them check and fix.
> >
> > We'll keep an eye open for any opportunities to go deeper here.
> > However further investigation on both our side and theirs is blocked
> > by not having any of the affected hardware (since the models are now
> > so old), so I'm not very optimistic that we'll be able to make
> > progress there.
> >
> > > Meanwhile, Mika's proposal sounds feasible and not so intrusive. We may
> > > implement this later on.
> >
> > Chris will work on implementing this for your consideration.
> >
> > Thanks for the quick feedback!
> > Daniel
> 
> What if I modify the patch as follows? It doesn't save HOSTSW_OWN register.
> It just toggles the bit specifically for the IRQ GPIO pin after resume when DMI
> matches.

I don't really like having quirks like this if we can avoid it and in
this case I think we can. Just always save HOSTSW_OWN and then restore
it if there is a GPIO requested and the value differs (and log a warning
or something like that).