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From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Chris Chiu <chiu@endlessm.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
	Daniel Drake <drake@endlessm.com>,
	Heikki Krogerus <heikki.krogerus@linux.intel.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	"open list:PIN CONTROL SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	Linux Upstreaming Team <linux@endlessm.com>
Subject: Re: [PATCH] pinctrl: intel: save HOSTSW_OWN register over suspend/resume
Date: Wed, 3 Apr 2019 16:06:40 +0300	[thread overview]
Message-ID: <20190403130640.GD9224@smile.fi.intel.com> (raw)
In-Reply-To: <CAB4CAwe7n5XsRNS-ZoJL1K7dHLpRrwNReBCCMXjDWCtxYaqfdQ@mail.gmail.com>

On Wed, Apr 03, 2019 at 03:06:43PM +0800, Chris Chiu wrote:
> On Tue, Apr 2, 2019 at 7:58 PM Andy Shevchenko
> <andriy.shevchenko@intel.com> wrote:

> > Instead you may need to loop over each pin in the part of the group related to
> > one 32-bit HOSTSW_OWN register (i.e. 8, see PADOWN_*() macros in the driver),
> > check if it's requested and break a loop. If loop index is off-by-one a limit,
> > nothing to do, otherwise restore hostown register.
> >
> > More pedantic approach is to collect the mask inside the loop and apply it.
> >
> > The check function name is gpiochip_is_requested().
> >
> > (One of Intel's drivers which is using that at ->resume() is
> >  drivers/gpio/gpio-lynxpoint.c)
> >
> > P.S. I prefer pedantic approach. The simplification one is showed in order to
> > give you an idea.

> Thanks for your great comment. I remove the useless hostown save function
> and make the following change in ->resume() to detect and restore the abnormal
> HOSTSW_OWN. Please help comment if there're still problems. Thanks.

> +               base = community->regs + community->hostown_offset;
> +               for (gpp = 0; gpp < community->ngpps; gpp++) {
> +                       const struct intel_padgroup *padgrp =
> &community->gpps[i];
> +                       unsigned int requested = 0;
> +                       int j;
> +
> +                       if (padgrp->gpio_base < 0)
> +                               continue;

> +
> +                       for (j = 0; j < padgrp->size; j++)
> +                               if
> (gpiochip_is_requested(&pctrl->chip, padgrp->gpio_base + j))
> +                                       requested |= BIT(j);
> +

This better to make as a separate helper function

static u32 intel_gpio_is_requested(chip, base, size)
{
	u32 requested = 0;
	unsigned int i;

	for () {
		if ()
			requested |= BIT();
	}
	return requested;
}

(Note u32 as a type)

> +                       if (requested) {
> +                               if (communities[i].hostown[gpp] !=
> readl(base + gpp * 4)) {
> +
> writel(communities[i].hostown[gpp], base + gpp * 4);

The idea here not to check this at all, but rather apply a mask.

u32 value;

...
value = readl();
value = (value & ~requested) | (hostown[gpp] & requested);
writel(value);

> +                                       dev_warn(dev, "hostown been
> changed during resume\n");
> +                                       dev_dbg(dev, "restored hostown
> %d/%u %#08x\n", i, gpp,
> +                                               readl(base + gpp * 4));
> +                               }
> +                       }
> +               }

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2019-04-03 13:06 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-14 10:41 [PATCH] pinctrl: intel: save HOSTSW_OWN register over suspend/resume Chris Chiu
     [not found] ` <20171115080446.GY17200@lahna.fi.intel.com>
2017-11-15  8:08   ` Chris Chiu
2017-11-15 10:13     ` Mika Westerberg
2017-11-15 10:19       ` Chris Chiu
2017-11-16 12:44         ` Mika Westerberg
2017-11-16 13:27           ` Chris Chiu
2017-11-17  6:49             ` Mika Westerberg
2017-11-17  8:11               ` Chris Chiu
2017-11-21 10:52                 ` Mika Westerberg
2017-11-21 11:54                   ` Chris Chiu
2017-11-21 12:04                     ` Mika Westerberg
2017-11-23 12:24                       ` Chris Chiu
2017-11-23 12:43                         ` Mika Westerberg
2019-03-27  8:22                       ` Daniel Drake
2019-03-27 17:29                         ` Mika Westerberg
2019-03-28  8:28                           ` Mika Westerberg
2019-03-28  9:17                           ` Andy Shevchenko
2019-03-28  9:38                             ` Daniel Drake
2019-03-28 12:19                               ` Chris Chiu
2019-03-28 12:34                                 ` Mika Westerberg
2019-03-29  8:38                                   ` Chris Chiu
2019-04-01  7:49                                     ` Mika Westerberg
2019-04-01 10:41                                       ` Chris Chiu
2019-04-01 12:22                                         ` Andy Shevchenko
2019-04-02  6:16                                           ` Chris Chiu
2019-04-02 11:58                                             ` Andy Shevchenko
2019-04-03  7:06                                               ` Chris Chiu
2019-04-03 13:06                                                 ` Andy Shevchenko [this message]
2019-04-04 13:06                                                   ` Chris Chiu
2019-04-04 13:59                                                     ` Andy Shevchenko

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