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From: Paul Walmsley <paul.walmsley@sifive.com>
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Paul Walmsley <paul@pwsan.com>, Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: [PATCH 5/6] riscv: dts: add initial board data for the SiFive HiFive Unleashed
Date: Thu, 11 Apr 2019 01:43:03 -0700	[thread overview]
Message-ID: <20190411084304.5072-6-paul.walmsley@sifive.com> (raw)
In-Reply-To: <20190411084304.5072-2-paul.walmsley@sifive.com>

Add initial board data for the SiFive HiFive Unleashed A00.

Currently the data populated in this DT file describes the board
DRAM configuration and the external clock sources that supply the
PRCI.

This second version adds onboard SPI device data, fixes the board's
memory size, and adds changes based on comments from Rob Herring
<robh+dt@kernel.org>.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/riscv/boot/dts/sifive/Makefile           |  2 +
 .../dts/sifive/hifive-unleashed-a00-fu540.dts | 69 +++++++++++++++++++
 2 files changed, 71 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sifive/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts

diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
new file mode 100644
index 000000000000..fb825db888df
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00-fu540.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
new file mode 100644
index 000000000000..9d35e811a3aa
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (Apache-2.0 OR GPL-2.0+)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include "fu540-c000.dtsi"
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SiFive HiFive Unleashed A00 (FU540-C000)";
+	compatible = "sifive,hifive-unleashed-a00-fu540",
+		"sifive,hifive-unleashed-fu540",
+		"sifive,fu540-c000", "sifive-fu540";
+
+	chosen {
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+
+	soc {
+	};
+
+	hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <33333333>;
+		clock-output-names = "hfclk";
+	};
+
+	rtcclk: rtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <RTCCLK_FREQ>;
+		clock-output-names = "rtcclk";
+	};
+};
+
+&qspi0 {
+	flash@0 {
+		compatible = "issi,is25wp256d", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&qspi2 {
+	status = "okay";
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		voltage-ranges = <3300 3300>;
+		disable-wp;
+	};
+};
-- 
2.20.1


  parent reply	other threads:[~2019-04-11  8:43 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-11  8:42 [PATCH 1/6] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2019-04-11  8:43 ` [PATCH 2/6] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Paul Walmsley
2019-04-29 18:08   ` Rob Herring
2019-04-29 18:13     ` Paul Walmsley
2019-04-11  8:43 ` [PATCH 3/6] dt-bindings: riscv: convert cpu binding to json-schema Paul Walmsley
2019-04-11 12:55   ` Rob Herring
2019-04-11  8:43 ` [PATCH 4/6] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2019-04-11 13:10   ` Rob Herring
2019-04-11  8:43 ` Paul Walmsley [this message]
2019-04-11 13:03   ` [PATCH 5/6] riscv: dts: add initial board data for the SiFive HiFive Unleashed Rob Herring
2019-04-11  8:43 ` [PATCH 6/6] riscv: defconfig: enable ARCH_SIFIVE Paul Walmsley
2019-04-11 11:46 ` [PATCH 1/6] arch: riscv: add support for building DTB files from DT source data Christoph Hellwig
2019-04-11 21:11   ` Paul Walmsley
2019-04-11 21:52     ` Atish Patra
2019-04-12  0:08       ` Paul Walmsley
2019-04-12  5:49         ` Christoph Hellwig
2019-04-12  7:37         ` Atish Patra
2019-04-11 21:38   ` Atish Patra
2019-05-22 19:18 ` Loys Ollivier

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