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From: Andrew Lunn <andrew@lunn.ch>
To: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Rasmus Villemoes <Rasmus.Villemoes@prevas.se>
Subject: Re: [RFC PATCH 1/5] net: dsa: mv88e6xxx: introduce support for two chips using direct smi addressing
Date: Wed, 1 May 2019 22:19:19 +0200	[thread overview]
Message-ID: <20190501201919.GC19809@lunn.ch> (raw)
In-Reply-To: <20190501193126.19196-2-rasmus.villemoes@prevas.dk>

On Wed, May 01, 2019 at 07:32:10PM +0000, Rasmus Villemoes wrote:
> The 88e6250 (as well as 6220, 6071, 6070, 6020) do not support
> multi-chip (indirect) addressing. However, one can still have two of
> them on the same mdio bus, since the device only uses 16 of the 32
> possible addresses, either addresses 0x00-0x0F or 0x10-0x1F depending
> on the ADDR4 pin at reset [since ADDR4 is internally pulled high, the
> latter is the default].
> 
> In order to prepare for supporting the 88e6250 and friends, introduce
> mv88e6xxx_info::dual_chip to allow having a non-zero sw_addr while
> still using direct addressing.
> 
> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
> ---
>  drivers/net/dsa/mv88e6xxx/chip.c | 10 +++++++---
>  drivers/net/dsa/mv88e6xxx/chip.h |  5 +++++
>  2 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
> index c078c791f481..f66daa77774b 100644
> --- a/drivers/net/dsa/mv88e6xxx/chip.c
> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
> @@ -62,6 +62,10 @@ static void assert_reg_lock(struct mv88e6xxx_chip *chip)
>   * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
>   * multiple devices to share the SMI interface. In this mode it responds to only
>   * 2 registers, used to indirectly access the internal SMI devices.
> + *
> + * Some chips use a different scheme: Only the ADDR4 pin is used for
> + * configuration, and the device responds to 16 of the 32 SMI
> + * addresses, allowing two to coexist on the same SMI interface.
>   */
>  
>  static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
> @@ -87,7 +91,7 @@ static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
>  {
>  	int ret;
>  
> -	ret = mdiobus_read_nested(chip->bus, addr, reg);
> +	ret = mdiobus_read_nested(chip->bus, addr + chip->sw_addr, reg);
>  	if (ret < 0)
>  		return ret;
>  
> @@ -101,7 +105,7 @@ static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
>  {
>  	int ret;
>  
> -	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
> +	ret = mdiobus_write_nested(chip->bus, addr + chip->sw_addr, reg, val);
>  	if (ret < 0)
>  		return ret;

Hi Rasmus

This works, but i think i prefer adding mv88e6xxx_smi_dual_chip_write,
mv88e6xxx_smi_dual_chip_read, and create a
mv88e6xxx_smi_single_chip_ops.

>  
> @@ -4548,7 +4552,7 @@ static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
>  static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
>  			      struct mii_bus *bus, int sw_addr)
>  {
> -	if (sw_addr == 0)
> +	if (sw_addr == 0 || chip->info->dual_chip)
>  		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
>  	else if (chip->info->multi_chip)
>  		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;

And then select the dual chip ops here. That seems be to more in
keeping with the current code.

Thanks
	Andrew

  reply	other threads:[~2019-05-01 20:19 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-01 19:32 [RFC PATCH 0/5] net: dsa: POC support for mv88e6250 Rasmus Villemoes
2019-05-01 19:32 ` [RFC PATCH 1/5] net: dsa: mv88e6xxx: introduce support for two chips using direct smi addressing Rasmus Villemoes
2019-05-01 20:19   ` Andrew Lunn [this message]
2019-05-08  7:57     ` Rasmus Villemoes
2019-05-08 11:47       ` Andrew Lunn
2019-05-08 13:41         ` Vivien Didelot
2019-05-01 19:32 ` [RFC PATCH 2/5] net: dsa: mv88e6xxx: rename smi read/write functions Rasmus Villemoes
2019-05-03 21:57   ` Vivien Didelot
2019-05-06  5:57     ` Rasmus Villemoes
2019-05-06 14:51       ` Vivien Didelot
2019-05-01 19:32 ` [RFC PATCH 3/5] net: dsa: prepare mv88e6xxx_g1_atu_op() for the mv88e6250 Rasmus Villemoes
2019-05-01 20:22   ` Andrew Lunn
2019-05-01 19:32 ` [RFC PATCH 4/5] net: dsa: implement vtu_getnext and vtu_loadpurge for mv88e6250 Rasmus Villemoes
2019-05-01 20:25   ` Andrew Lunn
2019-05-01 19:32 ` [RFC PATCH 5/5] net: dsa: add support " Rasmus Villemoes
2019-05-01 20:29   ` Andrew Lunn
2019-05-24  9:00 ` [PATCH v2 0/5] net: dsa: " Rasmus Villemoes
2019-05-24  9:00   ` [PATCH v2 1/5] net: dsa: mv88e6xxx: introduce support for two chips using direct smi addressing Rasmus Villemoes
2019-05-24 14:13     ` Andrew Lunn
2019-05-24 17:54     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 2/5] net: dsa: prepare mv88e6xxx_g1_atu_op() for the mv88e6250 Rasmus Villemoes
2019-05-24 17:57     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 3/5] net: dsa: implement vtu_getnext and vtu_loadpurge for mv88e6250 Rasmus Villemoes
2019-05-24 18:02     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 4/5] net: dsa: mv88e6xxx: implement watchdog_ops " Rasmus Villemoes
2019-05-24 14:20     ` Andrew Lunn
2019-05-24 18:05     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 5/5] net: dsa: add support " Rasmus Villemoes
2019-05-24 14:27     ` Andrew Lunn
2019-06-03  8:52       ` Rasmus Villemoes
2019-06-03 12:45         ` Andrew Lunn
2019-05-24 18:11     ` Vivien Didelot

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