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From: Mark Brown <broonie@kernel.org>
To: Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Timo Alho <talho@nvidia.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	Krishna Yarlagadda <kyarlagadda@nvidia.com>,
	Laxman Dewangan <ldewangan@nvidia.com>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH V3 3/9] spi: add SPI_LSBYTE_FIRST mode
Date: Mon, 6 May 2019 13:49:16 +0900	[thread overview]
Message-ID: <20190506044916.GO14916@sirena.org.uk> (raw)
In-Reply-To: <BYAPR12MB33989D8DCEFCDE5DB76429E7C23F0@BYAPR12MB3398.namprd12.prod.outlook.com>

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On Sat, Apr 27, 2019 at 12:32:58AM +0000, Sowjanya Komatineni wrote:
> > On Mon, Apr 15, 2019 at 02:30:28PM -0700, Sowjanya Komatineni wrote:

> > This is byte ordering as opposed to bit ordering which the core
> > already supports.  Do you have any examples of devices that need
> > this or is it just being added for completeness?  If devices are
> > going to rely on this we probably need emulation > support in the
> > core I guess given that this is a pretty unusual controller feature.

> Current upstream platforms have no specific device requirement but
> added this feature as Tegra support it for specific requirements of
> some slaves.

Do we have any examples of such devices?  In any case I think the main
thing here would be a software implementation of the feature so that
drivers can use it sensibly - at the minute they'd have to provide code
to work without the feature anyway and it seems like a relatively small
optimization for most things.

> [Changed mail client message format word wrap limit to 74 columns]

It's not working, and it's also mangling quoted sections of the mail
too.

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  reply	other threads:[~2019-05-06  7:37 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-15 21:30 [PATCH V3 0/9] bug fixes and more features to Tegra SPI Sowjanya Komatineni
2019-04-15 21:30 ` [PATCH V3 1/9] spi: tegra114: fix PIO transfer Sowjanya Komatineni
2019-04-16 16:32   ` Applied "spi: tegra114: fix PIO transfer" to the spi tree Mark Brown
2019-04-29 21:42     ` Sowjanya Komatineni
2019-05-02  2:42       ` Mark Brown
2019-04-15 21:30 ` [PATCH V3 2/9] spi: expand mode support Sowjanya Komatineni
2019-04-18 10:26   ` Applied "spi: expand mode support" to the spi tree Mark Brown
2019-05-02  2:19   ` Mark Brown
2019-04-15 21:30 ` [PATCH V3 3/9] spi: add SPI_LSBYTE_FIRST mode Sowjanya Komatineni
2019-04-19 15:22   ` Mark Brown
2019-04-27  0:32     ` Sowjanya Komatineni
2019-05-06  4:49       ` Mark Brown [this message]
2019-04-15 21:30 ` [PATCH V3 4/9] spi: tegra114: add support for Tegra SPI LSBYTE_FIRST Sowjanya Komatineni
2019-04-15 21:30 ` [PATCH V3 5/9] spi: export spi core function spi_set_cs Sowjanya Komatineni
2019-04-19 15:18   ` Mark Brown
2019-04-29 22:02     ` Sowjanya Komatineni
2019-05-06  4:44       ` Mark Brown
2019-05-10 18:53         ` Sowjanya Komatineni
2019-05-12  3:12           ` Mark Brown
2019-04-15 21:30 ` [PATCH V3 6/9] spi: tegra114: add support for gpio based CS Sowjanya Komatineni
2019-04-15 21:30 ` [PATCH V3 7/9] spi: tegra114: add support for hw based cs Sowjanya Komatineni
2019-04-15 21:30 ` [PATCH V3 8/9] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
2019-04-15 21:30 ` [PATCH V3 9/9] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni

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