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From: Vivien Didelot <vivien.didelot@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Florian Fainelli <f.fainelli@gmail.com>
Subject: Re: [RFC PATCH 1/5] net: dsa: mv88e6xxx: introduce support for two chips using direct smi addressing
Date: Wed, 8 May 2019 09:41:32 -0400	[thread overview]
Message-ID: <20190508094132.GB13389@t480s.localdomain> (raw)
In-Reply-To: <20190508114715.GB30557@lunn.ch>

Hi Rasmus,

On Wed, 8 May 2019 13:47:15 +0200, Andrew Lunn <andrew@lunn.ch> wrote:
> > > 
> > > This works, but i think i prefer adding mv88e6xxx_smi_dual_chip_write,
> > > mv88e6xxx_smi_dual_chip_read, and create a
> > > mv88e6xxx_smi_single_chip_ops.
> > 
> > Now that Vivien's "net: dsa: mv88e6xxx: refine SMI support" is in
> > master, do you still prefer introducing a third bus_ops structure
> > (mv88e6xxx_smi_dual_direct_ops ?), or would the approach of adding
> > chip->sw_addr in the smi_direct_{read/write} functions be ok (which
> > would then require changing the indirect callers to pass 0 instead of
> > chip->swaddr).
> 
> I would still prefer a new bus_ops.

Even though those are direct read and write operations, having 3
mv88e6xxx_bus_ops structures will make it clear that there are 3 ways
for accessible the internal switch registers through SMI, depending
on the Marvell chip model.  So I would prefer a third ops as well.

Thanks,
Vivien

  reply	other threads:[~2019-05-08 13:41 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-01 19:32 [RFC PATCH 0/5] net: dsa: POC support for mv88e6250 Rasmus Villemoes
2019-05-01 19:32 ` [RFC PATCH 1/5] net: dsa: mv88e6xxx: introduce support for two chips using direct smi addressing Rasmus Villemoes
2019-05-01 20:19   ` Andrew Lunn
2019-05-08  7:57     ` Rasmus Villemoes
2019-05-08 11:47       ` Andrew Lunn
2019-05-08 13:41         ` Vivien Didelot [this message]
2019-05-01 19:32 ` [RFC PATCH 2/5] net: dsa: mv88e6xxx: rename smi read/write functions Rasmus Villemoes
2019-05-03 21:57   ` Vivien Didelot
2019-05-06  5:57     ` Rasmus Villemoes
2019-05-06 14:51       ` Vivien Didelot
2019-05-01 19:32 ` [RFC PATCH 3/5] net: dsa: prepare mv88e6xxx_g1_atu_op() for the mv88e6250 Rasmus Villemoes
2019-05-01 20:22   ` Andrew Lunn
2019-05-01 19:32 ` [RFC PATCH 4/5] net: dsa: implement vtu_getnext and vtu_loadpurge for mv88e6250 Rasmus Villemoes
2019-05-01 20:25   ` Andrew Lunn
2019-05-01 19:32 ` [RFC PATCH 5/5] net: dsa: add support " Rasmus Villemoes
2019-05-01 20:29   ` Andrew Lunn
2019-05-24  9:00 ` [PATCH v2 0/5] net: dsa: " Rasmus Villemoes
2019-05-24  9:00   ` [PATCH v2 1/5] net: dsa: mv88e6xxx: introduce support for two chips using direct smi addressing Rasmus Villemoes
2019-05-24 14:13     ` Andrew Lunn
2019-05-24 17:54     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 2/5] net: dsa: prepare mv88e6xxx_g1_atu_op() for the mv88e6250 Rasmus Villemoes
2019-05-24 17:57     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 3/5] net: dsa: implement vtu_getnext and vtu_loadpurge for mv88e6250 Rasmus Villemoes
2019-05-24 18:02     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 4/5] net: dsa: mv88e6xxx: implement watchdog_ops " Rasmus Villemoes
2019-05-24 14:20     ` Andrew Lunn
2019-05-24 18:05     ` Vivien Didelot
2019-05-24  9:00   ` [PATCH v2 5/5] net: dsa: add support " Rasmus Villemoes
2019-05-24 14:27     ` Andrew Lunn
2019-06-03  8:52       ` Rasmus Villemoes
2019-06-03 12:45         ` Andrew Lunn
2019-05-24 18:11     ` Vivien Didelot

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