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* [PATCH] perf vendor events amd: add L3 cache events for Family 17h
@ 2019-05-22 22:28 Phillips, Kim
  0 siblings, 0 replies; only message in thread
From: Phillips, Kim @ 2019-05-22 22:28 UTC (permalink / raw)
  To: linux-kernel
  Cc: Phillips, Kim, Natarajan, Janakarajan, Peter Zijlstra,
	Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin,
	Andi Kleen, Jiri Olsa, Namhyung Kim, Borislav Petkov,
	Martin Liška, Thomas Richter, Hendrik Brueckner

From: Kim Phillips <kim.phillips@amd.com>

Allow users to symbolically specify L3 events for Family 17h processors
using the existing AMD Uncore driver.

Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Borislav Petkov <bp@suse.de>
Cc: "Martin Liška" <mliska@suse.cz>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Cc: Hendrik Brueckner <brueckner@linux.ibm.com>
Cc: linux-kernel@vger.kernel.org
---
 .../perf/pmu-events/arch/x86/amdfam17h/cache.json  | 14 ++++++++++++++
 tools/perf/pmu-events/jevents.c                    |  1 +
 2 files changed, 15 insertions(+)

diff --git a/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json b/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json
index 5d9f9e172743..e38adf8927ae 100644
--- a/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json
+++ b/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json
@@ -311,5 +311,19 @@
     "BriefDescription": "Total cycles spent with one or more fill requests in flight from L2.",
     "PublicDescription": "Total cycles spent with one or more fill requests in flight from L2.",
     "UMask": "0x1"
+  },
+  {
+    "EventName": "l3_request_g1.caching_l3_cache_accesses",
+    "EventCode": "0x01",
+    "BriefDescription": "L3 cache accesses",
+    "UMask": "0x80",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_comb_clstr_state.request_miss",
+    "EventCode": "0x06",
+    "BriefDescription": "L3 cache misses",
+    "UMask": "0x01",
+    "Unit": "L3PMC"
   }
 ]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 58f77fd0f59f..fb2cc98c5b0e 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -236,6 +236,7 @@ static struct map {
 	{ "CPU-M-CF", "cpum_cf" },
 	{ "CPU-M-SF", "cpum_sf" },
 	{ "UPI LL", "uncore_upi" },
+	{ "L3PMC", "amd_l3" },
 	{}
 };
 
-- 
2.21.0

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