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From: Fabio Estevam <festevam@gmail.com>
To: srinivas.kandagatla@linaro.org
Cc: linux-kernel@vger.kernel.org, shawnguo@kernel.org,
	linux-imx@nxp.com, kernel@pengutronix.de,
	Fabio Estevam <festevam@gmail.com>
Subject: [PATCH] nvmem: Broaden the selection of NVMEM_SNVS_LPGPR
Date: Wed, 22 May 2019 21:15:02 -0300	[thread overview]
Message-ID: <20190523001502.20105-1-festevam@gmail.com> (raw)

The SNVS LPGR IP block is also found on other i.MX SoCs that
are not covered by the current SOC_IMX6 || SOC_IMX7D logic.

One example is the i.MX7ULP.

To avoid keep expanding the SoC logic selection, make it broader
by using the more generic ARCH_MXC symbol instead.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 drivers/nvmem/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index afa4335e0a20..700c262a117c 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -188,7 +188,7 @@ config MESON_MX_EFUSE
 
 config NVMEM_SNVS_LPGPR
 	tristate "Support for Low Power General Purpose Register"
-	depends on SOC_IMX6 || SOC_IMX7D || COMPILE_TEST
+	depends on ARCH_MXC || COMPILE_TEST
 	help
 	  This is a driver for Low Power General Purpose Register (LPGPR) available on
 	  i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
-- 
2.17.1


             reply	other threads:[~2019-05-23  0:15 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-23  0:15 Fabio Estevam [this message]
2019-05-23  8:52 ` Srinivas Kandagatla

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