LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: Sudeep Holla <sudeep.holla@arm.com>
To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org
Cc: Sudeep Holla <sudeep.holla@arm.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Christoffer Dall <christoffer.dall@arm.com>,
	Marc Zyngier <marc.zyngier@arm.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Pouloze <suzuki.poulose@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	Julien Thierry <julien.thierry@arm.com>
Subject: [PATCH v2 02/15] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems
Date: Thu, 23 May 2019 11:34:49 +0100	[thread overview]
Message-ID: <20190523103502.25925-3-sudeep.holla@arm.com> (raw)
In-Reply-To: <20190523103502.25925-1-sudeep.holla@arm.com>

It's not entirely clear for the binding document that the only way to
express ARM SPE affined to a subset of CPUs on a heterogeneous systems
is through the use of PPI partitions available in the interrupt
controller bindings.

Let's make it clear.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 Documentation/devicetree/bindings/arm/spe-pmu.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt
index 93372f2a7df9..4f4815800f6e 100644
--- a/Documentation/devicetree/bindings/arm/spe-pmu.txt
+++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt
@@ -9,8 +9,9 @@ performance sample data using an in-memory trace buffer.
 	       "arm,statistical-profiling-extension-v1"
 
 - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
-               SPE is only supported on a subset of the CPUs, please consult
-	       the arm,gic-v3 binding for details on describing a PPI partition.
+               SPE is only supported on a subset of the CPUs, a PPI partition
+	       described in the arm,gic-v3 binding must be used to describe
+	       the set of CPUs this interrupt is affine to.
 
 ** Example:
 
-- 
2.17.1


  parent reply	other threads:[~2019-05-23 10:35 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-23 10:34 [PATCH 00/15] arm64: KVM: add SPE profiling support for guest Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 01/15] KVM: arm64: add {read,write}_sysreg_elx_s versions for new registers Sudeep Holla
2019-05-23 10:34 ` Sudeep Holla [this message]
2019-05-23 10:34 ` [PATCH v2 03/15] arm64: KVM: reset E2PB correctly in MDCR_EL2 when exiting the guest(VHE) Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 04/15] arm64: KVM: define SPE data structure for each vcpu Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 05/15] arm64: KVM: add access handler for SPE system registers Sudeep Holla
2019-05-24 11:36   ` Julien Thierry
2019-05-24 14:12     ` Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 06/15] arm64: KVM/VHE: enable the use PMSCR_EL12 on VHE systems Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 07/15] arm64: KVM: split debug save restore across vm/traps activation Sudeep Holla
2019-05-28  8:18   ` Julien Thierry
2019-05-23 10:34 ` [PATCH v2 08/15] arm64: KVM/debug: drop pmscr_el1 and use sys_regs[PMSCR_EL1] in kvm_cpu_context Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 09/15] arm64: KVM: add support to save/restore SPE profiling buffer controls Sudeep Holla
2019-05-29  8:26   ` Julien Thierry
2019-05-23 10:34 ` [PATCH v2 10/15] arm64: KVM: enable conditional save/restore full " Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 11/15] arm64: KVM/debug: trap all accesses to SPE controls at EL1 Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 12/15] KVM: arm64: add a new vcpu device control group for SPEv1 Sudeep Holla
2019-05-24 10:37   ` Marc Zyngier
2019-05-24 11:21     ` Sudeep Holla
2019-05-24 12:07       ` Marc Zyngier
2019-05-23 10:35 ` [PATCH v2 13/15] KVM: arm64: enable SPE support Sudeep Holla
2019-05-23 10:35 ` [PATCH v2 14/15][KVMTOOL] update_headers: Sync kvm UAPI headers with linux v5.2-rc1 Sudeep Holla
2019-05-23 10:35 ` [PATCH v2 15/15][KVMTOOL] kvm: add a vcpu feature for SPEv1 support Sudeep Holla

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190523103502.25925-3-sudeep.holla@arm.com \
    --to=sudeep.holla@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=christoffer.dall@arm.com \
    --cc=james.morse@arm.com \
    --cc=julien.thierry@arm.com \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=marc.zyngier@arm.com \
    --cc=suzuki.poulose@arm.com \
    --cc=will.deacon@arm.com \
    --subject='Re: [PATCH v2 02/15] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).