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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id i101sm6691470pje.9.2019.05.25.11.16.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 11:16:46 -0700 (PDT) Date: Sat, 25 May 2019 11:17:14 -0700 From: Bjorn Andersson To: Sai Prakash Ranjan Cc: Andy Gross , David Brown , Stephen Boyd , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 2/4] soc: qcom: Add AOSS QMP driver Message-ID: <20190525181714.GI2085@tuxbook-pro> References: <20190501043734.26706-1-bjorn.andersson@linaro.org> <20190501043734.26706-3-bjorn.andersson@linaro.org> <3d2c61ca-b91b-fdc7-7837-af6a3b71af7e@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3d2c61ca-b91b-fdc7-7837-af6a3b71af7e@codeaurora.org> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat 25 May 10:53 PDT 2019, Sai Prakash Ranjan wrote: > On 5/1/2019 10:07 AM, Bjorn Andersson wrote: > > The Always On Subsystem (AOSS) Qualcomm Messaging Protocol (QMP) driver > > is used to communicate with the AOSS for certain side-channel requests, > > that are not available through the RPMh interface. > > > > The communication is a very simple synchronous mechanism of messages > > being written in message RAM and a doorbell in the AOSS is rung. As the > > AOSS has processed the message length is cleared and an interrupt is > > fired by the AOSS as acknowledgment. > > > > The driver exposes the QDSS clock as a clock and the low-power state > > associated with the remoteprocs in the system as a set of power-domains. > > > > Signed-off-by: Bjorn Andersson > > --- > > > > Changes since v6: > > - Squash the pd into the same driver as the communication, to simplify > > the interaction. > > - Representing the QDSS clocks as a clock/power domain turns out to > > cascade into a request to make all Coresight drivers have a secondary > > compatible to replace the required bus clock with a required power > > domain. So in v7 this is exposed as a clock instead. > > - Some error checking updates, as reported by Doug. > > > > Thanks for the patch Bjorn. > Tested the QDSS functionality on SDM845 based Cheza board with this > change and it works just fine. > > Tested-by: Sai Prakash Ranjan Thanks for the confirmation Sai! Regards, Bjorn