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From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@kernel.org, mingo@redhat.com, linux-kernel@vger.kernel.org,
	tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
	alexander.shishkin@linux.intel.com, ak@linux.intel.com
Subject: Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters
Date: Wed, 29 May 2019 10:14:57 +0200	[thread overview]
Message-ID: <20190529081457.GD2623@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20190521214055.31060-3-kan.liang@linux.intel.com>


On Tue, May 28, 2019 at 02:20:53PM -0400, Liang, Kan wrote:
> On 5/28/2019 8:05 AM, Peter Zijlstra wrote:
> > On Tue, May 21, 2019 at 02:40:48PM -0700, kan.liang@linux.intel.com wrote:

> @@ -2155,9 +2155,19 @@ static void intel_pmu_disable_event(struct perf_event *event)
>  		return;
>  	}
>  
> -	cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
> -	cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
> -	cpuc->intel_cp_status &= ~(1ull << hwc->idx);
> +	__clear_bit(hwc->idx, cpuc->enabled_events);
> +
> +	/*
> +	 * When any other slots sharing event is still enabled,
> +	 * cancel the disabling.
> +	 */
> +	if (is_any_slots_idx(hwc->idx) &&
> +	    (*(u64 *)&cpuc->enabled_events & INTEL_PMC_MSK_ANY_SLOTS))
> +		return;
> +
> +	cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->reg_idx);
> +	cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->reg_idx);
> +	cpuc->intel_cp_status &= ~(1ull << hwc->reg_idx);
>  
>  	if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
>  		intel_pmu_disable_fixed(hwc);

> @@ -2242,18 +2252,19 @@ static void intel_pmu_enable_event(struct perf_event *event)
>  	}
>  
>  	if (event->attr.exclude_host)
> -		cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
> +		cpuc->intel_ctrl_guest_mask |= (1ull << hwc->reg_idx);
>  	if (event->attr.exclude_guest)
> -		cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
> +		cpuc->intel_ctrl_host_mask |= (1ull << hwc->reg_idx);
>  
>  	if (unlikely(event_is_checkpointed(event)))
> -		cpuc->intel_cp_status |= (1ull << hwc->idx);
> +		cpuc->intel_cp_status |= (1ull << hwc->reg_idx);
>  
>  	if (unlikely(event->attr.precise_ip))
>  		intel_pmu_pebs_enable(event);
>  
>  	if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
> -		intel_pmu_enable_fixed(event);
> +		if (!__test_and_set_bit(hwc->idx, cpuc->enabled_events))
> +			intel_pmu_enable_fixed(event);
>  		return;
>  	}
>  
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index 7ae2912f16de..dd6c86a758f7 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -203,6 +203,7 @@ struct cpu_hw_events {
>  	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
>  	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
>  	int			enabled;
> +	unsigned long		enabled_events[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
>  
>  	int			n_events; /* the # of events in the below arrays */
>  	int			n_added;  /* the # last events in the below arrays;

> > Also, why do we need that whole enabled_events[] array. Do we really not
> > have that information elsewhere?
> 
> No. We don't have a case that several events share a counter at the same
> time. We don't need to check if other events are enabled when we try to
> disable a counter. So we don't save such information.
> But we have to do it for metrics events.

So you have x86_pmu.disable() clear the bit, and x86_pmu.enable() set
the bit, and then, if you look at arch/x86/events/core.c that doesn't
look redundant?

That is, explain to me how exactly this new enabled_events[] is different
from active_mask[].

  parent reply	other threads:[~2019-05-29  8:15 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-21 21:40 [PATCH 0/9] TopDown metrics support for Icelake kan.liang
2019-05-21 21:40 ` [PATCH 1/9] perf/core: Support a REMOVE transaction kan.liang
2019-05-21 21:40 ` [PATCH 2/9] perf/x86/intel: Basic support for metrics counters kan.liang
2019-05-28 12:05   ` Peter Zijlstra
2019-05-28 18:20     ` Liang, Kan
2019-05-28 12:15   ` Peter Zijlstra
2019-05-28 18:21     ` Liang, Kan
2019-05-29  7:28       ` Peter Zijlstra
2019-05-29 14:40         ` Liang, Kan
2019-05-29 16:46           ` Peter Zijlstra
2019-05-29  8:14   ` Peter Zijlstra [this message]
2019-05-21 21:40 ` [PATCH 3/9] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-05-28 12:20   ` Peter Zijlstra
2019-05-28 18:22     ` Liang, Kan
2019-05-21 21:40 ` [PATCH 4/9] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-05-28 12:43   ` Peter Zijlstra
2019-05-28 18:23     ` Liang, Kan
2019-05-29  7:30       ` Peter Zijlstra
2019-05-28 12:53   ` Peter Zijlstra
2019-05-28 12:56   ` Peter Zijlstra
2019-05-28 13:32     ` Peter Zijlstra
2019-05-28 13:30   ` Peter Zijlstra
2019-05-28 18:24     ` Liang, Kan
2019-05-29  7:34       ` Peter Zijlstra
2019-05-29 14:41         ` Liang, Kan
2019-05-28 13:43   ` Peter Zijlstra
2019-05-28 18:24     ` Liang, Kan
2019-05-29  7:54       ` Peter Zijlstra
2019-05-29 14:42         ` Liang, Kan
2019-05-29 16:58           ` Peter Zijlstra
2019-06-04 20:39             ` Liang, Kan
2019-05-28 13:48   ` Peter Zijlstra
2019-05-28 18:24     ` Liang, Kan
2019-05-29  7:57       ` Peter Zijlstra
2019-05-29 14:42         ` Liang, Kan
2019-05-21 21:40 ` [PATCH 5/9] perf/x86/intel: Set correct weight for TopDown metrics events kan.liang
2019-05-28 13:50   ` Peter Zijlstra
2019-05-21 21:40 ` [PATCH 6/9] perf/x86/intel: Export new TopDown metrics events for Icelake kan.liang
2019-05-21 21:40 ` [PATCH 7/9] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-05-28 13:52   ` Peter Zijlstra
2019-05-28 18:25     ` Liang, Kan
2019-05-29  7:58       ` Peter Zijlstra
2019-05-21 21:40 ` [PATCH 8/9] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-05-21 21:40 ` [PATCH 9/9] perf, tools: Add documentation for topdown metrics kan.liang

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