From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16E3CC28CC5 for ; Wed, 5 Jun 2019 17:34:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E8DBE20872 for ; Wed, 5 Jun 2019 17:34:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726761AbfFERez (ORCPT ); Wed, 5 Jun 2019 13:34:55 -0400 Received: from foss.arm.com ([217.140.101.70]:35510 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726240AbfFERev (ORCPT ); Wed, 5 Jun 2019 13:34:51 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 36C0E374; Wed, 5 Jun 2019 10:34:51 -0700 (PDT) Received: from e107155-lin (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F39383F5AF; Wed, 5 Jun 2019 10:34:48 -0700 (PDT) Date: Wed, 5 Jun 2019 18:34:42 +0100 From: Sudeep Holla To: Sricharan R Cc: robh+dt@kernel.org, sboyd@kernel.org, linus.walleij@linaro.org, agross@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sudeep Holla Subject: Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support Message-ID: <20190605173441.GA9903@e107155-lin> References: <1559755738-28643-1-git-send-email-sricharan@codeaurora.org> <1559755738-28643-6-git-send-email-sricharan@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1559755738-28643-6-git-send-email-sricharan@codeaurora.org> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote: > Add initial device tree support for the Qualcomm IPQ6018 SoC and > CP01 evaluation board. > > Signed-off-by: Sricharan R > Signed-off-by: Abhishek Sahu > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 ++++ > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 +++++++++++++++++++++++++++ > 3 files changed, 267 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi > [...] > + > + CPU3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x3>; > + next-level-cache = <&L2_0>; > + }; > + > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <0x2>; > + }; > + }; > + > + pmuv8: pmu { > + compatible = "arm,armv8-pmuv3"; We know these are Cortex-A53s, why not update these accordingly ? -- Regards, Sudeep