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From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Sayali Lokhande <sayalil@codeaurora.org>
Cc: adrian.hunter@intel.com, robh+dt@kernel.org,
	ulf.hansson@linaro.org, asutoshd@codeaurora.org,
	stummala@codeaurora.org, ppvk@codeaurora.org,
	rampraka@codeaurora.org, vbadigan@codeaurora.org,
	sboyd@kernel.org, georgi.djakov@linaro.org, mka@chromium.org,
	linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	agross@kernel.org, linux-mmc-owner@vger.kernel.org
Subject: Re: [PATCH RFC] mmc: sdhci-msm: Toggle fifo write clk after ungating sdcc clk
Date: Thu, 20 Feb 2020 07:44:34 -0800	[thread overview]
Message-ID: <20200220154434.GB955802@ripper> (raw)
In-Reply-To: <1582190446-4778-2-git-send-email-sayalil@codeaurora.org>

On Thu 20 Feb 01:20 PST 2020, Sayali Lokhande wrote:

> From: Ram Prakash Gupta <rampraka@codeaurora.org>
> 
> During GCC level clock gating of MCLK, the async FIFO
> gets into some hang condition, such that for the next
> transfer after MCLK ungating, first bit of CMD response
> doesn't get written in to the FIFO. This cause the CPSM
> to hang eventually leading to SW timeout.

Does this always happen, on what platforms does this happen? How does
this manifest itself? Can you please elaborate.

> 
> To fix the issue, toggle the FIFO write clock after
> MCLK ungated to get the FIFO pointers and flags to
> valid states.
> 
> Change-Id: Ibef2d1d283ac0b6983c609a4abc98bc574d31fa6

Please drop the Change-Id and please add

Cc: stable@vger.kernel.org

If this is a bug fix that should be backported to e.g. 5.4.

> Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
> Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
> ---
>  drivers/mmc/host/sdhci-msm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index c3a160c..eaa3e95 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -127,6 +127,8 @@
>  #define CQHCI_VENDOR_CFG1	0xA00
>  #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN	(0x3 << 13)
>  
> +#define RCLK_TOGGLE 0x2

Please use BIT(1) instead.

> +
>  struct sdhci_msm_offset {
>  	u32 core_hc_mode;
>  	u32 core_mci_data_cnt;
> @@ -1554,6 +1556,43 @@ static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>  	sdhci_enable_clk(host, clk);
>  }
>  
> +/*
> + * After MCLK ugating, toggle the FIFO write clock to get
> + * the FIFO pointers and flags to valid state.
> + */
> +static void sdhci_msm_toggle_fifo_write_clk(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> +	const struct sdhci_msm_offset *msm_offset =
> +					msm_host->offset;

This doesn't look to be > 80 chars, please unwrap.

> +	struct mmc_card *card = host->mmc->card;
> +
> +	if (msm_host->tuning_done ||
> +			(card && card->ext_csd.strobe_support &&
> +			card->host->ios.enhanced_strobe)) {
> +		/*
> +		 * set HC_REG_DLL_CONFIG_3[1] to select MCLK as
> +		 * DLL input clock

You can shorten this to /* Select MCLK as DLL input clock */ if you make
the below readl/writel a little bit easier to read.

> +		 */
> +		writel_relaxed(((readl_relaxed(host->ioaddr +
> +			msm_offset->core_dll_config_3))
> +			| RCLK_TOGGLE), host->ioaddr +
> +			msm_offset->core_dll_config_3);

Please use a local variable and write this out as:
		val = readl(addr);
		val |= RCLK_TOGGLE;
		writel(val, addr);

> +		/* ensure above write as toggling same bit quickly */
> +		wmb();

This ensures ordering of writes, if you want to make sure the write has
hit the hardware before the delay perform a readl() on the address.

> +		udelay(2);
> +		/*
> +		 * clear HC_REG_DLL_CONFIG_3[1] to select RCLK as
> +		 * DLL input clock
> +		 */

		/* Select RCLK as DLL input clock */

> +		writel_relaxed(((readl_relaxed(host->ioaddr +
> +			msm_offset->core_dll_config_3))
> +			& ~RCLK_TOGGLE), host->ioaddr +
> +			msm_offset->core_dll_config_3);

Same as above, readl(); val &= ~RCLK_TOGGLE; writel(); will make this
easier on the eyes.

> +	}
> +}
> +
>  /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
>  static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>  {
> @@ -2149,6 +2188,10 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
>  				       msm_host->bulk_clks);
>  	if (ret)
>  		return ret;

An empty line please.

> +	if (host->mmc &&

Afaict host->mmc can't be NULL, can you please confirm that you need
this check.

> +			(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
> +		sdhci_msm_toggle_fifo_write_clk(host);
> +

Regards,
Bjorn

>  	/*
>  	 * Whenever core-clock is gated dynamically, it's needed to
>  	 * restore the SDR DLL settings when the clock is ungated.
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project

  reply	other threads:[~2020-02-20 15:45 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-20  9:20 [PATCH RFC] " Sayali Lokhande
2020-02-20  9:20 ` [PATCH RFC] mmc: sdhci-msm: " Sayali Lokhande
2020-02-20 15:44   ` Bjorn Andersson [this message]
2020-02-20 18:02   ` Stephen Boyd
2020-02-24 13:49   ` Veerabhadrarao Badiganti
2020-02-28  6:54     ` Sayali Lokhande
2020-02-20 15:51 ` [PATCH RFC] " Bjorn Andersson

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