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* [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB
@ 2020-03-03 17:11 Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy Bryan O'Donoghue
                   ` (18 more replies)
  0 siblings, 19 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue

V1:
This series enables the Primary and Secondary USB controllers on the
QCS404, associated PHYs, role-switching and DTS descriptions.

The series takes in a number of patches worked on by a number of people
over the past few years from downstream, through to previous upstream
submissions for both of these interfaces. Additional work has been done to
enable USB role-switching.

1. USB SS
   - extcon has been dropped in favour of gpio-usb-conn as discussed and
     agreed previously by Jorge, Bjorn, Stephen Boyd and Jack Pham [1].

   - Regulator API has been updated following suggestions from Bjorn.
   
   - Sanitzation of the DT compatible name - dropped "snps" entirely
     from the name - it made almost no sense to me and doesn't appear
     consistent with similar naming conventions for Snopsys based IP.

2. USB HS
   - Regulator API changes here.
   - Dropped "snps" from the namespace for similar reasons as above.
   - Dropped "28nm" from the namespace, looked superfluous.
   - Changed "High-Speed" to "Hi-Speed".
   - [2]

3. DWC3 Role switching
   - At the time usb-gpio-conn was discussed it was mentioned that
     role-switching was absent from the DWC3 driver.
   - John Stultz has some patches in-flight for that, that I've included in
     this series for completeness.
   - Adds my SoB to relevant patches.
   - Drops gerrit ChangeId.

4. DWC3 usb-gpio-conn
   Needs to be a child node of the DWC3 driver so some code and DT binding
   is required for that.

5. QCOM-DWC3
   Since we are role-switching with an external PMIC supplying VBUS we want
   to skip past toggling VBUS from QCOM-DWC3 controlled registers, so a
   patch is added to the qcom-dwc3 driver to do that.

References:

1: USB SS PHY for Qualcomm's QCS404
https://lwn.net/ml/devicetree/20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org/

2: Add Synopsys High-Speed USB PHY driver for Qualcomm SoCs
https://lore.kernel.org/linux-arm-msm/20181127100722.9993-3-shawn.guo@linaro.org/

https://www.spinics.net/lists/linux-usb/msg190003.html

V2:
- Fixes yaml error - Rob's YAML robot
- Exclusive control of reset in PHY drivers - Philipp Zabel

V3:
- Fixes typo generating YAML warning - Rob's YAML robot

V4:

https://lore.kernel.org/linux-arm-msm/20200122185610.131930-1-bryan.odonoghue@linaro.org/

- Churn names of PHYs - Rob Herring
  Rob questioned the name of the SuperSpeed PHY in V3.
  Looking at available data 

  usb-hs-28nm - There are two possible PHYs on 28nm litho node
		so it makes sense to name the PHY relating to its relevant
		litho node.

  usb-ss - This is not litho node dependent and is used on  multiple SoCs
	   and litho nodes.

- Drop default mode for role switching - Felipe Balbi
  Felipe asked if the default mode for role switching was
  required and the answer is no. It makes no difference
  becuase the USB ID pin ultimately dictates the mode of operation.

- Change "gpio_usb_connector" to "connector" - Rob
  This was a minor change in terms of DTS but, means I need to look for the
  DTS compatible string as opposed to a label given in the DTS.
  No matter what the name of the label, this is he right thing to do.

- Used IS_ENABLED() - Felipe
  The logic is the same but IS_ENABLED() is used now.

- Retained example of USB connector in dwc.txt - Rob, Felipe
  Rob pointed out adding the connector was redundant as the documentation
  already implies it.
  Felipe seemed in favour of I think adding the example.
  I've dropped the documentation of the connector and kept the example.
  https://lore.kernel.org/linux-arm-msm/20200122185610.131930-7-bryan.odonoghue@linaro.org/

- Added example of usb-role-switch in dwc3.txt - BOD
  
- Incorporated various inputs from Rob on DTS/YAML
  - Added required:
  - Added additionalProperties:
  - Renamed "phy" clock to "ahb"
  - maxItems dropped as indicated

V5:
- https://lkml.org/lkml/2020/2/6/913

- Adds a notifier to DWC3 - BOD
  This is done in order to allow propagation of role-switch events from the
  DWC3 core to an associated binding layer.

- Re-use the existent EXTCON VBUS power lane toggle logic - Jack Pham
  Jack flagged this for inclusion and as a result we need to make a
  small change to the qcom binding layer.

- Squash DTS changes - BOD
  I've squashed down some of the DTS changes to stop the patch count in
  this series going  up any further.

V6:
- https://lkml.org/lkml/2020/2/7/632

- Add RB Jack Pham patch # 11

- Fix a stale description in git log patch # 10

V7:
- https://lkml.org/lkml/2020/2/10/258

- Adds RB Rob Herring as indicated

- Updates the naming of the USB SS PHY for the particular SoC.
  The name of the driver is maintained, as previously mentioned, this
  IP appears to be in use on the 20nm and 28nm nodes. However taking
  Rob's feedback on the naming of the SoC specific bit the code being added
  is specified @ 28nm.
  If/when we come to add in 20nm for this IP we can add a new compatible
  for 20nm.
  Rob Herring

Bjorn Andersson (1):
  arm64: dts: qcom: qcs404: Add USB devices and PHYs

Bryan O'Donoghue (11):
  dt-bindings: usb: dwc3: Add a gpio-usb-connector example
  dt-bindings: usb: dwc3: Add a usb-role-switch to the example
  usb: dwc3: qcom: Add support for usb-conn-gpio connectors
  usb: dwc3: Add support for usb-conn-gpio connectors
  usb: dwc3: Add support for a role-switch notifier
  usb: dwc3: qcom: Enable gpio-usb-conn based role-switching
  arm64: dts: qcom: qcs404-evb: Define VBUS pins
  arm64: dts: qcom: qcs404-evb: Define USB ID pin
  arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator
  arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage
  arm64: dts: qcom: qcs404-evb: Enable USB controllers

Jorge Ramirez-Ortiz (3):
  dt-bindings: phy: remove qcom-dwc3-usb-phy
  dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
  phy: qualcomm: usb: Add SuperSpeed PHY driver

Shawn Guo (1):
  phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver

Sriharsha Allenki (1):
  dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding

Yu Chen (1):
  usb: dwc3: Registering a role switch in the DRD code.

 .../bindings/phy/qcom,usb-hs-28nm.yaml        |  90 ++++
 .../devicetree/bindings/phy/qcom,usb-ss.yaml  |  83 ++++
 .../bindings/phy/qcom-dwc3-usb-phy.txt        |  37 --
 .../devicetree/bindings/usb/dwc3.txt          |   9 +
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi      |  90 +++-
 arch/arm64/boot/dts/qcom/qcs404.dtsi          | 100 +++++
 drivers/phy/qualcomm/Kconfig                  |  20 +
 drivers/phy/qualcomm/Makefile                 |   2 +
 drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c   | 415 ++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-usb-ss.c        | 246 +++++++++++
 drivers/usb/dwc3/core.h                       |  22 +
 drivers/usb/dwc3/drd.c                        | 119 ++++-
 drivers/usb/dwc3/dwc3-qcom.c                  |  31 +-
 13 files changed, 1223 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
 delete mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
 create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
 create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c

-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 02/18] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Bryan O'Donoghue
                   ` (17 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
	Bryan O'Donoghue

From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

This binding is not used by any driver.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 .../bindings/phy/qcom-dwc3-usb-phy.txt        | 37 -------------------
 1 file changed, 37 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
deleted file mode 100644
index a1697c27aecd..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-Qualcomm DWC3 HS AND SS PHY CONTROLLER
---------------------------------------
-
-DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
-controllers.  Each DWC3 PHY controller should have its own node.
-
-Required properties:
-- compatible: should contain one of the following:
-	- "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
-	- "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
-- reg: offset and length of the DWC3 PHY controller register set
-- #phy-cells: must be zero
-- clocks: a list of phandles and clock-specifier pairs, one for each entry in
-  clock-names.
-- clock-names: Should contain "ref" for the PHY reference clock
-
-Optional clocks:
-  "xo"		External reference clock
-
-Example:
-		phy@100f8800 {
-			compatible = "qcom,dwc3-hs-usb-phy";
-			reg = <0x100f8800 0x30>;
-			clocks = <&gcc USB30_0_UTMI_CLK>;
-			clock-names = "ref";
-			#phy-cells = <0>;
-
-		};
-
-		phy@100f8830 {
-			compatible = "qcom,dwc3-ss-usb-phy";
-			reg = <0x100f8830 0x30>;
-			clocks = <&gcc USB30_0_MASTER_CLK>;
-			clock-names = "ref";
-			#phy-cells = <0>;
-
-		};
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 02/18] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 03/18] phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver Bryan O'Donoghue
                   ` (16 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Sriharsha Allenki, Anu Ramanathan, Shawn Guo,
	Andy Gross, Kishon Vijay Abraham I, Rob Herring, Mark Rutland,
	Jorge Ramirez-Ortiz, devicetree, Bryan O'Donoghue

From: Sriharsha Allenki <sallenki@codeaurora.org>

Adds bindings for Qualcomm's 28 nm USB PHY supporting Low-Speed, Full-Speed
and Hi-Speed USB connectivity on Qualcomm chipsets.

[bod: Converted to YAML. Changed name dropping snps, 28nm components]

Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 .../bindings/phy/qcom,usb-hs-28nm.yaml        | 90 +++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml

diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
new file mode 100644
index 000000000000..ca6a0836b53c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
+
+maintainers:
+  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+  Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
+
+properties:
+  compatible:
+    enum:
+      - qcom,usb-hs-28nm-femtophy
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+  clocks:
+    items:
+      - description: rpmcc ref clock
+      - description: PHY AHB clock
+      - description: Rentention clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: ahb
+      - const: sleep
+
+  resets:
+    items:
+      - description: PHY core reset
+      - description: POR reset
+
+  reset-names:
+    items:
+      - const: phy
+      - const: por
+
+  vdd-supply:
+    description: phandle to the regulator VDD supply node.
+
+  vdda1p8-supply:
+    description: phandle to the regulator 1.8V supply node.
+
+  vdda3p3-supply:
+    description: phandle to the regulator 3.3V supply node.
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - vdd-supply
+  - vdda1p8-supply
+  - vdda3p3-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+    #include <dt-bindings/clock/qcom,rpmcc.h>
+    usb2_phy_prim: phy@7a000 {
+        compatible = "qcom,usb-hs-28nm-femtophy";
+        reg = <0x0007a000 0x200>;
+        #phy-cells = <0>;
+        clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+                 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+                 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+        clock-names = "ref", "ahb", "sleep";
+        resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+                 <&gcc GCC_USB2A_PHY_BCR>;
+        reset-names = "phy", "por";
+        vdd-supply = <&vreg_l4_1p2>;
+        vdda1p8-supply = <&vreg_l5_1p8>;
+        vdda3p3-supply = <&vreg_l12_3p3>;
+    };
+...
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 03/18] phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 02/18] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Bryan O'Donoghue
                   ` (15 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Shawn Guo, Andy Gross, Kishon Vijay Abraham I,
	Philipp Zabel, Jorge Ramirez-Ortiz, Bryan O'Donoghue

From: Shawn Guo <shawn.guo@linaro.org>

Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually
paired with Synopsys DWC3 USB controllers on Qualcomm SoCs.

The PHY can come in two flavours femtoPHY or picoPHY. This commit adds
support for the femtoPHY with the possibility of extending to the picoPHY
with additional future commits. Both PHYs are on a 28 nanometer process
node.

[bod: Updated qcom_snps_hsphy_set_mode to match new method signature
      Added disjunct on mode > 0
      Removed regulator_set_voltage() in favour of setting floor in dts
      Removed 'snps' and from driver name
      Extended commit log to mention femtoPHY and picoPHY for future
      reference.]

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 drivers/phy/qualcomm/Kconfig                |  11 +
 drivers/phy/qualcomm/Makefile               |   1 +
 drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c | 415 ++++++++++++++++++++
 3 files changed, 427 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index e46824da29f6..9c56a7216f72 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -91,3 +91,14 @@ config PHY_QCOM_USB_HSIC
 	select GENERIC_PHY
 	help
 	  Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
+
+config PHY_QCOM_USB_HS_28NM
+	tristate "Qualcomm 28nm High-Speed PHY"
+	depends on ARCH_QCOM || COMPILE_TEST
+	depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
+	select GENERIC_PHY
+	help
+	  Enable this to support the Qualcomm Synopsys DesignWare Core 28nm
+	  High-Speed PHY driver. This driver supports the Hi-Speed PHY which
+	  is usually paired with either the ChipIdea or Synopsys DWC3 USB
+	  IPs on MSM SOCs.
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index 283251d6a5d9..a4dab5329de0 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM)		+= phy-qcom-ufs-qmp-14nm.o
 obj-$(CONFIG_PHY_QCOM_UFS_20NM)		+= phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o
 obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o
+obj-$(CONFIG_PHY_QCOM_USB_HS_28NM)	+= phy-qcom-usb-hs-28nm.o
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
new file mode 100644
index 000000000000..d998e65c89c8
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2009-2018, Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2020, Linaro Limited
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+/* PHY register and bit definitions */
+#define PHY_CTRL_COMMON0		0x078
+#define SIDDQ				BIT(2)
+#define PHY_IRQ_CMD			0x0d0
+#define PHY_INTR_MASK0			0x0d4
+#define PHY_INTR_CLEAR0			0x0dc
+#define DPDM_MASK			0x1e
+#define DP_1_0				BIT(4)
+#define DP_0_1				BIT(3)
+#define DM_1_0				BIT(2)
+#define DM_0_1				BIT(1)
+
+enum hsphy_voltage {
+	VOL_NONE,
+	VOL_MIN,
+	VOL_MAX,
+	VOL_NUM,
+};
+
+enum hsphy_vreg {
+	VDD,
+	VDDA_1P8,
+	VDDA_3P3,
+	VREG_NUM,
+};
+
+struct hsphy_init_seq {
+	int offset;
+	int val;
+	int delay;
+};
+
+struct hsphy_data {
+	const struct hsphy_init_seq *init_seq;
+	unsigned int init_seq_num;
+};
+
+struct hsphy_priv {
+	void __iomem *base;
+	struct clk_bulk_data *clks;
+	int num_clks;
+	struct reset_control *phy_reset;
+	struct reset_control *por_reset;
+	struct regulator_bulk_data vregs[VREG_NUM];
+	const struct hsphy_data *data;
+	enum phy_mode mode;
+};
+
+static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
+				    int submode)
+{
+	struct hsphy_priv *priv = phy_get_drvdata(phy);
+
+	priv->mode = PHY_MODE_INVALID;
+
+	if (mode > 0)
+		priv->mode = mode;
+
+	return 0;
+}
+
+static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv)
+{
+	u32 val;
+
+	/* Clear any existing interrupts before enabling the interrupts */
+	val = readb(priv->base + PHY_INTR_CLEAR0);
+	val |= DPDM_MASK;
+	writeb(val, priv->base + PHY_INTR_CLEAR0);
+
+	writeb(0x0, priv->base + PHY_IRQ_CMD);
+	usleep_range(200, 220);
+	writeb(0x1, priv->base + PHY_IRQ_CMD);
+
+	/* Make sure the interrupts are cleared */
+	usleep_range(200, 220);
+
+	val = readb(priv->base + PHY_INTR_MASK0);
+	switch (priv->mode) {
+	case PHY_MODE_USB_HOST_HS:
+	case PHY_MODE_USB_HOST_FS:
+	case PHY_MODE_USB_DEVICE_HS:
+	case PHY_MODE_USB_DEVICE_FS:
+		val |= DP_1_0 | DM_0_1;
+		break;
+	case PHY_MODE_USB_HOST_LS:
+	case PHY_MODE_USB_DEVICE_LS:
+		val |= DP_0_1 | DM_1_0;
+		break;
+	default:
+		/* No device connected */
+		val |= DP_0_1 | DM_0_1;
+		break;
+	}
+	writeb(val, priv->base + PHY_INTR_MASK0);
+}
+
+static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv)
+{
+	u32 val;
+
+	val = readb(priv->base + PHY_INTR_MASK0);
+	val &= ~DPDM_MASK;
+	writeb(val, priv->base + PHY_INTR_MASK0);
+
+	/* Clear any pending interrupts */
+	val = readb(priv->base + PHY_INTR_CLEAR0);
+	val |= DPDM_MASK;
+	writeb(val, priv->base + PHY_INTR_CLEAR0);
+
+	writeb(0x0, priv->base + PHY_IRQ_CMD);
+	usleep_range(200, 220);
+
+	writeb(0x1, priv->base + PHY_IRQ_CMD);
+	usleep_range(200, 220);
+}
+
+static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv)
+{
+	u32 val;
+
+	val = readb(priv->base + PHY_CTRL_COMMON0);
+	val |= SIDDQ;
+	writeb(val, priv->base + PHY_CTRL_COMMON0);
+}
+
+static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv)
+{
+	u32 val;
+
+	val = readb(priv->base + PHY_CTRL_COMMON0);
+	val &= ~SIDDQ;
+	writeb(val, priv->base + PHY_CTRL_COMMON0);
+}
+
+static int qcom_snps_hsphy_power_on(struct phy *phy)
+{
+	struct hsphy_priv *priv = phy_get_drvdata(phy);
+	int ret;
+
+	ret = regulator_bulk_enable(VREG_NUM, priv->vregs);
+	if (ret)
+		return ret;
+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+	if (ret)
+		goto err_disable_regulator;
+	qcom_snps_hsphy_disable_hv_interrupts(priv);
+	qcom_snps_hsphy_exit_retention(priv);
+
+	return 0;
+
+err_disable_regulator:
+	regulator_bulk_disable(VREG_NUM, priv->vregs);
+
+	return ret;
+}
+
+static int qcom_snps_hsphy_power_off(struct phy *phy)
+{
+	struct hsphy_priv *priv = phy_get_drvdata(phy);
+
+	qcom_snps_hsphy_enter_retention(priv);
+	qcom_snps_hsphy_enable_hv_interrupts(priv);
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+	regulator_bulk_disable(VREG_NUM, priv->vregs);
+
+	return 0;
+}
+
+static int qcom_snps_hsphy_reset(struct hsphy_priv *priv)
+{
+	int ret;
+
+	ret = reset_control_assert(priv->phy_reset);
+	if (ret)
+		return ret;
+
+	usleep_range(10, 15);
+
+	ret = reset_control_deassert(priv->phy_reset);
+	if (ret)
+		return ret;
+
+	usleep_range(80, 100);
+
+	return 0;
+}
+
+static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv)
+{
+	const struct hsphy_data *data = priv->data;
+	const struct hsphy_init_seq *seq;
+	int i;
+
+	/* Device match data is optional. */
+	if (!data)
+		return;
+
+	seq = data->init_seq;
+
+	for (i = 0; i < data->init_seq_num; i++, seq++) {
+		writeb(seq->val, priv->base + seq->offset);
+		if (seq->delay)
+			usleep_range(seq->delay, seq->delay + 10);
+	}
+}
+
+static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv)
+{
+	int ret;
+
+	ret = reset_control_assert(priv->por_reset);
+	if (ret)
+		return ret;
+
+	/*
+	 * The Femto PHY is POR reset in the following scenarios.
+	 *
+	 * 1. After overriding the parameter registers.
+	 * 2. Low power mode exit from PHY retention.
+	 *
+	 * Ensure that SIDDQ is cleared before bringing the PHY
+	 * out of reset.
+	 */
+	qcom_snps_hsphy_exit_retention(priv);
+
+	/*
+	 * As per databook, 10 usec delay is required between
+	 * PHY POR assert and de-assert.
+	 */
+	usleep_range(10, 20);
+	ret = reset_control_deassert(priv->por_reset);
+	if (ret)
+		return ret;
+
+	/*
+	 * As per databook, it takes 75 usec for PHY to stabilize
+	 * after the reset.
+	 */
+	usleep_range(80, 100);
+
+	return 0;
+}
+
+static int qcom_snps_hsphy_init(struct phy *phy)
+{
+	struct hsphy_priv *priv = phy_get_drvdata(phy);
+	int ret;
+
+	ret = qcom_snps_hsphy_reset(priv);
+	if (ret)
+		return ret;
+
+	qcom_snps_hsphy_init_sequence(priv);
+
+	ret = qcom_snps_hsphy_por_reset(priv);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct phy_ops qcom_snps_hsphy_ops = {
+	.init = qcom_snps_hsphy_init,
+	.power_on = qcom_snps_hsphy_power_on,
+	.power_off = qcom_snps_hsphy_power_off,
+	.set_mode = qcom_snps_hsphy_set_mode,
+	.owner = THIS_MODULE,
+};
+
+static const char * const qcom_snps_hsphy_clks[] = {
+	"ref",
+	"ahb",
+	"sleep",
+};
+
+static int qcom_snps_hsphy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct phy_provider *provider;
+	struct hsphy_priv *priv;
+	struct phy *phy;
+	int ret;
+	int i;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks);
+	priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks),
+				  GFP_KERNEL);
+	if (!priv->clks)
+		return -ENOMEM;
+
+	for (i = 0; i < priv->num_clks; i++)
+		priv->clks[i].id = qcom_snps_hsphy_clks[i];
+
+	ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
+	if (ret)
+		return ret;
+
+	priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
+	if (IS_ERR(priv->phy_reset))
+		return PTR_ERR(priv->phy_reset);
+
+	priv->por_reset = devm_reset_control_get_exclusive(dev, "por");
+	if (IS_ERR(priv->por_reset))
+		return PTR_ERR(priv->por_reset);
+
+	priv->vregs[VDD].supply = "vdd";
+	priv->vregs[VDDA_1P8].supply = "vdda1p8";
+	priv->vregs[VDDA_3P3].supply = "vdda3p3";
+
+	ret = devm_regulator_bulk_get(dev, VREG_NUM, priv->vregs);
+	if (ret)
+		return ret;
+
+	/* Get device match data */
+	priv->data = device_get_match_data(dev);
+
+	phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops);
+	if (IS_ERR(phy))
+		return PTR_ERR(phy);
+
+	phy_set_drvdata(phy, priv);
+
+	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(provider))
+		return PTR_ERR(provider);
+
+	ret = regulator_set_load(priv->vregs[VDDA_1P8].consumer, 19000);
+	if (ret < 0)
+		return ret;
+
+	ret = regulator_set_load(priv->vregs[VDDA_3P3].consumer, 16000);
+	if (ret < 0)
+		goto unset_1p8_load;
+
+	return 0;
+
+unset_1p8_load:
+	regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0);
+
+	return ret;
+}
+
+/*
+ * The macro is used to define an initialization sequence.  Each tuple
+ * is meant to program 'value' into phy register at 'offset' with 'delay'
+ * in us followed.
+ */
+#define HSPHY_INIT_CFG(o, v, d)	{ .offset = o, .val = v, .delay = d, }
+
+static const struct hsphy_init_seq init_seq_femtophy[] = {
+	HSPHY_INIT_CFG(0xc0, 0x01, 0),
+	HSPHY_INIT_CFG(0xe8, 0x0d, 0),
+	HSPHY_INIT_CFG(0x74, 0x12, 0),
+	HSPHY_INIT_CFG(0x98, 0x63, 0),
+	HSPHY_INIT_CFG(0x9c, 0x03, 0),
+	HSPHY_INIT_CFG(0xa0, 0x1d, 0),
+	HSPHY_INIT_CFG(0xa4, 0x03, 0),
+	HSPHY_INIT_CFG(0x8c, 0x23, 0),
+	HSPHY_INIT_CFG(0x78, 0x08, 0),
+	HSPHY_INIT_CFG(0x7c, 0xdc, 0),
+	HSPHY_INIT_CFG(0x90, 0xe0, 20),
+	HSPHY_INIT_CFG(0x74, 0x10, 0),
+	HSPHY_INIT_CFG(0x90, 0x60, 0),
+};
+
+static const struct hsphy_data hsphy_data_femtophy = {
+	.init_seq = init_seq_femtophy,
+	.init_seq_num = ARRAY_SIZE(init_seq_femtophy),
+};
+
+static const struct of_device_id qcom_snps_hsphy_match[] = {
+	{ .compatible = "qcom,usb-hs-28nm-femtophy", .data = &hsphy_data_femtophy, },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match);
+
+static struct platform_driver qcom_snps_hsphy_driver = {
+	.probe = qcom_snps_hsphy_probe,
+	.driver	= {
+		.name = "qcom,usb-hs-28nm-phy",
+		.of_match_table = qcom_snps_hsphy_match,
+	},
+};
+module_platform_driver(qcom_snps_hsphy_driver);
+
+MODULE_DESCRIPTION("Qualcomm 28nm Hi-Speed USB PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (2 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 03/18] phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-04 16:17   ` Rob Herring
  2020-03-03 17:11 ` [PATCH v7 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver Bryan O'Donoghue
                   ` (14 subsequent siblings)
  18 siblings, 1 reply; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
	Rob Herring, Mark Rutland, devicetree, Bryan O'Donoghue

From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY
appears in a number of SoCs on various flavors of 20nm and 28nm nodes.

This commit adds information related to the 28nm node only.

Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
definitions.

[bod: converted to yaml format]

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 .../devicetree/bindings/phy/qcom,usb-ss.yaml  | 83 +++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml

diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
new file mode 100644
index 000000000000..bd1388d62ce0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
+
+maintainers:
+  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+  Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
+
+properties:
+  compatible:
+    enum:
+      - qcom,usb-ss-28nm-phy
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+  clocks:
+    items:
+      - description: rpmcc clock
+      - description: PHY AHB clock
+      - description: SuperSpeed pipe clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: ahb
+      - const: pipe
+
+  vdd-supply:
+    description: phandle to the regulator VDD supply node.
+
+  vdda1p8-supply:
+    description: phandle to the regulator 1.8V supply node.
+
+  resets:
+    items:
+      - description: COM reset
+      - description: PHY reset line
+
+  reset-names:
+    items:
+      - const: com
+      - const: phy
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+  - clocks
+  - clock-names
+  - vdd-supply
+  - vdda1p8-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+    #include <dt-bindings/clock/qcom,rpmcc.h>
+    usb3_phy: usb3-phy@78000 {
+        compatible = "qcom,usb-ss-28nm-phy";
+        reg = <0x78000 0x400>;
+        #phy-cells = <0>;
+        clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+                 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+                 <&gcc GCC_USB3_PHY_PIPE_CLK>;
+        clock-names = "ref", "ahb", "pipe";
+        resets = <&gcc GCC_USB3_PHY_BCR>,
+                 <&gcc GCC_USB3PHY_PHY_BCR>;
+        reset-names = "com", "phy";
+        vdd-supply = <&vreg_l3_1p05>;
+        vdda1p8-supply = <&vreg_l5_1p8>;
+    };
+...
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (3 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-09 10:49   ` Kishon Vijay Abraham I
  2020-03-03 17:11 ` [PATCH v7 06/18] usb: dwc3: Registering a role switch in the DRD code Bryan O'Donoghue
                   ` (13 subsequent siblings)
  18 siblings, 1 reply; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
	Sriharsha Allenki's, Andy Gross, Kishon Vijay Abraham I,
	Philipp Zabel, Bryan O'Donoghue

From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the
20nm and 28nm process nodes.

Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code.

[bod: Removed dependency on extcon.
      Switched to gpio-usb-conn to handle VBUS On/Off
      Switched to usb-role-switch to bind gpio-usb-conn to DWC3]
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: Sriharsha Allenki's <sallenki@codeaurora.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 drivers/phy/qualcomm/Kconfig           |   9 +
 drivers/phy/qualcomm/Makefile          |   1 +
 drivers/phy/qualcomm/phy-qcom-usb-ss.c | 246 +++++++++++++++++++++++++
 3 files changed, 256 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 9c56a7216f72..98674ed094d9 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -102,3 +102,12 @@ config PHY_QCOM_USB_HS_28NM
 	  High-Speed PHY driver. This driver supports the Hi-Speed PHY which
 	  is usually paired with either the ChipIdea or Synopsys DWC3 USB
 	  IPs on MSM SOCs.
+
+config PHY_QCOM_USB_SS
+	tristate "Qualcomm USB Super-Speed PHY driver"
+	depends on ARCH_QCOM || COMPILE_TEST
+	depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
+	select GENERIC_PHY
+	help
+	  Enable this to support the Super-Speed USB transceiver on various
+	  Qualcomm chipsets.
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index a4dab5329de0..1f14aeacbd70 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_20NM)		+= phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o
 obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o
 obj-$(CONFIG_PHY_QCOM_USB_HS_28NM)	+= phy-qcom-usb-hs-28nm.o
+obj-$(CONFIG_PHY_QCOM_USB_SS)		+= phy-qcom-usb-ss.o
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
new file mode 100644
index 000000000000..a3a6d3ce7ea1
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2020, Linaro Limited
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#define PHY_CTRL0			0x6C
+#define PHY_CTRL1			0x70
+#define PHY_CTRL2			0x74
+#define PHY_CTRL4			0x7C
+
+/* PHY_CTRL bits */
+#define REF_PHY_EN			BIT(0)
+#define LANE0_PWR_ON			BIT(2)
+#define SWI_PCS_CLK_SEL			BIT(4)
+#define TST_PWR_DOWN			BIT(4)
+#define PHY_RESET			BIT(7)
+
+#define NUM_BULK_CLKS			3
+#define NUM_BULK_REGS			2
+
+struct ssphy_priv {
+	void __iomem *base;
+	struct device *dev;
+	struct reset_control *reset_com;
+	struct reset_control *reset_phy;
+	struct regulator_bulk_data regs[NUM_BULK_REGS];
+	struct clk_bulk_data clks[NUM_BULK_CLKS];
+	enum phy_mode mode;
+};
+
+static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val)
+{
+	writel((readl(addr) & ~mask) | val, addr);
+}
+
+static int qcom_ssphy_do_reset(struct ssphy_priv *priv)
+{
+	int ret;
+
+	if (!priv->reset_com) {
+		qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET,
+				   PHY_RESET);
+		usleep_range(10, 20);
+		qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0);
+	} else {
+		ret = reset_control_assert(priv->reset_com);
+		if (ret) {
+			dev_err(priv->dev, "Failed to assert reset com\n");
+			return ret;
+		}
+
+		ret = reset_control_assert(priv->reset_phy);
+		if (ret) {
+			dev_err(priv->dev, "Failed to assert reset phy\n");
+			return ret;
+		}
+
+		usleep_range(10, 20);
+
+		ret = reset_control_deassert(priv->reset_com);
+		if (ret) {
+			dev_err(priv->dev, "Failed to deassert reset com\n");
+			return ret;
+		}
+
+		ret = reset_control_deassert(priv->reset_phy);
+		if (ret) {
+			dev_err(priv->dev, "Failed to deassert reset phy\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int qcom_ssphy_power_on(struct phy *phy)
+{
+	struct ssphy_priv *priv = phy_get_drvdata(phy);
+	int ret;
+
+	ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs);
+	if (ret)
+		return ret;
+
+	ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks);
+	if (ret)
+		goto err_disable_regulator;
+
+	ret = qcom_ssphy_do_reset(priv);
+	if (ret)
+		goto err_disable_clock;
+
+	writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0);
+	qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON);
+	qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN);
+	qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0);
+
+	return 0;
+err_disable_clock:
+	clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
+err_disable_regulator:
+	regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
+
+	return ret;
+}
+
+static int qcom_ssphy_power_off(struct phy *phy)
+{
+	struct ssphy_priv *priv = phy_get_drvdata(phy);
+
+	qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0);
+	qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0);
+	qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN);
+
+	clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
+	regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
+
+	return 0;
+}
+
+static int qcom_ssphy_init_clock(struct ssphy_priv *priv)
+{
+	priv->clks[0].id = "ref";
+	priv->clks[1].id = "ahb";
+	priv->clks[2].id = "pipe";
+
+	return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks);
+}
+
+static int qcom_ssphy_init_regulator(struct ssphy_priv *priv)
+{
+	int ret;
+
+	priv->regs[0].supply = "vdd";
+	priv->regs[1].supply = "vdda1p8";
+	ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs);
+	if (ret) {
+		if (ret != -EPROBE_DEFER)
+			dev_err(priv->dev, "Failed to get regulators\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int qcom_ssphy_init_reset(struct ssphy_priv *priv)
+{
+	priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com");
+	if (IS_ERR(priv->reset_com)) {
+		dev_err(priv->dev, "Failed to get reset control com\n");
+		return PTR_ERR(priv->reset_com);
+	}
+
+	if (priv->reset_com) {
+		/* if reset_com is present, reset_phy is no longer optional */
+		priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy");
+		if (IS_ERR(priv->reset_phy)) {
+			dev_err(priv->dev, "Failed to get reset control phy\n");
+			return PTR_ERR(priv->reset_phy);
+		}
+	}
+
+	return 0;
+}
+
+static const struct phy_ops qcom_ssphy_ops = {
+	.power_off = qcom_ssphy_power_off,
+	.power_on = qcom_ssphy_power_on,
+	.owner = THIS_MODULE,
+};
+
+static int qcom_ssphy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct phy_provider *provider;
+	struct ssphy_priv *priv;
+	struct phy *phy;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	priv->mode = PHY_MODE_INVALID;
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	ret = qcom_ssphy_init_clock(priv);
+	if (ret)
+		return ret;
+
+	ret = qcom_ssphy_init_reset(priv);
+	if (ret)
+		return ret;
+
+	ret = qcom_ssphy_init_regulator(priv);
+	if (ret)
+		return ret;
+
+	phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "Failed to create the SS phy\n");
+		return PTR_ERR(phy);
+	}
+
+	phy_set_drvdata(phy, priv);
+
+	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id qcom_ssphy_match[] = {
+	{ .compatible = "qcom,usb-ss-28nm-phy", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_ssphy_match);
+
+static struct platform_driver qcom_ssphy_driver = {
+	.probe		= qcom_ssphy_probe,
+	.driver = {
+		.name	= "qcom-usb-ssphy",
+		.of_match_table = qcom_ssphy_match,
+	},
+};
+module_platform_driver(qcom_ssphy_driver);
+
+MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 06/18] usb: dwc3: Registering a role switch in the DRD code.
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (4 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-07  7:20   ` Bjorn Andersson
  2020-03-03 17:11 ` [PATCH v7 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example Bryan O'Donoghue
                   ` (12 subsequent siblings)
  18 siblings, 1 reply; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Yu Chen, Rob Herring, Mark Rutland, ShuFan Lee,
	Heikki Krogerus, Suzuki K Poulose, Chunfeng Yun, Hans de Goede,
	Andy Shevchenko, Jun Li, Valentin Schneider, Guillaume Gardet,
	Bryan O'Donoghue, devicetree, John Stultz

From: Yu Chen <chenyu56@huawei.com>

The Type-C drivers use USB role switch API to inform the
system about the negotiated data role, so registering a role
switch in the DRD code in order to support platforms with
USB Type-C connectors.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
CC: ShuFan Lee <shufan_lee@richtek.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Jun Li <lijun.kernel@gmail.com>
Cc: Valentin Schneider <valentin.schneider@arm.com>
Cc: Guillaume Gardet <Guillaume.Gardet@arm.com>
Cc: Jack Pham <jackp@codeaurora.org>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Yu Chen <chenyu56@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
---
 drivers/usb/dwc3/core.h |  3 ++
 drivers/usb/dwc3/drd.c  | 77 ++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 77c4a9abe365..a99e57636172 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -25,6 +25,7 @@
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/role.h>
 #include <linux/ulpi/interface.h>
 
 #include <linux/phy/phy.h>
@@ -953,6 +954,7 @@ struct dwc3_scratchpad_array {
  * @hsphy_mode: UTMI phy mode, one of following:
  *		- USBPHY_INTERFACE_MODE_UTMI
  *		- USBPHY_INTERFACE_MODE_UTMIW
+ * @role_sw: usb_role_switch handle
  * @usb2_phy: pointer to USB2 PHY
  * @usb3_phy: pointer to USB3 PHY
  * @usb2_generic_phy: pointer to USB2 PHY
@@ -1086,6 +1088,7 @@ struct dwc3 {
 	struct extcon_dev	*edev;
 	struct notifier_block	edev_nb;
 	enum usb_phy_interface	hsphy_mode;
+	struct usb_role_switch	*role_sw;
 
 	u32			fladj;
 	u32			irq_gadget;
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index c946d64142ad..331c6e997f0c 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -476,6 +476,73 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
 	return edev;
 }
 
+#if IS_ENABLED(CONFIG_USB_ROLE_SWITCH)
+#define ROLE_SWITCH 1
+static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role)
+{
+	struct dwc3 *dwc = dev_get_drvdata(dev);
+	u32 mode;
+
+	switch (role) {
+	case USB_ROLE_HOST:
+		mode = DWC3_GCTL_PRTCAP_HOST;
+		break;
+	case USB_ROLE_DEVICE:
+		mode = DWC3_GCTL_PRTCAP_DEVICE;
+		break;
+	default:
+		mode = DWC3_GCTL_PRTCAP_DEVICE;
+		break;
+	}
+
+	dwc3_set_mode(dwc, mode);
+	return 0;
+}
+
+static enum usb_role dwc3_usb_role_switch_get(struct device *dev)
+{
+	struct dwc3 *dwc = dev_get_drvdata(dev);
+	unsigned long flags;
+	enum usb_role role;
+
+	spin_lock_irqsave(&dwc->lock, flags);
+	switch (dwc->current_dr_role) {
+	case DWC3_GCTL_PRTCAP_HOST:
+		role = USB_ROLE_HOST;
+		break;
+	case DWC3_GCTL_PRTCAP_DEVICE:
+		role = USB_ROLE_DEVICE;
+		break;
+	case DWC3_GCTL_PRTCAP_OTG:
+		role = dwc->current_otg_role;
+		break;
+	default:
+		role = USB_ROLE_DEVICE;
+		break;
+	}
+	spin_unlock_irqrestore(&dwc->lock, flags);
+	return role;
+}
+
+static int dwc3_setup_role_switch(struct dwc3 *dwc)
+{
+	struct usb_role_switch_desc dwc3_role_switch = {NULL};
+
+	dwc3_role_switch.fwnode = dev_fwnode(dwc->dev);
+	dwc3_role_switch.set = dwc3_usb_role_switch_set;
+	dwc3_role_switch.get = dwc3_usb_role_switch_get;
+	dwc->role_sw = usb_role_switch_register(dwc->dev, &dwc3_role_switch);
+	if (IS_ERR(dwc->role_sw))
+		return PTR_ERR(dwc->role_sw);
+
+	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
+	return 0;
+}
+#else
+#define ROLE_SWITCH 0
+#define dwc3_setup_role_switch(x) 0
+#endif
+
 int dwc3_drd_init(struct dwc3 *dwc)
 {
 	int ret, irq;
@@ -484,7 +551,12 @@ int dwc3_drd_init(struct dwc3 *dwc)
 	if (IS_ERR(dwc->edev))
 		return PTR_ERR(dwc->edev);
 
-	if (dwc->edev) {
+	if (ROLE_SWITCH &&
+	    device_property_read_bool(dwc->dev, "usb-role-switch")) {
+		ret = dwc3_setup_role_switch(dwc);
+		if (ret < 0)
+			return ret;
+	} else if (dwc->edev) {
 		dwc->edev_nb.notifier_call = dwc3_drd_notifier;
 		ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
 					       &dwc->edev_nb);
@@ -531,6 +603,9 @@ void dwc3_drd_exit(struct dwc3 *dwc)
 {
 	unsigned long flags;
 
+	if (dwc->role_sw)
+		usb_role_switch_unregister(dwc->role_sw);
+
 	if (dwc->edev)
 		extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST,
 					   &dwc->edev_nb);
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (5 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 06/18] usb: dwc3: Registering a role switch in the DRD code Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-04 14:57   ` Rob Herring
  2020-03-03 17:11 ` [PATCH v7 08/18] dt-bindings: usb: dwc3: Add a usb-role-switch to the example Bryan O'Donoghue
                   ` (11 subsequent siblings)
  18 siblings, 1 reply; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Rob Herring, Mark Rutland,
	devicetree

A USB connector should be a child node of the USB controller
connector/usb-connector.txt. This patch adds an example of how to do this
to the dwc3 binding descriptions.

It is necessary to declare a connector as a child-node of a USB controller
for role-switching to work, so this example should be helpful to others
implementing that.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 Documentation/devicetree/bindings/usb/dwc3.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 66780a47ad85..4e1e4afccee6 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -121,4 +121,12 @@ dwc3@4a030000 {
 	interrupts = <0 92 4>
 	usb-phy = <&usb2_phy>, <&usb3,phy>;
 	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+
+	usb_con: connector {
+		compatible = "gpio-usb-b-connector";
+		id-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+		vbus-supply = <&usb3_vbus_reg>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3_id_pin>, <&usb3_vbus_pin>;
+	};
 };
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 08/18] dt-bindings: usb: dwc3: Add a usb-role-switch to the example
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (6 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 09/18] usb: dwc3: qcom: Add support for usb-conn-gpio connectors Bryan O'Donoghue
                   ` (10 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue

This patch adds usb-role-switch to the example dwc3 given in the file.

Documentation/devicetree/bindings/usb/generic.txt makes this a valid
declaration for dwc3 this patch gives an example of how to use it.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 Documentation/devicetree/bindings/usb/dwc3.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 4e1e4afccee6..8c6c7b355356 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -121,6 +121,7 @@ dwc3@4a030000 {
 	interrupts = <0 92 4>
 	usb-phy = <&usb2_phy>, <&usb3,phy>;
 	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+	usb-role-switch;
 
 	usb_con: connector {
 		compatible = "gpio-usb-b-connector";
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 09/18] usb: dwc3: qcom: Add support for usb-conn-gpio connectors
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (7 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 08/18] dt-bindings: usb: dwc3: Add a usb-role-switch to the example Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 10/18] usb: dwc3: " Bryan O'Donoghue
                   ` (9 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Lee Jones, Philipp Zabel

This patch adds a routine to find a usb-conn-gpio in the main DWC3 code.
This will be useful in a subsequent patch where we will reuse the current
extcon VBUS notifier with usb-conn-gpio.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 drivers/usb/dwc3/dwc3-qcom.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 1dfd024cd06b..6f4b2b3cffce 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -550,6 +550,21 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
 	.ss_phy_irq_index = 2
 };
 
+static bool dwc3_qcom_find_gpio_usb_connector(struct platform_device *pdev)
+{
+	struct device_node	*np;
+	bool			retval = false;
+
+	np = of_get_child_by_name(pdev->dev.of_node, "connector");
+	if (np) {
+		if (of_device_is_compatible(np, "gpio-usb-b-connector"))
+			retval = true;
+	}
+	of_node_put(np);
+
+	return retval;
+}
+
 static int dwc3_qcom_probe(struct platform_device *pdev)
 {
 	struct device_node	*np = pdev->dev.of_node;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 10/18] usb: dwc3: Add support for usb-conn-gpio connectors
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (8 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 09/18] usb: dwc3: qcom: Add support for usb-conn-gpio connectors Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 11/18] usb: dwc3: Add support for a role-switch notifier Bryan O'Donoghue
                   ` (8 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, John Stultz, Lee Jones,
	Rob Herring, Mark Rutland, ShuFan Lee, Heikki Krogerus,
	Suzuki K Poulose, Chunfeng Yun, Yu Chen, Hans de Goede,
	Andy Shevchenko, Jun Li, Valentin Schneider, devicetree

This patch adds the ability to probe and enumerate a connector based on
usb-conn-gpio.

You would use usb-conn-gpio when a regulator in your system provides VBUS
directly to the connector instead of supplying via the USB PHY.

The parent device must have the "usb-role-switch" property, so that when
the usb-conn-gpio driver calls usb_role_switch_set_role() the notification
in dwc3 will run and the block registers will be updated to match the state
detected at the connector.

Cc: John Stultz <john.stultz@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
CC: ShuFan Lee <shufan_lee@richtek.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Jun Li <lijun.kernel@gmail.com>
Cc: Valentin Schneider <valentin.schneider@arm.com>
Cc: Jack Pham <jackp@codeaurora.org>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 drivers/usb/dwc3/drd.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index 331c6e997f0c..2ec1ae30bcc5 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -11,6 +11,7 @@
 #include <linux/of_graph.h>
 #include <linux/platform_device.h>
 #include <linux/property.h>
+#include <linux/of_platform.h>
 
 #include "debug.h"
 #include "core.h"
@@ -538,9 +539,30 @@ static int dwc3_setup_role_switch(struct dwc3 *dwc)
 	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 	return 0;
 }
+
+static int dwc3_register_gpio_usb_connector(struct dwc3 *dwc)
+{
+	struct device		*dev = dwc->dev;
+	struct device_node	*np = dev->of_node, *conn_np;
+	int			ret = 0;
+
+	conn_np = of_get_child_by_name(np, "connector");
+	if (!conn_np) {
+		dev_dbg(dev, "no connector child node specified\n");
+		goto done;
+	}
+
+	if (of_device_is_compatible(conn_np, "gpio-usb-b-connector"))
+		ret = of_platform_populate(np, NULL, NULL, dev);
+done:
+	of_node_put(conn_np);
+	return ret;
+}
+
 #else
 #define ROLE_SWITCH 0
 #define dwc3_setup_role_switch(x) 0
+#define dwc3_register_gpio_usb_connector(x) 0
 #endif
 
 int dwc3_drd_init(struct dwc3 *dwc)
@@ -556,6 +578,9 @@ int dwc3_drd_init(struct dwc3 *dwc)
 		ret = dwc3_setup_role_switch(dwc);
 		if (ret < 0)
 			return ret;
+		ret = dwc3_register_gpio_usb_connector(dwc);
+		if (ret < 0)
+			return ret;
 	} else if (dwc->edev) {
 		dwc->edev_nb.notifier_call = dwc3_drd_notifier;
 		ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 11/18] usb: dwc3: Add support for a role-switch notifier
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (9 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 10/18] usb: dwc3: " Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 12/18] usb: dwc3: qcom: Enable gpio-usb-conn based role-switching Bryan O'Donoghue
                   ` (7 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Lee Jones, Philipp Zabel

Role-switching is a 1:1 mapping between a producer and a consumer. For DWC3
we have some vendor specific wrappers, notably the qcom wrapper that want
to toggle some PHY related bits on a USB role switch.

This patch adds a role-switch notifier to the dwc3 drd code. When the USB
role-switch set() routine runs, the notifier will fire passing the notified
mode to the consumer, thus allowing vendor specific fix-ups to toggle from
the role-switching events.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Jack Pham <jackp@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Jack Pham <jackp@codeaurora.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 drivers/usb/dwc3/core.h | 19 +++++++++++++++++++
 drivers/usb/dwc3/drd.c  | 17 +++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a99e57636172..c2e85f587674 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -955,6 +955,7 @@ struct dwc3_scratchpad_array {
  *		- USBPHY_INTERFACE_MODE_UTMI
  *		- USBPHY_INTERFACE_MODE_UTMIW
  * @role_sw: usb_role_switch handle
+ * @role_sw_nl: role switch notifier list
  * @usb2_phy: pointer to USB2 PHY
  * @usb3_phy: pointer to USB3 PHY
  * @usb2_generic_phy: pointer to USB2 PHY
@@ -1089,6 +1090,7 @@ struct dwc3 {
 	struct notifier_block	edev_nb;
 	enum usb_phy_interface	hsphy_mode;
 	struct usb_role_switch	*role_sw;
+	struct raw_notifier_head role_sw_nl;
 
 	u32			fladj;
 	u32			irq_gadget;
@@ -1499,4 +1501,21 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
 { }
 #endif
 
+#if IS_ENABLED(CONFIG_USB_ROLE_SWITCH)
+int dwc3_role_switch_notifier_register(struct dwc3 *dwc,
+				       struct notifier_block *nb);
+int dwc3_role_switch_notifier_unregister(struct dwc3 *dwc,
+					 struct notifier_block *nb);
+#else
+static inline int
+dwc3_role_switch_notifier_register(struct dwc3 *dwc,
+				   struct notifier_block *nb)
+{ return 0; }
+
+static inline int
+dwc3_role_switch_notifier_unregister(struct dwc3 *dwc,
+				     struct notifier_block *nb)
+{ return 0; }
+#endif
+
 #endif /* __DRIVERS_USB_DWC3_CORE_H */
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index 2ec1ae30bcc5..d65b1cc2f4b6 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -497,6 +497,8 @@ static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role)
 	}
 
 	dwc3_set_mode(dwc, mode);
+	raw_notifier_call_chain(&dwc->role_sw_nl, mode, NULL);
+
 	return 0;
 }
 
@@ -559,6 +561,18 @@ static int dwc3_register_gpio_usb_connector(struct dwc3 *dwc)
 	return ret;
 }
 
+int dwc3_role_switch_notifier_register(struct dwc3 *dwc,
+				       struct notifier_block *nb)
+{
+	return raw_notifier_chain_register(&dwc->role_sw_nl, nb);
+}
+
+int dwc3_role_switch_notifier_unregister(struct dwc3 *dwc,
+					 struct notifier_block *nb)
+{
+	return raw_notifier_chain_unregister(&dwc->role_sw_nl, nb);
+}
+
 #else
 #define ROLE_SWITCH 0
 #define dwc3_setup_role_switch(x) 0
@@ -581,6 +595,9 @@ int dwc3_drd_init(struct dwc3 *dwc)
 		ret = dwc3_register_gpio_usb_connector(dwc);
 		if (ret < 0)
 			return ret;
+
+		RAW_INIT_NOTIFIER_HEAD(&dwc->role_sw_nl);
+
 	} else if (dwc->edev) {
 		dwc->edev_nb.notifier_call = dwc3_drd_notifier;
 		ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 12/18] usb: dwc3: qcom: Enable gpio-usb-conn based role-switching
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (10 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 11/18] usb: dwc3: Add support for a role-switch notifier Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 13/18] arm64: dts: qcom: qcs404: Add USB devices and PHYs Bryan O'Donoghue
                   ` (6 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Lee Jones, Philipp Zabel

This patch adds the ability to receive a notification from the DRD code for
role-switch events and in doing so it introduces a disjunction between
gpio-usb-conn or extcon mode.

This is what we want to do, since the two methods are mutually exclusive.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Jack Pham <jackp@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 drivers/usb/dwc3/dwc3-qcom.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 6f4b2b3cffce..f6a7ede5953e 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -571,6 +571,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
 	struct device		*dev = &pdev->dev;
 	struct dwc3_qcom	*qcom;
 	struct resource		*res, *parent_res = NULL;
+	struct dwc3		*dwc;
 	int			ret, i;
 	bool			ignore_pipe_clk;
 
@@ -669,8 +670,16 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
 	if (qcom->mode == USB_DR_MODE_PERIPHERAL)
 		dwc3_qcom_vbus_overrride_enable(qcom, true);
 
-	/* register extcon to override sw_vbus on Vbus change later */
-	ret = dwc3_qcom_register_extcon(qcom);
+	if (dwc3_qcom_find_gpio_usb_connector(qcom->dwc3)) {
+		/* Using gpio-usb-conn register a notifier for VBUS */
+		dwc = platform_get_drvdata(qcom->dwc3);
+		qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
+		ret = dwc3_role_switch_notifier_register(dwc, &qcom->vbus_nb);
+	} else {
+		/* register extcon to override sw_vbus on Vbus change later */
+		ret = dwc3_qcom_register_extcon(qcom);
+	}
+
 	if (ret)
 		goto depopulate;
 
@@ -702,8 +711,11 @@ static int dwc3_qcom_remove(struct platform_device *pdev)
 {
 	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 	struct device *dev = &pdev->dev;
+	struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
 	int i;
 
+	dwc3_role_switch_notifier_unregister(dwc, &qcom->vbus_nb);
+
 	of_platform_depopulate(dev);
 
 	for (i = qcom->num_clocks - 1; i >= 0; i--) {
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 13/18] arm64: dts: qcom: qcs404: Add USB devices and PHYs
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (11 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 12/18] usb: dwc3: qcom: Enable gpio-usb-conn based role-switching Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 14/18] arm64: dts: qcom: qcs404-evb: Define VBUS pins Bryan O'Donoghue
                   ` (5 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Vinod Koul, Shawn Guo, Andy Gross, Rob Herring,
	Mark Rutland, devicetree, Bryan O'Donoghue

From: Bjorn Andersson <bjorn.andersson@linaro.org>

QCS404 sports HS and SS USB controllers based on dwc3 block with two HS
PHYs and one SS PHY. Add nodes for these devices and enable them for
EVB board.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 100 +++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 4ee1e3d5f123..d3347ce2b94f 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -323,6 +323,48 @@ rpm_msg_ram: memory@60000 {
 			reg = <0x00060000 0x6000>;
 		};
 
+		usb3_phy: phy@78000 {
+			compatible = "qcom,usb-ss-28nm-phy";
+			reg = <0x00078000 0x400>;
+			#phy-cells = <0>;
+			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
+			clock-names = "ref", "ahb", "pipe";
+			resets = <&gcc GCC_USB3_PHY_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_BCR>;
+			reset-names = "com", "phy";
+			status = "disabled";
+		};
+
+		usb2_phy_prim: phy@7a000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			reg = <0x0007a000 0x200>;
+			#phy-cells = <0>;
+			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ref", "ahb", "sleep";
+			resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+				 <&gcc GCC_USB2A_PHY_BCR>;
+			reset-names = "phy", "por";
+			status = "disabled";
+		};
+
+		usb2_phy_sec: phy@7c000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			reg = <0x0007c000 0x200>;
+			#phy-cells = <0>;
+			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ref", "ahb", "sleep";
+			resets = <&gcc GCC_QUSB2_PHY_BCR>,
+				 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+			reset-names = "phy", "por";
+			status = "disabled";
+		};
+
 		qfprom: qfprom@a4000 {
 			compatible = "qcom,qfprom";
 			reg = <0x000a4000 0x1000>;
@@ -486,6 +528,64 @@ glink-edge {
 			};
 		};
 
+		usb3: usb@7678800 {
+			compatible = "qcom,dwc3";
+			reg = <0x07678800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clocks = <&gcc GCC_USB30_MASTER_CLK>,
+				 <&gcc GCC_SYS_NOC_USB3_CLK>,
+				 <&gcc GCC_USB30_SLEEP_CLK>,
+				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+			clock-names = "core", "iface", "sleep", "mock_utmi";
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+			status = "disabled";
+
+			dwc3@7580000 {
+				compatible = "snps,dwc3";
+				reg = <0x07580000 0xcd00>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy_sec>, <&usb3_phy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+				dr_mode = "otg";
+			};
+		};
+
+		usb2: usb@79b8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x079b8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
+				 <&gcc GCC_PCNOC_USB2_CLK>,
+				 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
+				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+			clock-names = "core", "iface", "sleep", "mock_utmi";
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			assigned-clock-rates = <19200000>, <133333333>;
+			status = "disabled";
+
+			dwc3@78c0000 {
+				compatible = "snps,dwc3";
+				reg = <0x078c0000 0xcc00>;
+				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy_prim>;
+				phy-names = "usb2-phy";
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+				dr_mode = "peripheral";
+			};
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,qcs404-pinctrl";
 			reg = <0x01000000 0x200000>,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 14/18] arm64: dts: qcom: qcs404-evb: Define VBUS pins
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (12 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 13/18] arm64: dts: qcom: qcs404: Add USB devices and PHYs Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 15/18] arm64: dts: qcom: qcs404-evb: Define USB ID pin Bryan O'Donoghue
                   ` (4 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
	Mark Rutland, devicetree

Defines VBUS detect and VBUS boost for the QCS404 EVB.

Detect:
VBUS present/absent is presented to the SoC via a GPIO on the EVB. Define
the pin mapping for later use by gpio-usb-conn.

Boost:
An external regulator is used to trigger VBUS on/off via GPIO. This patch
defines the relevant GPIO in the EVB dts.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 522d3ef72df5..62ef9c34b04e 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -4,6 +4,8 @@
 #include <dt-bindings/gpio/gpio.h>
 #include "qcs404.dtsi"
 #include "pms405.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 
 / {
 	aliases {
@@ -271,6 +273,26 @@ rclk {
 	};
 };
 
+&pms405_gpios {
+	usb_vbus_boost_pin: usb-vbus-boost-pin {
+		pinconf {
+			pins = "gpio3";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+			power-source = <1>;
+		};
+	};
+	usb3_vbus_pin: usb3-vbus-pin {
+		pinconf {
+			pins = "gpio12";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			input-enable;
+			bias-pull-down;
+			power-source = <1>;
+		};
+	};
+};
+
 &wifi {
 	status = "okay";
 	vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 15/18] arm64: dts: qcom: qcs404-evb: Define USB ID pin
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (13 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 14/18] arm64: dts: qcom: qcs404-evb: Define VBUS pins Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 16/18] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator Bryan O'Donoghue
                   ` (3 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
	Mark Rutland, devicetree

The USB ID pin is used to tell if a system is a Host or a Device. For our
purposes we will bind this pin into gpio-usb-conn later.

For now define the pin with its pinmux.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 62ef9c34b04e..cb893ca76901 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -271,6 +271,20 @@ rclk {
 			bias-pull-down;
 		};
 	};
+
+	usb3_id_pin: usb3-id-pin {
+		pinmux {
+			pins = "gpio116";
+			function = "gpio";
+		};
+
+		pinconf {
+			pins = "gpio116";
+			drive-strength = <2>;
+			bias-pull-up;
+			input-enable;
+		};
+	};
 };
 
 &pms405_gpios {
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 16/18] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (14 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 15/18] arm64: dts: qcom: qcs404-evb: Define USB ID pin Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 17/18] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Bryan O'Donoghue
                   ` (2 subsequent siblings)
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
	Mark Rutland, devicetree

VBUS is supplied by an external regulator controlled by a GPIO pin. This
patch models the regulator as regulator-usb3-vbus.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index cb893ca76901..4b529a6077d2 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -33,6 +33,18 @@ vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};
+
+	usb3_vbus_reg: regulator-usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "VBUS_BOOST_5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_vbus_boost_pin>;
+		vin-supply = <&vph_pwr>;
+		enable-active-high;
+	};
 };
 
 &blsp1_uart3 {
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 17/18] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (15 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 16/18] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-03 17:11 ` [PATCH v7 18/18] arm64: dts: qcom: qcs404-evb: Enable USB controllers Bryan O'Donoghue
  2020-03-08  5:23 ` [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bjorn Andersson
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
	Mark Rutland, devicetree

Rather than set the minimum microvolt for this regulator in the USB SS PHY
driver, set it in the DTS.

Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 4b529a6077d2..44c7dda1e1fc 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -200,7 +200,7 @@ vreg_l11_sdc2: l11 {
 		};
 
 		vreg_l12_3p3: l12 {
-			regulator-min-microvolt = <2968000>;
+			regulator-min-microvolt = <3050000>;
 			regulator-max-microvolt = <3300000>;
 		};
 
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* [PATCH v7 18/18] arm64: dts: qcom: qcs404-evb: Enable USB controllers
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (16 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 17/18] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Bryan O'Donoghue
@ 2020-03-03 17:11 ` Bryan O'Donoghue
  2020-03-08  5:23 ` [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bjorn Andersson
  18 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-03 17:11 UTC (permalink / raw)
  To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson, robh
  Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
	Mark Rutland, devicetree

This patch enables the primary and secondary USB controllers on the
qcs404-evb.

Primary:
The primary USB controller has

- One USB3 SS PHY using gpio-usb-conn
- One USB2 HS PHY in device mode only and no connector driver
  associated.

Secondary:
The second DWC3 controller which has one USB Hi-Speed PHY attached to it.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 40 ++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 44c7dda1e1fc..4dc3f45282fe 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -319,6 +319,46 @@ pinconf {
 	};
 };
 
+&usb2 {
+	status = "okay";
+};
+
+&usb2_phy_sec {
+	vdd-supply = <&vreg_l4_1p2>;
+	vdda1p8-supply = <&vreg_l5_1p8>;
+	vdda3p3-supply = <&vreg_l12_3p3>;
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+	dwc3@7580000 {
+		usb-role-switch;
+		usb_con: connector {
+			compatible = "gpio-usb-b-connector";
+			label = "USB-C";
+			id-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+			vbus-supply = <&usb3_vbus_reg>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usb3_id_pin>, <&usb3_vbus_pin>;
+			status = "okay";
+		};
+	};
+};
+
+&usb2_phy_prim {
+	vdd-supply = <&vreg_l4_1p2>;
+	vdda1p8-supply = <&vreg_l5_1p8>;
+	vdda3p3-supply = <&vreg_l12_3p3>;
+	status = "okay";
+};
+
+&usb3_phy {
+	vdd-supply = <&vreg_l3_1p05>;
+	vdda1p8-supply = <&vreg_l5_1p8>;
+	status = "okay";
+};
+
 &wifi {
 	status = "okay";
 	vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH v7 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example
  2020-03-03 17:11 ` [PATCH v7 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example Bryan O'Donoghue
@ 2020-03-04 14:57   ` Rob Herring
  2020-03-04 16:24     ` Bryan O'Donoghue
  0 siblings, 1 reply; 26+ messages in thread
From: Rob Herring @ 2020-03-04 14:57 UTC (permalink / raw)
  To: Bryan O'Donoghue
  Cc: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson,
	robh, linux-kernel, Bryan O'Donoghue, Mark Rutland,
	devicetree

On Tue,  3 Mar 2020 17:11:48 +0000, Bryan O'Donoghue wrote:
> A USB connector should be a child node of the USB controller
> connector/usb-connector.txt. This patch adds an example of how to do this
> to the dwc3 binding descriptions.
> 
> It is necessary to declare a connector as a child-node of a USB controller
> for role-switching to work, so this example should be helpful to others
> implementing that.
> 
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: linux-usb@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Acked-by: Felipe Balbi <balbi@kernel.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
>  Documentation/devicetree/bindings/usb/dwc3.txt | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.

If a tag was not added on purpose, please state why and what changed.

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH v7 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
  2020-03-03 17:11 ` [PATCH v7 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Bryan O'Donoghue
@ 2020-03-04 16:17   ` Rob Herring
  0 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2020-03-04 16:17 UTC (permalink / raw)
  To: Bryan O'Donoghue
  Cc: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson,
	robh, linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
	Mark Rutland, devicetree, Bryan O'Donoghue

On Tue,  3 Mar 2020 17:11:45 +0000, Bryan O'Donoghue wrote:
> From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> 
> Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY
> appears in a number of SoCs on various flavors of 20nm and 28nm nodes.
> 
> This commit adds information related to the 28nm node only.
> 
> Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
> definitions.
> 
> [bod: converted to yaml format]
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
>  .../devicetree/bindings/phy/qcom,usb-ss.yaml  | 83 +++++++++++++++++++
>  1 file changed, 83 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH v7 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example
  2020-03-04 14:57   ` Rob Herring
@ 2020-03-04 16:24     ` Bryan O'Donoghue
  0 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-04 16:24 UTC (permalink / raw)
  To: Rob Herring
  Cc: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson,
	linux-kernel, Mark Rutland, devicetree

On 04/03/2020 14:57, Rob Herring wrote:
> On Tue,  3 Mar 2020 17:11:48 +0000, Bryan O'Donoghue wrote:
>> A USB connector should be a child node of the USB controller
>> connector/usb-connector.txt. This patch adds an example of how to do this
>> to the dwc3 binding descriptions.
>>
>> It is necessary to declare a connector as a child-node of a USB controller
>> for role-switching to work, so this example should be helpful to others
>> implementing that.
>>
>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: linux-usb@vger.kernel.org
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Acked-by: Felipe Balbi <balbi@kernel.org>
>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> ---
>>   Documentation/devicetree/bindings/usb/dwc3.txt | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
> 
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
> 
> If a tag was not added on purpose, please state why and what changed.
> 

Yep apologies I forgot to add your

Reviewed-by: Rob Herring <robh@kernel.org>

when posting this one

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH v7 06/18] usb: dwc3: Registering a role switch in the DRD code.
  2020-03-03 17:11 ` [PATCH v7 06/18] usb: dwc3: Registering a role switch in the DRD code Bryan O'Donoghue
@ 2020-03-07  7:20   ` Bjorn Andersson
  0 siblings, 0 replies; 26+ messages in thread
From: Bjorn Andersson @ 2020-03-07  7:20 UTC (permalink / raw)
  To: Bryan O'Donoghue
  Cc: linux-arm-msm, linux-usb, gregkh, jackp, balbi, robh,
	linux-kernel, Yu Chen, Rob Herring, Mark Rutland, ShuFan Lee,
	Heikki Krogerus, Suzuki K Poulose, Chunfeng Yun, Hans de Goede,
	Andy Shevchenko, Jun Li, Valentin Schneider, Guillaume Gardet,
	devicetree, John Stultz

On Tue 03 Mar 09:11 PST 2020, Bryan O'Donoghue wrote:

> From: Yu Chen <chenyu56@huawei.com>
> 
> The Type-C drivers use USB role switch API to inform the
> system about the negotiated data role, so registering a role
> switch in the DRD code in order to support platforms with
> USB Type-C connectors.
> 
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> CC: ShuFan Lee <shufan_lee@richtek.com>
> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
> Cc: Yu Chen <chenyu56@huawei.com>
> Cc: Felipe Balbi <balbi@kernel.org>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Jun Li <lijun.kernel@gmail.com>
> Cc: Valentin Schneider <valentin.schneider@arm.com>
> Cc: Guillaume Gardet <Guillaume.Gardet@arm.com>
> Cc: Jack Pham <jackp@codeaurora.org>
> Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Cc: linux-usb@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Signed-off-by: Yu Chen <chenyu56@huawei.com>
> Signed-off-by: John Stultz <john.stultz@linaro.org>
> ---
>  drivers/usb/dwc3/core.h |  3 ++
>  drivers/usb/dwc3/drd.c  | 77 ++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 79 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 77c4a9abe365..a99e57636172 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -25,6 +25,7 @@
>  #include <linux/usb/ch9.h>
>  #include <linux/usb/gadget.h>
>  #include <linux/usb/otg.h>
> +#include <linux/usb/role.h>
>  #include <linux/ulpi/interface.h>
>  
>  #include <linux/phy/phy.h>
> @@ -953,6 +954,7 @@ struct dwc3_scratchpad_array {
>   * @hsphy_mode: UTMI phy mode, one of following:
>   *		- USBPHY_INTERFACE_MODE_UTMI
>   *		- USBPHY_INTERFACE_MODE_UTMIW
> + * @role_sw: usb_role_switch handle
>   * @usb2_phy: pointer to USB2 PHY
>   * @usb3_phy: pointer to USB3 PHY
>   * @usb2_generic_phy: pointer to USB2 PHY
> @@ -1086,6 +1088,7 @@ struct dwc3 {
>  	struct extcon_dev	*edev;
>  	struct notifier_block	edev_nb;
>  	enum usb_phy_interface	hsphy_mode;
> +	struct usb_role_switch	*role_sw;
>  
>  	u32			fladj;
>  	u32			irq_gadget;
> diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
> index c946d64142ad..331c6e997f0c 100644
> --- a/drivers/usb/dwc3/drd.c
> +++ b/drivers/usb/dwc3/drd.c
> @@ -476,6 +476,73 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
>  	return edev;
>  }
>  
> +#if IS_ENABLED(CONFIG_USB_ROLE_SWITCH)
> +#define ROLE_SWITCH 1
> +static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role)

The prototype for set and get was changed in 'bce3052f0c16 ("usb: roles:
Provide the switch drivers handle to the switch in the API")', so this
no longer compiles.

The new prototype should be:
static int dwc3_usb_role_switch_set(struct usb_role_switch *sw, enum usb_role role)

> +{
> +	struct dwc3 *dwc = dev_get_drvdata(dev);

And this would then be:
	struct dwc3 *dwc = usb_role_switch_get_drvdata(sw);

> +	u32 mode;
> +
> +	switch (role) {
> +	case USB_ROLE_HOST:
> +		mode = DWC3_GCTL_PRTCAP_HOST;
> +		break;
> +	case USB_ROLE_DEVICE:
> +		mode = DWC3_GCTL_PRTCAP_DEVICE;
> +		break;
> +	default:
> +		mode = DWC3_GCTL_PRTCAP_DEVICE;
> +		break;
> +	}
> +
> +	dwc3_set_mode(dwc, mode);
> +	return 0;
> +}
> +
> +static enum usb_role dwc3_usb_role_switch_get(struct device *dev)

static enum usb_role dwc3_usb_role_switch_get(struct usb_role_switch sw)

> +{
> +	struct dwc3 *dwc = dev_get_drvdata(dev);

	struct dwc3 *dwc = usb_role_switch_get_drvdata(sw);

> +	unsigned long flags;
> +	enum usb_role role;
> +
> +	spin_lock_irqsave(&dwc->lock, flags);
> +	switch (dwc->current_dr_role) {
> +	case DWC3_GCTL_PRTCAP_HOST:
> +		role = USB_ROLE_HOST;
> +		break;
> +	case DWC3_GCTL_PRTCAP_DEVICE:
> +		role = USB_ROLE_DEVICE;
> +		break;
> +	case DWC3_GCTL_PRTCAP_OTG:
> +		role = dwc->current_otg_role;
> +		break;
> +	default:
> +		role = USB_ROLE_DEVICE;
> +		break;
> +	}
> +	spin_unlock_irqrestore(&dwc->lock, flags);
> +	return role;
> +}
> +
> +static int dwc3_setup_role_switch(struct dwc3 *dwc)
> +{
> +	struct usb_role_switch_desc dwc3_role_switch = {NULL};
> +
> +	dwc3_role_switch.fwnode = dev_fwnode(dwc->dev);
> +	dwc3_role_switch.set = dwc3_usb_role_switch_set;
> +	dwc3_role_switch.get = dwc3_usb_role_switch_get;

And you need to pass dwc as .driver_data here:

	dwc3_role_switch.driver_data = dwc;

With this the series compiles and both dwc3 devices probes nicely. I
haven't done any further testing though...

Regards,
Bjorn

> +	dwc->role_sw = usb_role_switch_register(dwc->dev, &dwc3_role_switch);
> +	if (IS_ERR(dwc->role_sw))
> +		return PTR_ERR(dwc->role_sw);
> +
> +	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
> +	return 0;
> +}
> +#else
> +#define ROLE_SWITCH 0
> +#define dwc3_setup_role_switch(x) 0
> +#endif
> +
>  int dwc3_drd_init(struct dwc3 *dwc)
>  {
>  	int ret, irq;
> @@ -484,7 +551,12 @@ int dwc3_drd_init(struct dwc3 *dwc)
>  	if (IS_ERR(dwc->edev))
>  		return PTR_ERR(dwc->edev);
>  
> -	if (dwc->edev) {
> +	if (ROLE_SWITCH &&
> +	    device_property_read_bool(dwc->dev, "usb-role-switch")) {
> +		ret = dwc3_setup_role_switch(dwc);
> +		if (ret < 0)
> +			return ret;
> +	} else if (dwc->edev) {
>  		dwc->edev_nb.notifier_call = dwc3_drd_notifier;
>  		ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
>  					       &dwc->edev_nb);
> @@ -531,6 +603,9 @@ void dwc3_drd_exit(struct dwc3 *dwc)
>  {
>  	unsigned long flags;
>  
> +	if (dwc->role_sw)
> +		usb_role_switch_unregister(dwc->role_sw);
> +
>  	if (dwc->edev)
>  		extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST,
>  					   &dwc->edev_nb);
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB
  2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
                   ` (17 preceding siblings ...)
  2020-03-03 17:11 ` [PATCH v7 18/18] arm64: dts: qcom: qcs404-evb: Enable USB controllers Bryan O'Donoghue
@ 2020-03-08  5:23 ` Bjorn Andersson
  2020-03-09  0:02   ` Bryan O'Donoghue
  18 siblings, 1 reply; 26+ messages in thread
From: Bjorn Andersson @ 2020-03-08  5:23 UTC (permalink / raw)
  To: Bryan O'Donoghue
  Cc: linux-arm-msm, linux-usb, gregkh, jackp, balbi, robh, linux-kernel

On Tue 03 Mar 09:11 PST 2020, Bryan O'Donoghue wrote:

> V1:
> This series enables the Primary and Secondary USB controllers on the
> QCS404, associated PHYs, role-switching and DTS descriptions.
> 

Finally took the time to give this a spin on my QCS404 dev board.

Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>


As this touches three different subsystems, and doesn't have have
compile time dependencies between the parts, I would suggest that as you
fix up the build error I reported yesterday you send v8 as three
different series - one per maintainer/subsystem. That way we avoid any
questions about whom should merge what parts and in what order.

Thanks,
Bjorn

> The series takes in a number of patches worked on by a number of people
> over the past few years from downstream, through to previous upstream
> submissions for both of these interfaces. Additional work has been done to
> enable USB role-switching.
> 
> 1. USB SS
>    - extcon has been dropped in favour of gpio-usb-conn as discussed and
>      agreed previously by Jorge, Bjorn, Stephen Boyd and Jack Pham [1].
> 
>    - Regulator API has been updated following suggestions from Bjorn.
>    
>    - Sanitzation of the DT compatible name - dropped "snps" entirely
>      from the name - it made almost no sense to me and doesn't appear
>      consistent with similar naming conventions for Snopsys based IP.
> 
> 2. USB HS
>    - Regulator API changes here.
>    - Dropped "snps" from the namespace for similar reasons as above.
>    - Dropped "28nm" from the namespace, looked superfluous.
>    - Changed "High-Speed" to "Hi-Speed".
>    - [2]
> 
> 3. DWC3 Role switching
>    - At the time usb-gpio-conn was discussed it was mentioned that
>      role-switching was absent from the DWC3 driver.
>    - John Stultz has some patches in-flight for that, that I've included in
>      this series for completeness.
>    - Adds my SoB to relevant patches.
>    - Drops gerrit ChangeId.
> 
> 4. DWC3 usb-gpio-conn
>    Needs to be a child node of the DWC3 driver so some code and DT binding
>    is required for that.
> 
> 5. QCOM-DWC3
>    Since we are role-switching with an external PMIC supplying VBUS we want
>    to skip past toggling VBUS from QCOM-DWC3 controlled registers, so a
>    patch is added to the qcom-dwc3 driver to do that.
> 
> References:
> 
> 1: USB SS PHY for Qualcomm's QCS404
> https://lwn.net/ml/devicetree/20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org/
> 
> 2: Add Synopsys High-Speed USB PHY driver for Qualcomm SoCs
> https://lore.kernel.org/linux-arm-msm/20181127100722.9993-3-shawn.guo@linaro.org/
> 
> https://www.spinics.net/lists/linux-usb/msg190003.html
> 
> V2:
> - Fixes yaml error - Rob's YAML robot
> - Exclusive control of reset in PHY drivers - Philipp Zabel
> 
> V3:
> - Fixes typo generating YAML warning - Rob's YAML robot
> 
> V4:
> 
> https://lore.kernel.org/linux-arm-msm/20200122185610.131930-1-bryan.odonoghue@linaro.org/
> 
> - Churn names of PHYs - Rob Herring
>   Rob questioned the name of the SuperSpeed PHY in V3.
>   Looking at available data 
> 
>   usb-hs-28nm - There are two possible PHYs on 28nm litho node
> 		so it makes sense to name the PHY relating to its relevant
> 		litho node.
> 
>   usb-ss - This is not litho node dependent and is used on  multiple SoCs
> 	   and litho nodes.
> 
> - Drop default mode for role switching - Felipe Balbi
>   Felipe asked if the default mode for role switching was
>   required and the answer is no. It makes no difference
>   becuase the USB ID pin ultimately dictates the mode of operation.
> 
> - Change "gpio_usb_connector" to "connector" - Rob
>   This was a minor change in terms of DTS but, means I need to look for the
>   DTS compatible string as opposed to a label given in the DTS.
>   No matter what the name of the label, this is he right thing to do.
> 
> - Used IS_ENABLED() - Felipe
>   The logic is the same but IS_ENABLED() is used now.
> 
> - Retained example of USB connector in dwc.txt - Rob, Felipe
>   Rob pointed out adding the connector was redundant as the documentation
>   already implies it.
>   Felipe seemed in favour of I think adding the example.
>   I've dropped the documentation of the connector and kept the example.
>   https://lore.kernel.org/linux-arm-msm/20200122185610.131930-7-bryan.odonoghue@linaro.org/
> 
> - Added example of usb-role-switch in dwc3.txt - BOD
>   
> - Incorporated various inputs from Rob on DTS/YAML
>   - Added required:
>   - Added additionalProperties:
>   - Renamed "phy" clock to "ahb"
>   - maxItems dropped as indicated
> 
> V5:
> - https://lkml.org/lkml/2020/2/6/913
> 
> - Adds a notifier to DWC3 - BOD
>   This is done in order to allow propagation of role-switch events from the
>   DWC3 core to an associated binding layer.
> 
> - Re-use the existent EXTCON VBUS power lane toggle logic - Jack Pham
>   Jack flagged this for inclusion and as a result we need to make a
>   small change to the qcom binding layer.
> 
> - Squash DTS changes - BOD
>   I've squashed down some of the DTS changes to stop the patch count in
>   this series going  up any further.
> 
> V6:
> - https://lkml.org/lkml/2020/2/7/632
> 
> - Add RB Jack Pham patch # 11
> 
> - Fix a stale description in git log patch # 10
> 
> V7:
> - https://lkml.org/lkml/2020/2/10/258
> 
> - Adds RB Rob Herring as indicated
> 
> - Updates the naming of the USB SS PHY for the particular SoC.
>   The name of the driver is maintained, as previously mentioned, this
>   IP appears to be in use on the 20nm and 28nm nodes. However taking
>   Rob's feedback on the naming of the SoC specific bit the code being added
>   is specified @ 28nm.
>   If/when we come to add in 20nm for this IP we can add a new compatible
>   for 20nm.
>   Rob Herring
> 
> Bjorn Andersson (1):
>   arm64: dts: qcom: qcs404: Add USB devices and PHYs
> 
> Bryan O'Donoghue (11):
>   dt-bindings: usb: dwc3: Add a gpio-usb-connector example
>   dt-bindings: usb: dwc3: Add a usb-role-switch to the example
>   usb: dwc3: qcom: Add support for usb-conn-gpio connectors
>   usb: dwc3: Add support for usb-conn-gpio connectors
>   usb: dwc3: Add support for a role-switch notifier
>   usb: dwc3: qcom: Enable gpio-usb-conn based role-switching
>   arm64: dts: qcom: qcs404-evb: Define VBUS pins
>   arm64: dts: qcom: qcs404-evb: Define USB ID pin
>   arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator
>   arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage
>   arm64: dts: qcom: qcs404-evb: Enable USB controllers
> 
> Jorge Ramirez-Ortiz (3):
>   dt-bindings: phy: remove qcom-dwc3-usb-phy
>   dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
>   phy: qualcomm: usb: Add SuperSpeed PHY driver
> 
> Shawn Guo (1):
>   phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver
> 
> Sriharsha Allenki (1):
>   dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding
> 
> Yu Chen (1):
>   usb: dwc3: Registering a role switch in the DRD code.
> 
>  .../bindings/phy/qcom,usb-hs-28nm.yaml        |  90 ++++
>  .../devicetree/bindings/phy/qcom,usb-ss.yaml  |  83 ++++
>  .../bindings/phy/qcom-dwc3-usb-phy.txt        |  37 --
>  .../devicetree/bindings/usb/dwc3.txt          |   9 +
>  arch/arm64/boot/dts/qcom/qcs404-evb.dtsi      |  90 +++-
>  arch/arm64/boot/dts/qcom/qcs404.dtsi          | 100 +++++
>  drivers/phy/qualcomm/Kconfig                  |  20 +
>  drivers/phy/qualcomm/Makefile                 |   2 +
>  drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c   | 415 ++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-usb-ss.c        | 246 +++++++++++
>  drivers/usb/dwc3/core.h                       |  22 +
>  drivers/usb/dwc3/drd.c                        | 119 ++++-
>  drivers/usb/dwc3/dwc3-qcom.c                  |  31 +-
>  13 files changed, 1223 insertions(+), 41 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
>  delete mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
>  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
>  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c
> 
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB
  2020-03-08  5:23 ` [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bjorn Andersson
@ 2020-03-09  0:02   ` Bryan O'Donoghue
  0 siblings, 0 replies; 26+ messages in thread
From: Bryan O'Donoghue @ 2020-03-09  0:02 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: linux-arm-msm, linux-usb, gregkh, jackp, balbi, robh, linux-kernel

On 08/03/2020 05:23, Bjorn Andersson wrote:
> On Tue 03 Mar 09:11 PST 2020, Bryan O'Donoghue wrote:
> 
>> V1:
>> This series enables the Primary and Secondary USB controllers on the
>> QCS404, associated PHYs, role-switching and DTS descriptions.
>>
> 
> Finally took the time to give this a spin on my QCS404 dev board.
> 
> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>

thanks !

> 
> As this touches three different subsystems, and doesn't have have
> compile time dependencies between the parts, I would suggest that as you
> fix up the build error I reported yesterday you send v8 as three
> different series - one per maintainer/subsystem. That way we avoid any
> questions about whom should merge what parts and in what order.

ack, will do.

---
bod

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [PATCH v7 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver
  2020-03-03 17:11 ` [PATCH v7 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver Bryan O'Donoghue
@ 2020-03-09 10:49   ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 26+ messages in thread
From: Kishon Vijay Abraham I @ 2020-03-09 10:49 UTC (permalink / raw)
  To: Bryan O'Donoghue, linux-arm-msm, linux-usb, gregkh, jackp,
	balbi, bjorn.andersson, robh
  Cc: linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
	Sriharsha Allenki's, Andy Gross, Philipp Zabel

Hi,

On 03/03/20 10:41 pm, Bryan O'Donoghue wrote:
> From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> 
> Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the
> 20nm and 28nm process nodes.
> 
> Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code.
> 
> [bod: Removed dependency on extcon.
>       Switched to gpio-usb-conn to handle VBUS On/Off
>       Switched to usb-role-switch to bind gpio-usb-conn to DWC3]
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
> Cc: Sriharsha Allenki's <sallenki@codeaurora.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

I only have 02, 03, and 05 of this patch series. Can you split the
series and send all the patches targeted to PHY tree separately?

Thanks
Kishon

> ---
>  drivers/phy/qualcomm/Kconfig           |   9 +
>  drivers/phy/qualcomm/Makefile          |   1 +
>  drivers/phy/qualcomm/phy-qcom-usb-ss.c | 246 +++++++++++++++++++++++++
>  3 files changed, 256 insertions(+)
>  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c
> 
> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
> index 9c56a7216f72..98674ed094d9 100644
> --- a/drivers/phy/qualcomm/Kconfig
> +++ b/drivers/phy/qualcomm/Kconfig
> @@ -102,3 +102,12 @@ config PHY_QCOM_USB_HS_28NM
>  	  High-Speed PHY driver. This driver supports the Hi-Speed PHY which
>  	  is usually paired with either the ChipIdea or Synopsys DWC3 USB
>  	  IPs on MSM SOCs.
> +
> +config PHY_QCOM_USB_SS
> +	tristate "Qualcomm USB Super-Speed PHY driver"
> +	depends on ARCH_QCOM || COMPILE_TEST
> +	depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Super-Speed USB transceiver on various
> +	  Qualcomm chipsets.
> diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
> index a4dab5329de0..1f14aeacbd70 100644
> --- a/drivers/phy/qualcomm/Makefile
> +++ b/drivers/phy/qualcomm/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_20NM)		+= phy-qcom-ufs-qmp-20nm.o
>  obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o
>  obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o
>  obj-$(CONFIG_PHY_QCOM_USB_HS_28NM)	+= phy-qcom-usb-hs-28nm.o
> +obj-$(CONFIG_PHY_QCOM_USB_SS)		+= phy-qcom-usb-ss.o
> diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
> new file mode 100644
> index 000000000000..a3a6d3ce7ea1
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
> @@ -0,0 +1,246 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2018-2020, Linaro Limited
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#define PHY_CTRL0			0x6C
> +#define PHY_CTRL1			0x70
> +#define PHY_CTRL2			0x74
> +#define PHY_CTRL4			0x7C
> +
> +/* PHY_CTRL bits */
> +#define REF_PHY_EN			BIT(0)
> +#define LANE0_PWR_ON			BIT(2)
> +#define SWI_PCS_CLK_SEL			BIT(4)
> +#define TST_PWR_DOWN			BIT(4)
> +#define PHY_RESET			BIT(7)
> +
> +#define NUM_BULK_CLKS			3
> +#define NUM_BULK_REGS			2
> +
> +struct ssphy_priv {
> +	void __iomem *base;
> +	struct device *dev;
> +	struct reset_control *reset_com;
> +	struct reset_control *reset_phy;
> +	struct regulator_bulk_data regs[NUM_BULK_REGS];
> +	struct clk_bulk_data clks[NUM_BULK_CLKS];
> +	enum phy_mode mode;
> +};
> +
> +static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val)
> +{
> +	writel((readl(addr) & ~mask) | val, addr);
> +}
> +
> +static int qcom_ssphy_do_reset(struct ssphy_priv *priv)
> +{
> +	int ret;
> +
> +	if (!priv->reset_com) {
> +		qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET,
> +				   PHY_RESET);
> +		usleep_range(10, 20);
> +		qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0);
> +	} else {
> +		ret = reset_control_assert(priv->reset_com);
> +		if (ret) {
> +			dev_err(priv->dev, "Failed to assert reset com\n");
> +			return ret;
> +		}
> +
> +		ret = reset_control_assert(priv->reset_phy);
> +		if (ret) {
> +			dev_err(priv->dev, "Failed to assert reset phy\n");
> +			return ret;
> +		}
> +
> +		usleep_range(10, 20);
> +
> +		ret = reset_control_deassert(priv->reset_com);
> +		if (ret) {
> +			dev_err(priv->dev, "Failed to deassert reset com\n");
> +			return ret;
> +		}
> +
> +		ret = reset_control_deassert(priv->reset_phy);
> +		if (ret) {
> +			dev_err(priv->dev, "Failed to deassert reset phy\n");
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int qcom_ssphy_power_on(struct phy *phy)
> +{
> +	struct ssphy_priv *priv = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks);
> +	if (ret)
> +		goto err_disable_regulator;
> +
> +	ret = qcom_ssphy_do_reset(priv);
> +	if (ret)
> +		goto err_disable_clock;
> +
> +	writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0);
> +	qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON);
> +	qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN);
> +	qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0);
> +
> +	return 0;
> +err_disable_clock:
> +	clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
> +err_disable_regulator:
> +	regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
> +
> +	return ret;
> +}
> +
> +static int qcom_ssphy_power_off(struct phy *phy)
> +{
> +	struct ssphy_priv *priv = phy_get_drvdata(phy);
> +
> +	qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0);
> +	qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0);
> +	qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN);
> +
> +	clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
> +	regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
> +
> +	return 0;
> +}
> +
> +static int qcom_ssphy_init_clock(struct ssphy_priv *priv)
> +{
> +	priv->clks[0].id = "ref";
> +	priv->clks[1].id = "ahb";
> +	priv->clks[2].id = "pipe";
> +
> +	return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks);
> +}
> +
> +static int qcom_ssphy_init_regulator(struct ssphy_priv *priv)
> +{
> +	int ret;
> +
> +	priv->regs[0].supply = "vdd";
> +	priv->regs[1].supply = "vdda1p8";
> +	ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs);
> +	if (ret) {
> +		if (ret != -EPROBE_DEFER)
> +			dev_err(priv->dev, "Failed to get regulators\n");
> +		return ret;
> +	}
> +
> +	return ret;
> +}
> +
> +static int qcom_ssphy_init_reset(struct ssphy_priv *priv)
> +{
> +	priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com");
> +	if (IS_ERR(priv->reset_com)) {
> +		dev_err(priv->dev, "Failed to get reset control com\n");
> +		return PTR_ERR(priv->reset_com);
> +	}
> +
> +	if (priv->reset_com) {
> +		/* if reset_com is present, reset_phy is no longer optional */
> +		priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy");
> +		if (IS_ERR(priv->reset_phy)) {
> +			dev_err(priv->dev, "Failed to get reset control phy\n");
> +			return PTR_ERR(priv->reset_phy);
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops qcom_ssphy_ops = {
> +	.power_off = qcom_ssphy_power_off,
> +	.power_on = qcom_ssphy_power_on,
> +	.owner = THIS_MODULE,
> +};
> +
> +static int qcom_ssphy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct phy_provider *provider;
> +	struct ssphy_priv *priv;
> +	struct phy *phy;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->dev = dev;
> +	priv->mode = PHY_MODE_INVALID;
> +
> +	priv->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	ret = qcom_ssphy_init_clock(priv);
> +	if (ret)
> +		return ret;
> +
> +	ret = qcom_ssphy_init_reset(priv);
> +	if (ret)
> +		return ret;
> +
> +	ret = qcom_ssphy_init_regulator(priv);
> +	if (ret)
> +		return ret;
> +
> +	phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops);
> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "Failed to create the SS phy\n");
> +		return PTR_ERR(phy);
> +	}
> +
> +	phy_set_drvdata(phy, priv);
> +
> +	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static const struct of_device_id qcom_ssphy_match[] = {
> +	{ .compatible = "qcom,usb-ss-28nm-phy", },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_ssphy_match);
> +
> +static struct platform_driver qcom_ssphy_driver = {
> +	.probe		= qcom_ssphy_probe,
> +	.driver = {
> +		.name	= "qcom-usb-ssphy",
> +		.of_match_table = qcom_ssphy_match,
> +	},
> +};
> +module_platform_driver(qcom_ssphy_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver");
> +MODULE_LICENSE("GPL v2");
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

end of thread, other threads:[~2020-03-09 10:45 UTC | newest]

Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-03 17:11 [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 02/18] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 03/18] phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Bryan O'Donoghue
2020-03-04 16:17   ` Rob Herring
2020-03-03 17:11 ` [PATCH v7 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver Bryan O'Donoghue
2020-03-09 10:49   ` Kishon Vijay Abraham I
2020-03-03 17:11 ` [PATCH v7 06/18] usb: dwc3: Registering a role switch in the DRD code Bryan O'Donoghue
2020-03-07  7:20   ` Bjorn Andersson
2020-03-03 17:11 ` [PATCH v7 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example Bryan O'Donoghue
2020-03-04 14:57   ` Rob Herring
2020-03-04 16:24     ` Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 08/18] dt-bindings: usb: dwc3: Add a usb-role-switch to the example Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 09/18] usb: dwc3: qcom: Add support for usb-conn-gpio connectors Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 10/18] usb: dwc3: " Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 11/18] usb: dwc3: Add support for a role-switch notifier Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 12/18] usb: dwc3: qcom: Enable gpio-usb-conn based role-switching Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 13/18] arm64: dts: qcom: qcs404: Add USB devices and PHYs Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 14/18] arm64: dts: qcom: qcs404-evb: Define VBUS pins Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 15/18] arm64: dts: qcom: qcs404-evb: Define USB ID pin Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 16/18] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 17/18] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Bryan O'Donoghue
2020-03-03 17:11 ` [PATCH v7 18/18] arm64: dts: qcom: qcs404-evb: Enable USB controllers Bryan O'Donoghue
2020-03-08  5:23 ` [PATCH v7 00/18] Enable Qualcomm QCS 404 HS/SS USB Bjorn Andersson
2020-03-09  0:02   ` Bryan O'Donoghue

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