From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8281DC3F2C6 for ; Tue, 10 Mar 2020 15:48:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 688EF20866 for ; Tue, 10 Mar 2020 15:48:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726646AbgCJPsd (ORCPT ); Tue, 10 Mar 2020 11:48:33 -0400 Received: from muru.com ([72.249.23.125]:59512 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726477AbgCJPsd (ORCPT ); Tue, 10 Mar 2020 11:48:33 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 64DAF810A; Tue, 10 Mar 2020 15:49:18 +0000 (UTC) Date: Tue, 10 Mar 2020 08:48:29 -0700 From: Tony Lindgren To: Tero Kristo Cc: Roger Quadros , hch@lst.de, robin.murphy@arm.com, robh+dt@kernel.org, nm@ti.com, nsekhar@ti.com, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: dts: dra7: Add bus_dma_limit for L3 bus Message-ID: <20200310154829.GS37466@atomide.com> References: <20200310115309.31354-1-rogerq@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Tero Kristo [200310 14:46]: > On 10/03/2020 13:53, Roger Quadros wrote: > > The L3 interconnect can access only 32-bits of address. > > Add the dma-ranges property to reflect this limit. > > > > This will ensure that no device under L3 is > > given > 32-bit address for DMA. > > > > Issue was observed only with SATA on DRA7-EVM with 4GB RAM > > and CONFIG_ARM_LPAE enabled. This is because the controller > > can perform 64-bit DMA and was setting the dma_mask to 64-bit. > > > > Setting the correct bus_dma_limit fixes the issue. > > This seems kind of messy to modify almost every DT node because of this.... > Are you sure this is the only way to get it done? No way to modify the sata > node only which is impacted somehow? > > Also, what if you just pass 0xffffffff to the dma-ranges property? That > would avoid modifying every node I guess. Also, I think these interconnects are not limited to 32-bit access. So yeah I too would prefer a top level dma-ranges property assuming that works. I guess there dma-ranges should not be 0xffffffff though if limited to 2GB :) Regards, Tony