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From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
To: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Alexey Brodkin <Alexey.Brodkin@synopsys.com>,
	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Subject: [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first
Date: Wed, 11 Mar 2020 16:41:13 +0300	[thread overview]
Message-ID: <20200311134115.13257-2-Eugeniy.Paltsev@synopsys.com> (raw)
In-Reply-To: <20200311134115.13257-1-Eugeniy.Paltsev@synopsys.com>

If PLL is bypassed the EN (enable) bit has no effect on
output clock.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
 drivers/clk/clk-hsdk-pll.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 97d1e8c35b71..b47a559f3528 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -172,14 +172,14 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
 
 	dev_dbg(clk->dev, "current configuration: %#x\n", val);
 
-	/* Check if PLL is disabled */
-	if (val & CGU_PLL_CTRL_PD)
-		return 0;
-
 	/* Check if PLL is bypassed */
 	if (val & CGU_PLL_CTRL_BYPASS)
 		return parent_rate;
 
+	/* Check if PLL is disabled */
+	if (val & CGU_PLL_CTRL_PD)
+		return 0;
+
 	/* input divider = reg.idiv + 1 */
 	idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
 	/* fb divider = 2*(reg.fbdiv + 1) */
-- 
2.21.1


  reply	other threads:[~2020-03-11 13:41 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-11 13:41 [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management Eugeniy Paltsev
2020-03-11 13:41 ` Eugeniy Paltsev [this message]
2020-05-29  4:07   ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Stephen Boyd
2020-03-11 13:41 ` [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing Eugeniy Paltsev
2020-05-29  4:07   ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock Eugeniy Paltsev
2020-05-29  4:07   ` Stephen Boyd

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