[PATCH v14 0/2] Add dts and bindings update for i.MX8QM/QXP JPEG codec

[PATCH v14 0/2] Add dts and bindings update for i.MX8QM/QXP JPEG codec

[Mirela Rabulea (OSS)]

From: Mirela Rabulea <mirela.rabulea@nxp.com>

Add the dts files for i.MX8QM/QXP JPEG codec.
The bindings for i.MX8QXP were already upstream, only update with i.MX8QM compatible.

Mirela Rabulea (2):
  media: dt-bindings: imx-jpeg: Add compatible for i.MX8QM JPEG codec
  arm64: dts: imx8: Add jpeg encoder/decoder nodes

 .../bindings/media/nxp,imx8-jpeg.yaml         | 19 +++--
 .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 80 +++++++++++++++++++
 .../boot/dts/freescale/imx8qm-ss-img.dtsi     | 12 +++
 arch/arm64/boot/dts/freescale/imx8qm.dtsi     |  2 +
 .../boot/dts/freescale/imx8qxp-ss-img.dtsi    | 13 +++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  2 +
 6 files changed, 121 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi

-- 
2.17.1

[PATCH v14 1/2] media: dt-bindings: imx-jpeg: Add compatible for i.MX8QM JPEG codec

[Mirela Rabulea (OSS)]

From: Mirela Rabulea <mirela.rabulea@nxp.com>

Add two more compatibles: "nxp,imx8qm-jpgdec" and " nxp,imx8qm-jpgenc".
Also update the compatible property to ensure mutually exclusive usage of
encoder and decoder compatibles.
Update examples.

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
---
Changes in v14:
  Address feedback from Aisheng Dong, do not use anyOf

 .../bindings/media/nxp,imx8-jpeg.yaml         | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
index 5d13cbb5251b..3cc6f42aeb76 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
@@ -16,12 +16,17 @@ description: |-
 
 properties:
   compatible:
-    items:
-      - enum:
-            # JPEG decoder
-          - nxp,imx8qxp-jpgdec
-            # JPEG encoder
-          - nxp,imx8qxp-jpgenc
+    oneOf:
+      - items:
+          enum:
+            - nxp,imx8qxp-jpgdec
+            - nxp,imx8qxp-jpgenc
+      - items:
+          - const: nxp,imx8qm-jpgdec
+          - const: nxp,imx8qxp-jpgdec
+      - items:
+          - const: nxp,imx8qm-jpgenc
+          - const: nxp,imx8qxp-jpgenc
 
   reg:
     maxItems: 1
@@ -69,7 +74,7 @@ examples:
     };
 
     jpegenc: jpegenc@58450000 {
-        compatible = "nxp,imx8qxp-jpgenc";
+        compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
         reg = <0x58450000 0x00050000 >;
         interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.17.1

[PATCH v14 2/2] arm64: dts: imx8: Add jpeg encoder/decoder nodes

[Mirela Rabulea (OSS)]

From: Mirela Rabulea <mirela.rabulea@nxp.com>

Add dts for imaging subsytem, include jpeg nodes here.
Tested on imx8qxp/qm.

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
---
Changes in v14:
  Address feedback from Aisheng Dong and Ezequiel Garcia:
    - use imx8 instead of imx in patch subject
    - keep jpeg and LPCGs used by jpeg enabled by default in platform dts (no change here)

 .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 80 +++++++++++++++++++
 .../boot/dts/freescale/imx8qm-ss-img.dtsi     | 12 +++
 arch/arm64/boot/dts/freescale/imx8qm.dtsi     |  2 +
 .../boot/dts/freescale/imx8qxp-ss-img.dtsi    | 13 +++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  2 +
 5 files changed, 109 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
new file mode 100644
index 000000000000..a90654155a88
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ * Zhou Guoniu <guoniu.zhou@nxp.com>
+ */
+img_subsys: bus@58000000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x58000000 0x0 0x58000000 0x1000000>;
+
+	img_ipg_clk: clock-img-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		clock-output-names = "img_ipg_clk";
+	};
+
+	jpegdec: jpegdec@58400000 {
+		reg = <0x58400000 0x00050000>;
+		interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
+			 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
+				  <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
+		assigned-clock-rates = <200000000>, <200000000>;
+		power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
+				<&pd IMX_SC_R_MJPEG_DEC_S0>,
+				<&pd IMX_SC_R_MJPEG_DEC_S1>,
+				<&pd IMX_SC_R_MJPEG_DEC_S2>,
+				<&pd IMX_SC_R_MJPEG_DEC_S3>;
+	};
+
+	jpegenc: jpegenc@58450000 {
+		reg = <0x58450000 0x00050000>;
+		interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
+			 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
+				  <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
+		assigned-clock-rates = <200000000>, <200000000>;
+		power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
+				<&pd IMX_SC_R_MJPEG_ENC_S0>,
+				<&pd IMX_SC_R_MJPEG_ENC_S1>,
+				<&pd IMX_SC_R_MJPEG_ENC_S2>,
+				<&pd IMX_SC_R_MJPEG_ENC_S3>;
+	};
+
+	img_jpeg_dec_lpcg: clock-controller@585d0000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x585d0000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>,
+				<IMX_LPCG_CLK_4>;
+		clock-output-names = "img_jpeg_dec_lpcg_clk",
+				     "img_jpeg_dec_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
+	};
+
+	img_jpeg_enc_lpcg: clock-controller@585f0000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x585f0000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>,
+				<IMX_LPCG_CLK_4>;
+		clock-output-names = "img_jpeg_enc_lpcg_clk",
+				     "img_jpeg_enc_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
new file mode 100644
index 000000000000..7764b4146e0a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&jpegdec {
+	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
+};
+
+&jpegenc {
+	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 12cd059b339b..aebbe2b84aa1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -166,11 +166,13 @@
 	};
 
 	/* sorted in register address */
+	#include "imx8-ss-img.dtsi"
 	#include "imx8-ss-dma.dtsi"
 	#include "imx8-ss-conn.dtsi"
 	#include "imx8-ss-lsio.dtsi"
 };
 
+#include "imx8qm-ss-img.dtsi"
 #include "imx8qm-ss-dma.dtsi"
 #include "imx8qm-ss-conn.dtsi"
 #include "imx8qm-ss-lsio.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
new file mode 100644
index 000000000000..3a087317591d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&jpegdec {
+	compatible = "nxp,imx8qxp-jpgdec";
+};
+
+&jpegenc {
+	compatible = "nxp,imx8qxp-jpgenc";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 1e6b4995091e..a625fb6bdc62 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -258,12 +258,14 @@
 	};
 
 	/* sorted in register address */
+	#include "imx8-ss-img.dtsi"
 	#include "imx8-ss-adma.dtsi"
 	#include "imx8-ss-conn.dtsi"
 	#include "imx8-ss-ddr.dtsi"
 	#include "imx8-ss-lsio.dtsi"
 };
 
+#include "imx8qxp-ss-img.dtsi"
 #include "imx8qxp-ss-adma.dtsi"
 #include "imx8qxp-ss-conn.dtsi"
 #include "imx8qxp-ss-lsio.dtsi"
-- 
2.17.1

RE: [PATCH v14 1/2] media: dt-bindings: imx-jpeg: Add compatible for i.MX8QM JPEG codec

[Aisheng Dong]

> From: Mirela Rabulea (OSS) <mirela.rabulea@oss.nxp.com>
> Sent: Saturday, June 19, 2021 10:36 PM
> Subject: [PATCH v14 1/2] media: dt-bindings: imx-jpeg: Add compatible for
> i.MX8QM JPEG codec

Nitpick: we usually put dt-bindings first.
e.g.
dt-bindings: media: xxx

Anyway it's small problem, so:

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> 
> Add two more compatibles: "nxp,imx8qm-jpgdec" and " nxp,imx8qm-jpgenc".
> Also update the compatible property to ensure mutually exclusive usage of
> encoder and decoder compatibles.
> Update examples.
> 
> Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
> ---
> Changes in v14:
>   Address feedback from Aisheng Dong, do not use anyOf
> 
>  .../bindings/media/nxp,imx8-jpeg.yaml         | 19 ++++++++++++-------
>  1 file changed, 12 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
> b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
> index 5d13cbb5251b..3cc6f42aeb76 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
> @@ -16,12 +16,17 @@ description: |-
> 
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -            # JPEG decoder
> -          - nxp,imx8qxp-jpgdec
> -            # JPEG encoder
> -          - nxp,imx8qxp-jpgenc
> +    oneOf:
> +      - items:
> +          enum:
> +            - nxp,imx8qxp-jpgdec
> +            - nxp,imx8qxp-jpgenc
> +      - items:
> +          - const: nxp,imx8qm-jpgdec
> +          - const: nxp,imx8qxp-jpgdec
> +      - items:
> +          - const: nxp,imx8qm-jpgenc
> +          - const: nxp,imx8qxp-jpgenc
> 
>    reg:
>      maxItems: 1
> @@ -69,7 +74,7 @@ examples:
>      };
> 
>      jpegenc: jpegenc@58450000 {
> -        compatible = "nxp,imx8qxp-jpgenc";
> +        compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
>          reg = <0x58450000 0x00050000 >;
>          interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
>                       <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> --
> 2.17.1

RE: [PATCH v14 2/2] arm64: dts: imx8: Add jpeg encoder/decoder nodes

[Aisheng Dong]

> From: Mirela Rabulea (OSS) <mirela.rabulea@oss.nxp.com>
> Sent: Saturday, June 19, 2021 10:36 PM
> 
> Add dts for imaging subsytem, include jpeg nodes here.
> Tested on imx8qxp/qm.
> 
> Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
> Changes in v14:
>   Address feedback from Aisheng Dong and Ezequiel Garcia:
>     - use imx8 instead of imx in patch subject
>     - keep jpeg and LPCGs used by jpeg enabled by default in platform dts (no
> change here)
> 
>  .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 80 +++++++++++++++++++
>  .../boot/dts/freescale/imx8qm-ss-img.dtsi     | 12 +++
>  arch/arm64/boot/dts/freescale/imx8qm.dtsi     |  2 +
>  .../boot/dts/freescale/imx8qxp-ss-img.dtsi    | 13 +++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  2 +
>  5 files changed, 109 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> new file mode 100644
> index 000000000000..a90654155a88
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + * Zhou Guoniu <guoniu.zhou@nxp.com>
> + */
> +img_subsys: bus@58000000 {
> +	compatible = "simple-bus";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x58000000 0x0 0x58000000 0x1000000>;
> +
> +	img_ipg_clk: clock-img-ipg {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <200000000>;
> +		clock-output-names = "img_ipg_clk";
> +	};
> +
> +	jpegdec: jpegdec@58400000 {
> +		reg = <0x58400000 0x00050000>;
> +		interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
> +			 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
> +				  <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
> +		assigned-clock-rates = <200000000>, <200000000>;
> +		power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S0>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S1>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S2>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S3>;
> +	};
> +
> +	jpegenc: jpegenc@58450000 {
> +		reg = <0x58450000 0x00050000>;
> +		interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
> +			 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
> +				  <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
> +		assigned-clock-rates = <200000000>, <200000000>;
> +		power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S0>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S1>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S2>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S3>;
> +	};
> +
> +	img_jpeg_dec_lpcg: clock-controller@585d0000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x585d0000 0x10000>;
> +		#clock-cells = <1>;
> +		clocks = <&img_ipg_clk>, <&img_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>,
> +				<IMX_LPCG_CLK_4>;
> +		clock-output-names = "img_jpeg_dec_lpcg_clk",
> +				     "img_jpeg_dec_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
> +	};
> +
> +	img_jpeg_enc_lpcg: clock-controller@585f0000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x585f0000 0x10000>;
> +		#clock-cells = <1>;
> +		clocks = <&img_ipg_clk>, <&img_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>,
> +				<IMX_LPCG_CLK_4>;
> +		clock-output-names = "img_jpeg_enc_lpcg_clk",
> +				     "img_jpeg_enc_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> new file mode 100644
> index 000000000000..7764b4146e0a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +&jpegdec {
> +	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec"; };
> +
> +&jpegenc {
> +	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc"; };
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> index 12cd059b339b..aebbe2b84aa1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> @@ -166,11 +166,13 @@
>  	};
> 
>  	/* sorted in register address */
> +	#include "imx8-ss-img.dtsi"
>  	#include "imx8-ss-dma.dtsi"
>  	#include "imx8-ss-conn.dtsi"
>  	#include "imx8-ss-lsio.dtsi"
>  };
> 
> +#include "imx8qm-ss-img.dtsi"
>  #include "imx8qm-ss-dma.dtsi"
>  #include "imx8qm-ss-conn.dtsi"
>  #include "imx8qm-ss-lsio.dtsi"
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> new file mode 100644
> index 000000000000..3a087317591d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + *	Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +&jpegdec {
> +	compatible = "nxp,imx8qxp-jpgdec";
> +};
> +
> +&jpegenc {
> +	compatible = "nxp,imx8qxp-jpgenc";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 1e6b4995091e..a625fb6bdc62 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -258,12 +258,14 @@
>  	};
> 
>  	/* sorted in register address */
> +	#include "imx8-ss-img.dtsi"
>  	#include "imx8-ss-adma.dtsi"
>  	#include "imx8-ss-conn.dtsi"
>  	#include "imx8-ss-ddr.dtsi"
>  	#include "imx8-ss-lsio.dtsi"
>  };
> 
> +#include "imx8qxp-ss-img.dtsi"
>  #include "imx8qxp-ss-adma.dtsi"
>  #include "imx8qxp-ss-conn.dtsi"
>  #include "imx8qxp-ss-lsio.dtsi"
> --
> 2.17.1

Re: [PATCH v14 1/2] media: dt-bindings: imx-jpeg: Add compatible for i.MX8QM JPEG codec

[Rob Herring]

On Sat, 19 Jun 2021 17:36:10 +0300, Mirela Rabulea (OSS) wrote:
> From: Mirela Rabulea <mirela.rabulea@nxp.com>
> 
> Add two more compatibles: "nxp,imx8qm-jpgdec" and " nxp,imx8qm-jpgenc".
> Also update the compatible property to ensure mutually exclusive usage of
> encoder and decoder compatibles.
> Update examples.
> 
> Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
> ---
> Changes in v14:
>   Address feedback from Aisheng Dong, do not use anyOf
> 
>  .../bindings/media/nxp,imx8-jpeg.yaml         | 19 ++++++++++++-------
>  1 file changed, 12 insertions(+), 7 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v14 0/2] Add dts and bindings update for i.MX8QM/QXP JPEG codec

[Shawn Guo]

On Sat, Jun 19, 2021 at 05:36:09PM +0300, Mirela Rabulea (OSS) wrote:
> From: Mirela Rabulea <mirela.rabulea@nxp.com>
> 
> Add the dts files for i.MX8QM/QXP JPEG codec.
> The bindings for i.MX8QXP were already upstream, only update with i.MX8QM compatible.
> 
> Mirela Rabulea (2):
>   media: dt-bindings: imx-jpeg: Add compatible for i.MX8QM JPEG codec

I fixed the prefix as Aisheng suggested.

>   arm64: dts: imx8: Add jpeg encoder/decoder nodes

Applied both, thanks.

Shawn

Re: [PATCH v14 2/2] arm64: dts: imx8: Add jpeg encoder/decoder nodes

[Hans Verkuil]

Hi Mirela,

On 19/06/2021 16:36, Mirela Rabulea (OSS) wrote:
> From: Mirela Rabulea <mirela.rabulea@nxp.com>
> 
> Add dts for imaging subsytem, include jpeg nodes here.
> Tested on imx8qxp/qm.

I've posted a pull request for the first bindings patch for v5.16, so this dts patch can be merged
through whatever tree takes such dts patches.

Regards,

	Hans

> 
> Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
> ---
> Changes in v14:
>   Address feedback from Aisheng Dong and Ezequiel Garcia:
>     - use imx8 instead of imx in patch subject
>     - keep jpeg and LPCGs used by jpeg enabled by default in platform dts (no change here)
> 
>  .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 80 +++++++++++++++++++
>  .../boot/dts/freescale/imx8qm-ss-img.dtsi     | 12 +++
>  arch/arm64/boot/dts/freescale/imx8qm.dtsi     |  2 +
>  .../boot/dts/freescale/imx8qxp-ss-img.dtsi    | 13 +++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  2 +
>  5 files changed, 109 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> new file mode 100644
> index 000000000000..a90654155a88
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + * Zhou Guoniu <guoniu.zhou@nxp.com>
> + */
> +img_subsys: bus@58000000 {
> +	compatible = "simple-bus";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x58000000 0x0 0x58000000 0x1000000>;
> +
> +	img_ipg_clk: clock-img-ipg {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <200000000>;
> +		clock-output-names = "img_ipg_clk";
> +	};
> +
> +	jpegdec: jpegdec@58400000 {
> +		reg = <0x58400000 0x00050000>;
> +		interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
> +			 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
> +				  <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
> +		assigned-clock-rates = <200000000>, <200000000>;
> +		power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S0>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S1>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S2>,
> +				<&pd IMX_SC_R_MJPEG_DEC_S3>;
> +	};
> +
> +	jpegenc: jpegenc@58450000 {
> +		reg = <0x58450000 0x00050000>;
> +		interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&img_jpeg_enc_lpcg IMX_LPC[GIT PULL FOR v5.16]G_CLK_0>,
> +			 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
> +				  <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
> +		assigned-clock-rates = <200000000>, <200000000>;
> +		power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S0>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S1>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S2>,
> +				<&pd IMX_SC_R_MJPEG_ENC_S3>;
> +	};
> +
> +	img_jpeg_dec_lpcg: clock-controller@585d0000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x585d0000 0x10000>;
> +		#clock-cells = <1>;
> +		clocks = <&img_ipg_clk>, <&img_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>,
> +				<IMX_LPCG_CLK_4>;
> +		clock-output-names = "img_jpeg_dec_lpcg_clk",
> +				     "img_jpeg_dec_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
> +	};
> +
> +	img_jpeg_enc_lpcg: clock-controller@585f0000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x585f0000 0x10000>;
> +		#clock-cells = <1>;
> +		clocks = <&img_ipg_clk>, <&img_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>,
> +				<IMX_LPCG_CLK_4>;
> +		clock-output-names = "img_jpeg_enc_lpcg_clk",
> +				     "img_jpeg_enc_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> new file mode 100644
> index 000000000000..7764b4146e0a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +&jpegdec {
> +	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
> +};
> +
> +&jpegenc {
> +	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> index 12cd059b339b..aebbe2b84aa1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> @@ -166,11 +166,13 @@
>  	};
>  
>  	/* sorted in register address */
> +	#include "imx8-ss-img.dtsi"
>  	#include "imx8-ss-dma.dtsi"
>  	#include "imx8-ss-conn.dtsi"
>  	#include "imx8-ss-lsio.dtsi"
>  };
>  
> +#include "imx8qm-ss-img.dtsi"
>  #include "imx8qm-ss-dma.dtsi"
>  #include "imx8qm-ss-conn.dtsi"
>  #include "imx8qm-ss-lsio.dtsi"
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> new file mode 100644
> index 000000000000..3a087317591d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + *	Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +&jpegdec {
> +	compatible = "nxp,imx8qxp-jpgdec";
> +};
> +
> +&jpegenc {
> +	compatible = "nxp,imx8qxp-jpgenc";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 1e6b4995091e..a625fb6bdc62 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -258,12 +258,14 @@
>  	};
>  
>  	/* sorted in register address */
> +	#include "imx8-ss-img.dtsi"
>  	#include "imx8-ss-adma.dtsi"
>  	#include "imx8-ss-conn.dtsi"
>  	#include "imx8-ss-ddr.dtsi"
>  	#include "imx8-ss-lsio.dtsi"
>  };
>  
> +#include "imx8qxp-ss-img.dtsi"
>  #include "imx8qxp-ss-adma.dtsi"
>  #include "imx8qxp-ss-conn.dtsi"
>  #include "imx8qxp-ss-lsio.dtsi"
> 

Re: [EXT] Re: [PATCH v14 2/2] arm64: dts: imx8: Add jpeg encoder/decoder nodes

[Mirela Rabulea]

Hi Hans,

On Tue, 2021-09-14 at 09:11 +0200, Hans Verkuil wrote:
> Caution: EXT Email
> 
> Hi Mirela,
> 
> On 19/06/2021 16:36, Mirela Rabulea (OSS) wrote:
> > From: Mirela Rabulea <mirela.rabulea@nxp.com>
> > 
> > Add dts for imaging subsytem, include jpeg nodes here.
> > Tested on imx8qxp/qm.
> 
> I've posted a pull request for the first bindings patch for v5.16, so
> this dts patch can be merged
> through whatever tree takes such dts patches.

Thanks for the notice. I see the patch is already in linux-next. Any
 more action required from my behalf?

Regards,
Mirela

> 
> Regards,
> 
>         Hans
> 
> > Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
> > ---
> > Changes in v14:
> >   Address feedback from Aisheng Dong and Ezequiel Garcia:
> >     - use imx8 instead of imx in patch subject
> >     - keep jpeg and LPCGs used by jpeg enabled by default in
> > platform dts (no change here)
> > 
> >  .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 80
> > +++++++++++++++++++
> >  .../boot/dts/freescale/imx8qm-ss-img.dtsi     | 12 +++
> >  arch/arm64/boot/dts/freescale/imx8qm.dtsi     |  2 +
> >  .../boot/dts/freescale/imx8qxp-ss-img.dtsi    | 13 +++
> >  arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  2 +
> >  5 files changed, 109 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-
> > img.dtsi
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-
> > img.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> > new file mode 100644
> > index 000000000000..a90654155a88
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> > @@ -0,0 +1,80 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + * Zhou Guoniu <guoniu.zhou@nxp.com>
> > + */
> > +img_subsys: bus@58000000 {
> > +     compatible = "simple-bus";
> > +     #address-cells = <1>;
> > +     #size-cells = <1>;
> > +     ranges = <0x58000000 0x0 0x58000000 0x1000000>;
> > +
> > +     img_ipg_clk: clock-img-ipg {
> > +             compatible = "fixed-clock";
> > +             #clock-cells = <0>;
> > +             clock-frequency = <200000000>;
> > +             clock-output-names = "img_ipg_clk";
> > +     };
> > +
> > +     jpegdec: jpegdec@58400000 {
> > +             reg = <0x58400000 0x00050000>;
> > +             interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> > +             clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
> > +                      <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
> > +             clock-names = "per", "ipg";
> > +             assigned-clocks = <&img_jpeg_dec_lpcg
> > IMX_LPCG_CLK_0>,
> > +                               <&img_jpeg_dec_lpcg
> > IMX_LPCG_CLK_4>;
> > +             assigned-clock-rates = <200000000>, <200000000>;
> > +             power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
> > +                             <&pd IMX_SC_R_MJPEG_DEC_S0>,
> > +                             <&pd IMX_SC_R_MJPEG_DEC_S1>,
> > +                             <&pd IMX_SC_R_MJPEG_DEC_S2>,
> > +                             <&pd IMX_SC_R_MJPEG_DEC_S3>;
> > +     };
> > +
> > +     jpegenc: jpegenc@58450000 {
> > +             reg = <0x58450000 0x00050000>;
> > +             interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> > +             clocks = <&img_jpeg_enc_lpcg IMX_LPC[GIT PULL FOR
> > v5.16]G_CLK_0>,
> > +                      <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
> > +             clock-names = "per", "ipg";
> > +             assigned-clocks = <&img_jpeg_enc_lpcg
> > IMX_LPCG_CLK_0>,
> > +                               <&img_jpeg_enc_lpcg
> > IMX_LPCG_CLK_4>;
> > +             assigned-clock-rates = <200000000>, <200000000>;
> > +             power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
> > +                             <&pd IMX_SC_R_MJPEG_ENC_S0>,
> > +                             <&pd IMX_SC_R_MJPEG_ENC_S1>,
> > +                             <&pd IMX_SC_R_MJPEG_ENC_S2>,
> > +                             <&pd IMX_SC_R_MJPEG_ENC_S3>;
> > +     };
> > +
> > +     img_jpeg_dec_lpcg: clock-controller@585d0000 {
> > +             compatible = "fsl,imx8qxp-lpcg";
> > +             reg = <0x585d0000 0x10000>;
> > +             #clock-cells = <1>;
> > +             clocks = <&img_ipg_clk>, <&img_ipg_clk>;
> > +             clock-indices = <IMX_LPCG_CLK_0>,
> > +                             <IMX_LPCG_CLK_4>;
> > +             clock-output-names = "img_jpeg_dec_lpcg_clk",
> > +                                  "img_jpeg_dec_lpcg_ipg_clk";
> > +             power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
> > +     };
> > +
> > +     img_jpeg_enc_lpcg: clock-controller@585f0000 {
> > +             compatible = "fsl,imx8qxp-lpcg";
> > +             reg = <0x585f0000 0x10000>;
> > +             #clock-cells = <1>;
> > +             clocks = <&img_ipg_clk>, <&img_ipg_clk>;
> > +             clock-indices = <IMX_LPCG_CLK_0>,
> > +                             <IMX_LPCG_CLK_4>;
> > +             clock-output-names = "img_jpeg_enc_lpcg_clk",
> > +                                  "img_jpeg_enc_lpcg_ipg_clk";
> > +             power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
> > +     };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> > new file mode 100644
> > index 000000000000..7764b4146e0a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> > @@ -0,0 +1,12 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2021 NXP
> > + */
> > +
> > +&jpegdec {
> > +     compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
> > +};
> > +
> > +&jpegenc {
> > +     compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> > index 12cd059b339b..aebbe2b84aa1 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> > @@ -166,11 +166,13 @@
> >       };
> > 
> >       /* sorted in register address */
> > +     #include "imx8-ss-img.dtsi"
> >       #include "imx8-ss-dma.dtsi"
> >       #include "imx8-ss-conn.dtsi"
> >       #include "imx8-ss-lsio.dtsi"
> >  };
> > 
> > +#include "imx8qm-ss-img.dtsi"
> >  #include "imx8qm-ss-dma.dtsi"
> >  #include "imx8qm-ss-conn.dtsi"
> >  #include "imx8qm-ss-lsio.dtsi"
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> > new file mode 100644
> > index 000000000000..3a087317591d
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> > @@ -0,0 +1,13 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2021 NXP
> > + *   Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +&jpegdec {
> > +     compatible = "nxp,imx8qxp-jpgdec";
> > +};
> > +
> > +&jpegenc {
> > +     compatible = "nxp,imx8qxp-jpgenc";
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 1e6b4995091e..a625fb6bdc62 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -258,12 +258,14 @@
> >       };
> > 
> >       /* sorted in register address */
> > +     #include "imx8-ss-img.dtsi"
> >       #include "imx8-ss-adma.dtsi"
> >       #include "imx8-ss-conn.dtsi"
> >       #include "imx8-ss-ddr.dtsi"
> >       #include "imx8-ss-lsio.dtsi"
> >  };
> > 
> > +#include "imx8qxp-ss-img.dtsi"
> >  #include "imx8qxp-ss-adma.dtsi"
> >  #include "imx8qxp-ss-conn.dtsi"
> >  #include "imx8qxp-ss-lsio.dtsi"
> > 

Re: [EXT] Re: [PATCH v14 2/2] arm64: dts: imx8: Add jpeg encoder/decoder nodes

[Hans Verkuil]

On 14/09/2021 12:42, Mirela Rabulea wrote:
> Hi Hans,
> 
> On Tue, 2021-09-14 at 09:11 +0200, Hans Verkuil wrote:
>> Caution: EXT Email
>>
>> Hi Mirela,
>>
>> On 19/06/2021 16:36, Mirela Rabulea (OSS) wrote:
>>> From: Mirela Rabulea <mirela.rabulea@nxp.com>
>>>
>>> Add dts for imaging subsytem, include jpeg nodes here.
>>> Tested on imx8qxp/qm.
>>
>> I've posted a pull request for the first bindings patch for v5.16, so
>> this dts patch can be merged
>> through whatever tree takes such dts patches.
> 
> Thanks for the notice. I see the patch is already in linux-next. Any
>  more action required from my behalf?

No, that's it.

Regards,

	Hans

> 
> Regards,
> Mirela
> 
>>
>> Regards,
>>
>>         Hans
>>
>>> Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
>>> ---
>>> Changes in v14:
>>>   Address feedback from Aisheng Dong and Ezequiel Garcia:
>>>     - use imx8 instead of imx in patch subject
>>>     - keep jpeg and LPCGs used by jpeg enabled by default in
>>> platform dts (no change here)
>>>
>>>  .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 80
>>> +++++++++++++++++++
>>>  .../boot/dts/freescale/imx8qm-ss-img.dtsi     | 12 +++
>>>  arch/arm64/boot/dts/freescale/imx8qm.dtsi     |  2 +
>>>  .../boot/dts/freescale/imx8qxp-ss-img.dtsi    | 13 +++
>>>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  2 +
>>>  5 files changed, 109 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-
>>> img.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-
>>> img.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
>>> b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
>>> new file mode 100644
>>> index 000000000000..a90654155a88
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
>>> @@ -0,0 +1,80 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright 2019-2021 NXP
>>> + * Zhou Guoniu <guoniu.zhou@nxp.com>
>>> + */
>>> +img_subsys: bus@58000000 {
>>> +     compatible = "simple-bus";
>>> +     #address-cells = <1>;
>>> +     #size-cells = <1>;
>>> +     ranges = <0x58000000 0x0 0x58000000 0x1000000>;
>>> +
>>> +     img_ipg_clk: clock-img-ipg {
>>> +             compatible = "fixed-clock";
>>> +             #clock-cells = <0>;
>>> +             clock-frequency = <200000000>;
>>> +             clock-output-names = "img_ipg_clk";
>>> +     };
>>> +
>>> +     jpegdec: jpegdec@58400000 {
>>> +             reg = <0x58400000 0x00050000>;
>>> +             interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
>>> +             clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
>>> +                      <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
>>> +             clock-names = "per", "ipg";
>>> +             assigned-clocks = <&img_jpeg_dec_lpcg
>>> IMX_LPCG_CLK_0>,
>>> +                               <&img_jpeg_dec_lpcg
>>> IMX_LPCG_CLK_4>;
>>> +             assigned-clock-rates = <200000000>, <200000000>;
>>> +             power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
>>> +                             <&pd IMX_SC_R_MJPEG_DEC_S0>,
>>> +                             <&pd IMX_SC_R_MJPEG_DEC_S1>,
>>> +                             <&pd IMX_SC_R_MJPEG_DEC_S2>,
>>> +                             <&pd IMX_SC_R_MJPEG_DEC_S3>;
>>> +     };
>>> +
>>> +     jpegenc: jpegenc@58450000 {
>>> +             reg = <0x58450000 0x00050000>;
>>> +             interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
>>> +             clocks = <&img_jpeg_enc_lpcg IMX_LPC[GIT PULL FOR
>>> v5.16]G_CLK_0>,
>>> +                      <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
>>> +             clock-names = "per", "ipg";
>>> +             assigned-clocks = <&img_jpeg_enc_lpcg
>>> IMX_LPCG_CLK_0>,
>>> +                               <&img_jpeg_enc_lpcg
>>> IMX_LPCG_CLK_4>;
>>> +             assigned-clock-rates = <200000000>, <200000000>;
>>> +             power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
>>> +                             <&pd IMX_SC_R_MJPEG_ENC_S0>,
>>> +                             <&pd IMX_SC_R_MJPEG_ENC_S1>,
>>> +                             <&pd IMX_SC_R_MJPEG_ENC_S2>,
>>> +                             <&pd IMX_SC_R_MJPEG_ENC_S3>;
>>> +     };
>>> +
>>> +     img_jpeg_dec_lpcg: clock-controller@585d0000 {
>>> +             compatible = "fsl,imx8qxp-lpcg";
>>> +             reg = <0x585d0000 0x10000>;
>>> +             #clock-cells = <1>;
>>> +             clocks = <&img_ipg_clk>, <&img_ipg_clk>;
>>> +             clock-indices = <IMX_LPCG_CLK_0>,
>>> +                             <IMX_LPCG_CLK_4>;
>>> +             clock-output-names = "img_jpeg_dec_lpcg_clk",
>>> +                                  "img_jpeg_dec_lpcg_ipg_clk";
>>> +             power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
>>> +     };
>>> +
>>> +     img_jpeg_enc_lpcg: clock-controller@585f0000 {
>>> +             compatible = "fsl,imx8qxp-lpcg";
>>> +             reg = <0x585f0000 0x10000>;
>>> +             #clock-cells = <1>;
>>> +             clocks = <&img_ipg_clk>, <&img_ipg_clk>;
>>> +             clock-indices = <IMX_LPCG_CLK_0>,
>>> +                             <IMX_LPCG_CLK_4>;
>>> +             clock-output-names = "img_jpeg_enc_lpcg_clk",
>>> +                                  "img_jpeg_enc_lpcg_ipg_clk";
>>> +             power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
>>> +     };
>>> +};
>>> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
>>> b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
>>> new file mode 100644
>>> index 000000000000..7764b4146e0a
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
>>> @@ -0,0 +1,12 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright 2021 NXP
>>> + */
>>> +
>>> +&jpegdec {
>>> +     compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
>>> +};
>>> +
>>> +&jpegenc {
>>> +     compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
>>> +};
>>> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
>>> b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
>>> index 12cd059b339b..aebbe2b84aa1 100644
>>> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
>>> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
>>> @@ -166,11 +166,13 @@
>>>       };
>>>
>>>       /* sorted in register address */
>>> +     #include "imx8-ss-img.dtsi"
>>>       #include "imx8-ss-dma.dtsi"
>>>       #include "imx8-ss-conn.dtsi"
>>>       #include "imx8-ss-lsio.dtsi"
>>>  };
>>>
>>> +#include "imx8qm-ss-img.dtsi"
>>>  #include "imx8qm-ss-dma.dtsi"
>>>  #include "imx8qm-ss-conn.dtsi"
>>>  #include "imx8qm-ss-lsio.dtsi"
>>> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
>>> b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
>>> new file mode 100644
>>> index 000000000000..3a087317591d
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
>>> @@ -0,0 +1,13 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright 2021 NXP
>>> + *   Dong Aisheng <aisheng.dong@nxp.com>
>>> + */
>>> +
>>> +&jpegdec {
>>> +     compatible = "nxp,imx8qxp-jpgdec";
>>> +};
>>> +
>>> +&jpegenc {
>>> +     compatible = "nxp,imx8qxp-jpgenc";
>>> +};
>>> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
>>> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
>>> index 1e6b4995091e..a625fb6bdc62 100644
>>> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
>>> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
>>> @@ -258,12 +258,14 @@
>>>       };
>>>
>>>       /* sorted in register address */
>>> +     #include "imx8-ss-img.dtsi"
>>>       #include "imx8-ss-adma.dtsi"
>>>       #include "imx8-ss-conn.dtsi"
>>>       #include "imx8-ss-ddr.dtsi"
>>>       #include "imx8-ss-lsio.dtsi"
>>>  };
>>>
>>> +#include "imx8qxp-ss-img.dtsi"
>>>  #include "imx8qxp-ss-adma.dtsi"
>>>  #include "imx8qxp-ss-conn.dtsi"
>>>  #include "imx8qxp-ss-lsio.dtsi"
>>>