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From: Chun-Jie Chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Chun-Jie Chen <chun-jie.chen@mediatek.com>
Subject: [v14 01/21] dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock
Date: Mon, 26 Jul 2021 18:56:59 +0800	[thread overview]
Message-ID: <20210726105719.15793-2-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210726105719.15793-1-chun-jie.chen@mediatek.com>

This patch adds the new binding documentation for system clock
and functional clock on Mediatek MT8192.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../arm/mediatek/mediatek,mt8192-clock.yaml   | 199 ++++++++++++++++++
 .../mediatek/mediatek,mt8192-sys-clock.yaml   |  65 ++++++
 2 files changed, 264 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
new file mode 100644
index 000000000000..c8c67c033f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Functional Clock Controller for MT8192
+
+maintainers:
+  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description:
+  The Mediatek functional clock controller provides various clocks on MT8192.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-scp_adsp
+          - mediatek,mt8192-imp_iic_wrap_c
+          - mediatek,mt8192-imp_iic_wrap_e
+          - mediatek,mt8192-imp_iic_wrap_s
+          - mediatek,mt8192-imp_iic_wrap_ws
+          - mediatek,mt8192-imp_iic_wrap_w
+          - mediatek,mt8192-imp_iic_wrap_n
+          - mediatek,mt8192-msdc_top
+          - mediatek,mt8192-msdc
+          - mediatek,mt8192-mfgcfg
+          - mediatek,mt8192-imgsys
+          - mediatek,mt8192-imgsys2
+          - mediatek,mt8192-vdecsys_soc
+          - mediatek,mt8192-vdecsys
+          - mediatek,mt8192-vencsys
+          - mediatek,mt8192-camsys
+          - mediatek,mt8192-camsys_rawa
+          - mediatek,mt8192-camsys_rawb
+          - mediatek,mt8192-camsys_rawc
+          - mediatek,mt8192-ipesys
+          - mediatek,mt8192-mdpsys
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    scp_adsp: clock-controller@10720000 {
+        compatible = "mediatek,mt8192-scp_adsp";
+        reg = <0x10720000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_c: clock-controller@11007000 {
+        compatible = "mediatek,mt8192-imp_iic_wrap_c";
+        reg = <0x11007000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_e: clock-controller@11cb1000 {
+        compatible = "mediatek,mt8192-imp_iic_wrap_e";
+        reg = <0x11cb1000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_s: clock-controller@11d03000 {
+        compatible = "mediatek,mt8192-imp_iic_wrap_s";
+        reg = <0x11d03000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_ws: clock-controller@11d23000 {
+        compatible = "mediatek,mt8192-imp_iic_wrap_ws";
+        reg = <0x11d23000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_w: clock-controller@11e01000 {
+        compatible = "mediatek,mt8192-imp_iic_wrap_w";
+        reg = <0x11e01000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_n: clock-controller@11f02000 {
+        compatible = "mediatek,mt8192-imp_iic_wrap_n";
+        reg = <0x11f02000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    msdc_top: clock-controller@11f10000 {
+        compatible = "mediatek,mt8192-msdc_top";
+        reg = <0x11f10000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    msdc: clock-controller@11f60000 {
+        compatible = "mediatek,mt8192-msdc";
+        reg = <0x11f60000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    mfgcfg: clock-controller@13fbf000 {
+        compatible = "mediatek,mt8192-mfgcfg";
+        reg = <0x13fbf000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imgsys: clock-controller@15020000 {
+        compatible = "mediatek,mt8192-imgsys";
+        reg = <0x15020000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imgsys2: clock-controller@15820000 {
+        compatible = "mediatek,mt8192-imgsys2";
+        reg = <0x15820000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vdecsys_soc: clock-controller@1600f000 {
+        compatible = "mediatek,mt8192-vdecsys_soc";
+        reg = <0x1600f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vdecsys: clock-controller@1602f000 {
+        compatible = "mediatek,mt8192-vdecsys";
+        reg = <0x1602f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vencsys: clock-controller@17000000 {
+        compatible = "mediatek,mt8192-vencsys";
+        reg = <0x17000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys: clock-controller@1a000000 {
+        compatible = "mediatek,mt8192-camsys";
+        reg = <0x1a000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_rawa: clock-controller@1a04f000 {
+        compatible = "mediatek,mt8192-camsys_rawa";
+        reg = <0x1a04f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_rawb: clock-controller@1a06f000 {
+        compatible = "mediatek,mt8192-camsys_rawb";
+        reg = <0x1a06f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_rawc: clock-controller@1a08f000 {
+        compatible = "mediatek,mt8192-camsys_rawc";
+        reg = <0x1a08f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    ipesys: clock-controller@1b000000 {
+        compatible = "mediatek,mt8192-ipesys";
+        reg = <0x1b000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    mdpsys: clock-controller@1f000000 {
+        compatible = "mediatek,mt8192-mdpsys";
+        reg = <0x1f000000 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
new file mode 100644
index 000000000000..5705bcf1fe47
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek System Clock Controller for MT8192
+
+maintainers:
+  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description:
+  The Mediatek system clock controller provides various clocks and system configuration
+  like reset and bus protection on MT8192.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-topckgen
+          - mediatek,mt8192-infracfg
+          - mediatek,mt8192-pericfg
+          - mediatek,mt8192-apmixedsys
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    topckgen: syscon@10000000 {
+        compatible = "mediatek,mt8192-topckgen", "syscon";
+        reg = <0x10000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    infracfg: syscon@10001000 {
+        compatible = "mediatek,mt8192-infracfg", "syscon";
+        reg = <0x10001000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    pericfg: syscon@10003000 {
+        compatible = "mediatek,mt8192-pericfg", "syscon";
+        reg = <0x10003000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    apmixedsys: syscon@1000c000 {
+        compatible = "mediatek,mt8192-apmixedsys", "syscon";
+        reg = <0x1000c000 0x1000>;
+        #clock-cells = <1>;
+    };
-- 
2.18.0


  reply	other threads:[~2021-07-26 10:57 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-26 10:56 [v14 00/21] Mediatek MT8192 clock support Chun-Jie Chen
2021-07-26 10:56 ` Chun-Jie Chen [this message]
2021-07-27 17:53   ` [v14 01/21] dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock Stephen Boyd
2021-07-26 10:57 ` [v14 02/21] dt-bindings: ARM: Mediatek: Add mmsys document binding for MT8192 Chun-Jie Chen
2021-07-27 17:53   ` Stephen Boyd
2021-07-28  8:47     ` Enric Balletbo Serra
2021-07-28 10:21       ` Chun-Jie Chen
2021-08-03 20:17       ` Stephen Boyd
2021-08-05 15:35     ` Matthias Brugger
2021-08-05 23:49       ` Stephen Boyd
2021-07-26 10:57 ` [v14 03/21] dt-bindings: ARM: Mediatek: Add audsys " Chun-Jie Chen
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` [v14 04/21] clk: mediatek: Add dt-bindings of MT8192 clocks Chun-Jie Chen
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` [v14 05/21] clk: mediatek: Get regmap without syscon compatible check Chun-Jie Chen
2021-07-27  4:37   ` Ikjoon Jang
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` [v14 06/21] clk: mediatek: Fix asymmetrical PLL enable and disable control Chun-Jie Chen
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data Chun-Jie Chen
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 08/21] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Chun-Jie Chen
2021-07-27  4:38   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 09/21] clk: mediatek: Add MT8192 basic clocks support Chun-Jie Chen
2021-07-27  4:39   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 10/21] clk: mediatek: Add MT8192 audio clock support Chun-Jie Chen
2021-07-27  4:40   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 11/21] clk: mediatek: Add MT8192 camsys " Chun-Jie Chen
2021-07-27  4:41   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 12/21] clk: mediatek: Add MT8192 imgsys " Chun-Jie Chen
2021-07-27  4:41   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 13/21] clk: mediatek: Add MT8192 imp i2c wrapper " Chun-Jie Chen
2021-07-27  4:42   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 14/21] clk: mediatek: Add MT8192 ipesys " Chun-Jie Chen
2021-07-27  4:43   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 15/21] clk: mediatek: Add MT8192 mdpsys " Chun-Jie Chen
2021-07-27  4:43   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 16/21] clk: mediatek: Add MT8192 mfgcfg " Chun-Jie Chen
2021-07-27  4:44   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 17/21] clk: mediatek: Add MT8192 mmsys " Chun-Jie Chen
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 18/21] clk: mediatek: Add MT8192 msdc " Chun-Jie Chen
2021-07-27  4:45   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 19/21] clk: mediatek: Add MT8192 scp adsp " Chun-Jie Chen
2021-07-27  4:46   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 20/21] clk: mediatek: Add MT8192 vdecsys " Chun-Jie Chen
2021-07-27  4:47   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 21/21] clk: mediatek: Add MT8192 vencsys " Chun-Jie Chen
2021-07-27  4:47   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd

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