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From: Chun-Jie Chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>,
	Chun-Jie Chen <chun-jie.chen@mediatek.com>
Subject: [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data
Date: Mon, 26 Jul 2021 18:57:05 +0800	[thread overview]
Message-ID: <20210726105719.15793-8-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210726105719.15793-1-chun-jie.chen@mediatek.com>

In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.

Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.h | 20 +++++++++++---------
 drivers/clk/mediatek/clk-pll.c | 15 ++++++++++-----
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c3d6756b0c7e..31c7cb304508 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -213,13 +213,13 @@ struct mtk_pll_div_table {
 struct mtk_pll_data {
 	int id;
 	const char *name;
-	uint32_t reg;
-	uint32_t pwr_reg;
-	uint32_t en_mask;
-	uint32_t pd_reg;
-	uint32_t tuner_reg;
-	uint32_t tuner_en_reg;
-	uint8_t tuner_en_bit;
+	u32 reg;
+	u32 pwr_reg;
+	u32 en_mask;
+	u32 pd_reg;
+	u32 tuner_reg;
+	u32 tuner_en_reg;
+	u8 tuner_en_bit;
 	int pd_shift;
 	unsigned int flags;
 	const struct clk_ops *ops;
@@ -228,11 +228,13 @@ struct mtk_pll_data {
 	unsigned long fmax;
 	int pcwbits;
 	int pcwibits;
-	uint32_t pcw_reg;
+	u32 pcw_reg;
 	int pcw_shift;
-	uint32_t pcw_chg_reg;
+	u32 pcw_chg_reg;
 	const struct mtk_pll_div_table *div_table;
 	const char *parent_name;
+	u32 en_reg;
+	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
 };
 
 void mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 11ed5d1d1c36..7fb001a4e7d8 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -44,6 +44,7 @@ struct mtk_clk_pll {
 	void __iomem	*tuner_en_addr;
 	void __iomem	*pcw_addr;
 	void __iomem	*pcw_chg_addr;
+	void __iomem	*en_addr;
 	const struct mtk_pll_data *data;
 };
 
@@ -56,7 +57,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
 {
 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 
-	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
+	return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
 }
 
 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
@@ -248,8 +249,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
 	writel(r, pll->pwr_addr);
 	udelay(1);
 
-	r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
-	writel(r, pll->base_addr + REG_CON0);
+	r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
+	writel(r, pll->en_addr);
 
 	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
 	if (div_en_mask) {
@@ -290,8 +291,8 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
 		writel(r, pll->base_addr + REG_CON0);
 	}
 
-	r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN;
-	writel(r, pll->base_addr + REG_CON0);
+	r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
+	writel(r, pll->en_addr);
 
 	r = readl(pll->pwr_addr) | CON0_ISO_EN;
 	writel(r, pll->pwr_addr);
@@ -333,6 +334,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
 		pll->tuner_addr = base + data->tuner_reg;
 	if (data->tuner_en_reg)
 		pll->tuner_en_addr = base + data->tuner_en_reg;
+	if (data->en_reg)
+		pll->en_addr = base + data->en_reg;
+	else
+		pll->en_addr = pll->base_addr + REG_CON0;
 	pll->hw.init = &init;
 	pll->data = data;
 
-- 
2.18.0


  parent reply	other threads:[~2021-07-26 10:58 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-26 10:56 [v14 00/21] Mediatek MT8192 clock support Chun-Jie Chen
2021-07-26 10:56 ` [v14 01/21] dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock Chun-Jie Chen
2021-07-27 17:53   ` Stephen Boyd
2021-07-26 10:57 ` [v14 02/21] dt-bindings: ARM: Mediatek: Add mmsys document binding for MT8192 Chun-Jie Chen
2021-07-27 17:53   ` Stephen Boyd
2021-07-28  8:47     ` Enric Balletbo Serra
2021-07-28 10:21       ` Chun-Jie Chen
2021-08-03 20:17       ` Stephen Boyd
2021-08-05 15:35     ` Matthias Brugger
2021-08-05 23:49       ` Stephen Boyd
2021-07-26 10:57 ` [v14 03/21] dt-bindings: ARM: Mediatek: Add audsys " Chun-Jie Chen
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` [v14 04/21] clk: mediatek: Add dt-bindings of MT8192 clocks Chun-Jie Chen
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` [v14 05/21] clk: mediatek: Get regmap without syscon compatible check Chun-Jie Chen
2021-07-27  4:37   ` Ikjoon Jang
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` [v14 06/21] clk: mediatek: Fix asymmetrical PLL enable and disable control Chun-Jie Chen
2021-07-27 17:54   ` Stephen Boyd
2021-07-26 10:57 ` Chun-Jie Chen [this message]
2021-07-27 17:55   ` [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data Stephen Boyd
2021-07-26 10:57 ` [v14 08/21] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Chun-Jie Chen
2021-07-27  4:38   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 09/21] clk: mediatek: Add MT8192 basic clocks support Chun-Jie Chen
2021-07-27  4:39   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 10/21] clk: mediatek: Add MT8192 audio clock support Chun-Jie Chen
2021-07-27  4:40   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 11/21] clk: mediatek: Add MT8192 camsys " Chun-Jie Chen
2021-07-27  4:41   ` Ikjoon Jang
2021-07-27 17:55   ` Stephen Boyd
2021-07-26 10:57 ` [v14 12/21] clk: mediatek: Add MT8192 imgsys " Chun-Jie Chen
2021-07-27  4:41   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 13/21] clk: mediatek: Add MT8192 imp i2c wrapper " Chun-Jie Chen
2021-07-27  4:42   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 14/21] clk: mediatek: Add MT8192 ipesys " Chun-Jie Chen
2021-07-27  4:43   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 15/21] clk: mediatek: Add MT8192 mdpsys " Chun-Jie Chen
2021-07-27  4:43   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 16/21] clk: mediatek: Add MT8192 mfgcfg " Chun-Jie Chen
2021-07-27  4:44   ` Ikjoon Jang
2021-07-27 17:56   ` Stephen Boyd
2021-07-26 10:57 ` [v14 17/21] clk: mediatek: Add MT8192 mmsys " Chun-Jie Chen
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 18/21] clk: mediatek: Add MT8192 msdc " Chun-Jie Chen
2021-07-27  4:45   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 19/21] clk: mediatek: Add MT8192 scp adsp " Chun-Jie Chen
2021-07-27  4:46   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 20/21] clk: mediatek: Add MT8192 vdecsys " Chun-Jie Chen
2021-07-27  4:47   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd
2021-07-26 10:57 ` [v14 21/21] clk: mediatek: Add MT8192 vencsys " Chun-Jie Chen
2021-07-27  4:47   ` Ikjoon Jang
2021-07-27 17:57   ` Stephen Boyd

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