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From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <p.zabel@pengutronix.de>,
	<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <lokeshvutla@ti.com>
Subject: [PATCH v3 8/9] phy: cadence-torrent: Add debug information for PHY configuration
Date: Wed, 28 Jul 2021 16:54:53 +0200	[thread overview]
Message-ID: <20210728145454.15945-9-sjakhade@cadence.com> (raw)
In-Reply-To: <20210728145454.15945-1-sjakhade@cadence.com>

Add debug information in probe regarding PHY configuration parameters
like single link or multilink protocol along with number of lanes
used for each protocol link.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 drivers/phy/cadence/phy-cadence-torrent.c | 36 ++++++++++++++++++++---
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index e4dd8d1711a6..4024db052cf9 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -573,6 +573,24 @@ static const struct coefficients vltg_coeff[4][4] = {
 	}
 };
 
+static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
+{
+	switch (phy_type) {
+	case TYPE_DP:
+		return "DisplayPort";
+	case TYPE_PCIE:
+		return "PCIe";
+	case TYPE_SGMII:
+		return "SGMII";
+	case TYPE_QSGMII:
+		return "QSGMII";
+	case TYPE_USB:
+		return "USB";
+	default:
+		return "None";
+	}
+}
+
 /*
  * Set registers responsible for enabling and configuring SSC, with second and
  * third register values provided by parameters.
@@ -2392,10 +2410,9 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
 				init_dp_regmap++;
 			}
 
-			dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
-				 cdns_phy->phys[node].num_lanes,
-				 cdns_phy->max_bit_rate / 1000,
-				 cdns_phy->max_bit_rate % 1000);
+			dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
+				cdns_phy->max_bit_rate / 1000,
+				cdns_phy->max_bit_rate % 1000);
 
 			gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
 			gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
@@ -2427,6 +2444,17 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
 		goto put_lnk_rst;
 	}
 
+	if (cdns_phy->nsubnodes > 1)
+		dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
+			cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
+			cdns_phy->phys[0].num_lanes,
+			cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
+			cdns_phy->phys[1].num_lanes);
+	else
+		dev_dbg(dev, "Single link: %s (%d lanes)",
+			cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
+			cdns_phy->phys[0].num_lanes);
+
 	return 0;
 
 put_child:
-- 
2.26.1


  parent reply	other threads:[~2021-07-28 14:56 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 14:54 [PATCH v3 0/9] PHY: Prepare Cadence Torrent PHY driver to support multilink DP Swapnil Jakhade
2021-07-28 14:54 ` [PATCH v3 1/9] phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK message Swapnil Jakhade
2021-07-28 14:54 ` [PATCH v3 2/9] phy: cadence-torrent: Reorder few functions to remove function declarations Swapnil Jakhade
2021-07-28 14:54 ` [PATCH v3 3/9] phy: cadence-torrent: Add enum for supported input reference clock frequencies Swapnil Jakhade
2021-07-28 14:54 ` [PATCH v3 4/9] phy: cadence-torrent: Configure PHY registers as a function of input reference clock rate Swapnil Jakhade
2021-07-28 14:54 ` [PATCH v3 5/9] phy: cadence-torrent: Add PHY registers for DP in array format Swapnil Jakhade
2021-07-28 14:54 ` [PATCH v3 6/9] phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock Swapnil Jakhade
2021-07-28 14:54 ` [PATCH v3 7/9] phy: cadence-torrent: Add separate functions for reusable code Swapnil Jakhade
2021-07-28 14:54 ` Swapnil Jakhade [this message]
2021-07-28 14:54 ` [PATCH v3 9/9] phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-08-17 10:12 ` [PATCH v3 0/9] PHY: Prepare Cadence Torrent PHY driver to support multilink DP Vinod Koul

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