[PATCH 0/4] arm64: dts: qcom: IPA-related DTS updates

[PATCH 0/4] arm64: dts: qcom: IPA-related DTS updates

[Alex Elder]

This series includes four updates to DTS files for Qualcomm SoCs
that include IPA.

Most of this series was posted once before, and accepted into the
net-next/master branch by David Miller:
  https://lore.kernel.org/netdev/20210719212456.3176086-1-elder@linaro.org/

That series got reverted yesterday, meaning these patches can be
taken in through the Qualcomm tree as intended:
  https://lore.kernel.org/netdev/20210802233019.800250-1-elder@linaro.org/

The first patch defines IPA information for the SC7280 SoC.  The
second enables IPA for the SC7280 IDP platform, indicating the
modem should perform early IPA initialization.

The third patch adds the definition of a reserved memory area to
hold IPA firmware for the SC7180 SoC; this is used if the modem does
*not* do early IPA initialization.

And the last patch fixes the definitions used for interconnects for
the SM8350 SoC.  A corresponding update to the configuration data
(IPA code) was posted earlier today:
  https://lore.kernel.org/netdev/20210804135407.1358606-1-elder@linaro.org

  					-Alex

Alex Elder (4):
  arm64: dts: qcom: sc7280: add IPA information
  arm64: dts: qcom: sc7280: enable IPA for sc7280-idp
  arm64: dts: qcom: sc7180: define ipa_fw_mem node
  arm64: dts: qcom: sm8350: fix IPA interconnects

 arch/arm64/boot/dts/qcom/sc7180.dtsi    |  5 +++
 arch/arm64/boot/dts/qcom/sc7280-idp.dts |  5 +++
 arch/arm64/boot/dts/qcom/sc7280.dtsi    | 42 +++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8350.dtsi    |  8 ++---
 4 files changed, 55 insertions(+), 5 deletions(-)

-- 
2.27.0

[PATCH 1/4] arm64: dts: qcom: sc7280: add IPA information

[Alex Elder]

Add IPA-related nodes and definitions to "sc7280.dtsi", including
the reserved memory area used for AP-based IPA firmware loading.

Signed-off-by: Alex Elder <elder@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 42 ++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 029723a75edef..5764c5b5cae17 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -69,6 +69,11 @@ cpucp_mem: memory@80b00000 {
 			no-map;
 			reg = <0x0 0x80b00000 0x0 0x100000>;
 		};
+
+		ipa_fw_mem: memory@8b700000 {
+			reg = <0 0x8b700000 0 0x10000>;
+			no-map;
+		};
 	};
 
 	cpus {
@@ -568,6 +573,43 @@ mmss_noc: interconnect@1740000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		ipa: ipa@1e40000 {
+			compatible = "qcom,sc7280-ipa";
+
+			iommus = <&apps_smmu 0x480 0x0>,
+				 <&apps_smmu 0x482 0x0>;
+			reg = <0 0x1e40000 0 0x8000>,
+			      <0 0x1e50000 0 0x4ad0>,
+			      <0 0x1e04000 0 0x23000>;
+			reg-names = "ipa-reg",
+				    "ipa-shared",
+				    "gsi";
+
+			interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
+					      <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
+					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "ipa",
+					  "gsi",
+					  "ipa-clock-query",
+					  "ipa-setup-ready";
+
+			clocks = <&rpmhcc RPMH_IPA_CLK>;
+			clock-names = "core";
+
+			interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
+					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
+			interconnect-names = "memory",
+					     "config";
+
+			qcom,smem-states = <&ipa_smp2p_out 0>,
+					   <&ipa_smp2p_out 1>;
+			qcom,smem-state-names = "ipa-clock-enabled-valid",
+						"ipa-clock-enabled";
+
+			status = "disabled";
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex", "syscon";
 			reg = <0 0x01f40000 0 0x40000>;
-- 
2.27.0

Re: [PATCH 1/4] arm64: dts: qcom: sc7280: add IPA information

[Matthias Kaehlcke]

On Wed, Aug 04, 2021 at 04:02:11PM -0500, Alex Elder wrote:
> Add IPA-related nodes and definitions to "sc7280.dtsi", including
> the reserved memory area used for AP-based IPA firmware loading.
> 
> Signed-off-by: Alex Elder <elder@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 42 ++++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 029723a75edef..5764c5b5cae17 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -69,6 +69,11 @@ cpucp_mem: memory@80b00000 {
>  			no-map;
>  			reg = <0x0 0x80b00000 0x0 0x100000>;
>  		};
> +
> +		ipa_fw_mem: memory@8b700000 {
> +			reg = <0 0x8b700000 0 0x10000>;
> +			no-map;
> +		};
>  	};
>  
>  	cpus {
> @@ -568,6 +573,43 @@ mmss_noc: interconnect@1740000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +		ipa: ipa@1e40000 {
> +			compatible = "qcom,sc7280-ipa";
> +
> +			iommus = <&apps_smmu 0x480 0x0>,
> +				 <&apps_smmu 0x482 0x0>;
> +			reg = <0 0x1e40000 0 0x8000>,
> +			      <0 0x1e50000 0 0x4ad0>,
> +			      <0 0x1e04000 0 0x23000>;
> +			reg-names = "ipa-reg",
> +				    "ipa-shared",
> +				    "gsi";
> +
> +			interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
> +					      <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,

nit: use GIC_SPI for the interrupt type

> +					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "ipa",
> +					  "gsi",
> +					  "ipa-clock-query",
> +					  "ipa-setup-ready";
> +
> +			clocks = <&rpmhcc RPMH_IPA_CLK>;
> +			clock-names = "core";
> +
> +			interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
> +					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
> +			interconnect-names = "memory",
> +					     "config";
> +
> +			qcom,smem-states = <&ipa_smp2p_out 0>,
> +					   <&ipa_smp2p_out 1>;
> +			qcom,smem-state-names = "ipa-clock-enabled-valid",
> +						"ipa-clock-enabled";
> +
> +			status = "disabled";
> +		};
> +

I know little about IPA, but besides the nit this looks sane to me.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>

[PATCH 2/4] arm64: dts: qcom: sc7280: enable IPA for sc7280-idp

[Alex Elder]

Enable IPA for the SC7280 IDP, with the modem performing early
initialization.

Signed-off-by: Alex Elder <elder@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 73225e3c2f86f..66640ce959124 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -243,6 +243,11 @@ vreg_l6e_0p8: ldo6 {
 	};
 };
 
+&ipa {
+	status = "okay";
+	modem-init;
+};
+
 &pmk8350_vadc {
 		pm8350_die_temp {
 			reg = <PM8350_ADC7_DIE_TEMP>;
-- 
2.27.0

Re: [PATCH 2/4] arm64: dts: qcom: sc7280: enable IPA for sc7280-idp

[Matthias Kaehlcke]

On Wed, Aug 04, 2021 at 04:02:12PM -0500, Alex Elder wrote:
> Enable IPA for the SC7280 IDP, with the modem performing early
> initialization.
> 
> Signed-off-by: Alex Elder <elder@linaro.org>

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>

[PATCH 3/4] arm64: dts: qcom: sc7180: define ipa_fw_mem node

[Alex Elder]

Define the reserved memory space used for IPA firmware for the
Qualcomm SC7180 SoC.

Signed-off-by: Alex Elder <elder@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 9b65896d62dc1..5b10eb4be2b1d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -110,6 +110,11 @@ tz_mem: memory@80b00000 {
 			no-map;
 		};
 
+		ipa_fw_mem: memory@8b700000 {
+			reg = <0 0x8b700000 0 0x10000>;
+			no-map;
+		};
+
 		rmtfs_mem: memory@94600000 {
 			compatible = "qcom,rmtfs-mem";
 			reg = <0x0 0x94600000 0x0 0x200000>;
-- 
2.27.0

Re: [PATCH 3/4] arm64: dts: qcom: sc7180: define ipa_fw_mem node

[Matthias Kaehlcke]

On Wed, Aug 04, 2021 at 04:02:13PM -0500, Alex Elder wrote:
> Define the reserved memory space used for IPA firmware for the
> Qualcomm SC7180 SoC.
> 
> Signed-off-by: Alex Elder <elder@linaro.org>

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>

[PATCH 4/4] arm64: dts: qcom: sm8350: fix IPA interconnects

[Alex Elder]

There should only be two interconnects defined for IPA on the
QUalcomm SM8350 SoC.  The names should also match those specified by
the IPA Device Tree binding.

Signed-off-by: Alex Elder <elder@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a631d58166b1c..01f60a3bd1c14 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -666,12 +666,10 @@ ipa: ipa@1e40000 {
 			clocks = <&rpmhcc RPMH_IPA_CLK>;
 			clock-names = "core";
 
-			interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
-					<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
+			interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
 					<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
-			interconnect-names = "ipa_to_llcc",
-					     "llcc_to_ebi1",
-					     "appss_to_ipa";
+			interconnect-names = "memory",
+					     "config";
 
 			qcom,smem-states = <&ipa_smp2p_out 0>,
 					   <&ipa_smp2p_out 1>;
-- 
2.27.0

Re: [PATCH 4/4] arm64: dts: qcom: sm8350: fix IPA interconnects

[Georgi Djakov]

On 5.08.21 0:02, Alex Elder wrote:
> There should only be two interconnects defined for IPA on the
> QUalcomm SM8350 SoC.  The names should also match those specified by
> the IPA Device Tree binding.
> 
> Signed-off-by: Alex Elder <elder@linaro.org>

Acked-by: Georgi Djakov <djakov@kernel.org>

> ---
>   arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 +++-----
>   1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index a631d58166b1c..01f60a3bd1c14 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -666,12 +666,10 @@ ipa: ipa@1e40000 {
>   			clocks = <&rpmhcc RPMH_IPA_CLK>;
>   			clock-names = "core";
>   
> -			interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
> -					<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
> +			interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
>   					<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
> -			interconnect-names = "ipa_to_llcc",
> -					     "llcc_to_ebi1",
> -					     "appss_to_ipa";
> +			interconnect-names = "memory",
> +					     "config";
>   
>   			qcom,smem-states = <&ipa_smp2p_out 0>,
>   					   <&ipa_smp2p_out 1>;
>