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From: Huacai Chen <chenhuacai@loongson.cn> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org> Cc: linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>, Huacai Chen <chenhuacai@gmail.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Huacai Chen <chenhuacai@loongson.cn> Subject: [PATCH V2 02/10] irqchip/loongson-pch-pic: Add ACPI init support Date: Mon, 16 Aug 2021 15:52:44 +0800 [thread overview] Message-ID: <20210816075252.4003406-3-chenhuacai@loongson.cn> (raw) In-Reply-To: <20210816075252.4003406-1-chenhuacai@loongson.cn> We are preparing to add new Loongson (based on LoongArch, not MIPS) support. LoongArch use ACPI other than DT as its boot protocol, so add ACPI init support. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> --- drivers/irqchip/irq-loongson-pch-pic.c | 110 +++++++++++++++++++------ 1 file changed, 83 insertions(+), 27 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index a4eb8a2181c7..476a00f11480 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -33,13 +33,18 @@ #define PIC_REG_IDX(irq_id) ((irq_id) / PIC_COUNT_PER_REG) #define PIC_REG_BIT(irq_id) ((irq_id) % PIC_COUNT_PER_REG) +static int nr_pch_pics; + struct pch_pic { void __iomem *base; struct irq_domain *pic_domain; + struct fwnode_handle *domain_handle; u32 ht_vec_base; raw_spinlock_t pic_lock; }; +struct pch_pic *pch_pic_priv[4]; + static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit) { u32 reg; @@ -180,7 +185,7 @@ static void pch_pic_reset(struct pch_pic *priv) int i; for (i = 0; i < PIC_COUNT; i++) { - /* Write vectored ID */ + /* Write vector ID */ writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i)); /* Hardcode route to HT0 Lo */ writeb(1, priv->base + PCH_INT_ROUTE(i)); @@ -198,50 +203,37 @@ static void pch_pic_reset(struct pch_pic *priv) } } -static int pch_pic_of_init(struct device_node *node, - struct device_node *parent) +static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, + struct irq_domain *parent_domain, struct fwnode_handle *domain_handle) { + int vec_count; struct pch_pic *priv; - struct irq_domain *parent_domain; - int err; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; raw_spin_lock_init(&priv->pic_lock); - priv->base = of_iomap(node, 0); - if (!priv->base) { - err = -ENOMEM; + priv->base = ioremap(addr, size); + if (!priv->base) goto free_priv; - } - parent_domain = irq_find_host(parent); - if (!parent_domain) { - pr_err("Failed to find the parent domain\n"); - err = -ENXIO; - goto iounmap_base; - } + priv->domain_handle = domain_handle; - if (of_property_read_u32(node, "loongson,pic-base-vec", - &priv->ht_vec_base)) { - pr_err("Failed to determine pic-base-vec\n"); - err = -EINVAL; - goto iounmap_base; - } + priv->ht_vec_base = vec_base; + vec_count = ((readq(priv->base) >> 48) & 0xff) + 1; priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0, - PIC_COUNT, - of_node_to_fwnode(node), - &pch_pic_domain_ops, - priv); + vec_count, priv->domain_handle, + &pch_pic_domain_ops, priv); + if (!priv->pic_domain) { pr_err("Failed to create IRQ domain\n"); - err = -ENOMEM; goto iounmap_base; } pch_pic_reset(priv); + pch_pic_priv[nr_pch_pics++] = priv; return 0; @@ -250,7 +242,71 @@ static int pch_pic_of_init(struct device_node *node, free_priv: kfree(priv); - return err; + return -EINVAL; +} + +#ifdef CONFIG_OF + +static int pch_pic_of_init(struct device_node *node, + struct device_node *parent) +{ + int err, vec_base; + struct resource res; + struct irq_domain *parent_domain; + + if (of_address_to_resource(node, 0, &res)) + return -EINVAL; + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("Failed to find the parent domain\n"); + return -ENXIO; + } + + if (of_property_read_u32(node, "loongson,pic-base-vec", &vec_base)) { + pr_err("Failed to determine pic-base-vec\n"); + return -EINVAL; + } + + err = pch_pic_init(res.start, resource_size(&res), vec_base, + parent_domain, of_node_to_fwnode(node)); + if (err < 0) + return err; + + return 0; } IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init); + +#endif + +#ifdef CONFIG_ACPI + +struct fwnode_handle *pch_pic_acpi_init(struct fwnode_handle *parent, + struct acpi_madt_bio_pic *acpi_pchpic) +{ + int ret; + struct irq_domain *parent_domain; + struct fwnode_handle *domain_handle; + + parent_domain = irq_find_matching_fwnode(parent, DOMAIN_BUS_ANY); + if (!parent_domain) { + pr_err("Failed to find the parent domain\n"); + return NULL; + } + + domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchpic); + if (!domain_handle) { + pr_err("Unable to allocate domain handle\n"); + return NULL; + } + + ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size, + acpi_pchpic->gsi_base, parent_domain, domain_handle); + if (ret < 0) + return NULL; + + return domain_handle; +} + +#endif -- 2.27.0
next prev parent reply other threads:[~2021-08-16 7:54 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-16 7:52 [PATCH V2 00/10] irqchip: Add LoongArch-related irqchip drivers Huacai Chen 2021-08-16 7:52 ` [PATCH V2 01/10] irqchip: Adjust Kconfig for Loongson Huacai Chen 2021-08-16 7:52 ` Huacai Chen [this message] 2021-08-16 7:52 ` [PATCH V2 03/10] irqchip/loongson-pch-pic: Add suspend/resume support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 04/10] irqchip/loongson-pch-msi: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 05/10] irqchip/loongson-htvec: " Huacai Chen 2021-08-16 7:52 ` [PATCH V2 06/10] irqchip/loongson-htvec: Add suspend/resume support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 07/10] irqchip/loongson-liointc: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 08/10] irqchip: Add LoongArch CPU interrupt controller support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 09/10] irqchip: Add Loongson Extended I/O " Huacai Chen 2021-08-16 7:52 ` [PATCH V2 10/10] irqchip: Add Loongson PCH LPC " Huacai Chen
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