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From: Huacai Chen <chenhuacai@loongson.cn> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org> Cc: linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>, Huacai Chen <chenhuacai@gmail.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Huacai Chen <chenhuacai@loongson.cn> Subject: [PATCH V2 04/10] irqchip/loongson-pch-msi: Add ACPI init support Date: Mon, 16 Aug 2021 15:52:46 +0800 [thread overview] Message-ID: <20210816075252.4003406-5-chenhuacai@loongson.cn> (raw) In-Reply-To: <20210816075252.4003406-1-chenhuacai@loongson.cn> We are preparing to add new Loongson (based on LoongArch, not MIPS) support. LoongArch use ACPI other than DT as its boot protocol, so add ACPI init support. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> --- drivers/irqchip/irq-loongson-pch-msi.c | 126 ++++++++++++++++--------- 1 file changed, 84 insertions(+), 42 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c index 32562b7e681b..1ecb15f8745b 100644 --- a/drivers/irqchip/irq-loongson-pch-msi.c +++ b/drivers/irqchip/irq-loongson-pch-msi.c @@ -21,6 +21,7 @@ struct pch_msi_data { u32 irq_first; /* The vector number that MSIs starts */ u32 num_irqs; /* The number of vectors for MSIs */ unsigned long *msi_map; + struct fwnode_handle *domain_handle; }; static void pch_msi_mask_msi_irq(struct irq_data *d) @@ -154,12 +155,14 @@ static const struct irq_domain_ops pch_msi_middle_domain_ops = { }; static int pch_msi_init_domains(struct pch_msi_data *priv, - struct device_node *node, - struct irq_domain *parent) + struct irq_domain *parent, + struct fwnode_handle *domain_handle) { struct irq_domain *middle_domain, *msi_domain; - middle_domain = irq_domain_create_linear(of_node_to_fwnode(node), + priv->domain_handle = domain_handle; + + middle_domain = irq_domain_create_linear(priv->domain_handle, priv->num_irqs, &pch_msi_middle_domain_ops, priv); @@ -171,7 +174,7 @@ static int pch_msi_init_domains(struct pch_msi_data *priv, middle_domain->parent = parent; irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS); - msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node), + msi_domain = pci_msi_create_irq_domain(priv->domain_handle, &pch_msi_domain_info, middle_domain); if (!msi_domain) { @@ -183,19 +186,11 @@ static int pch_msi_init_domains(struct pch_msi_data *priv, return 0; } -static int pch_msi_init(struct device_node *node, - struct device_node *parent) +static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count, + struct irq_domain *parent_domain, struct fwnode_handle *domain_handle) { - struct pch_msi_data *priv; - struct irq_domain *parent_domain; - struct resource res; int ret; - - parent_domain = irq_find_host(parent); - if (!parent_domain) { - pr_err("Failed to find the parent domain\n"); - return -ENXIO; - } + struct pch_msi_data *priv; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -203,38 +198,18 @@ static int pch_msi_init(struct device_node *node, mutex_init(&priv->msi_map_lock); - ret = of_address_to_resource(node, 0, &res); - if (ret) { - pr_err("Failed to allocate resource\n"); - goto err_priv; - } - - priv->doorbell = res.start; - - if (of_property_read_u32(node, "loongson,msi-base-vec", - &priv->irq_first)) { - pr_err("Unable to parse MSI vec base\n"); - ret = -EINVAL; - goto err_priv; - } - - if (of_property_read_u32(node, "loongson,msi-num-vecs", - &priv->num_irqs)) { - pr_err("Unable to parse MSI vec number\n"); - ret = -EINVAL; - goto err_priv; - } + priv->doorbell = msg_address; + priv->irq_first = irq_base; + priv->num_irqs = irq_count; priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL); - if (!priv->msi_map) { - ret = -ENOMEM; + if (!priv->msi_map) goto err_priv; - } pr_debug("Registering %d MSIs, starting at %d\n", priv->num_irqs, priv->irq_first); - ret = pch_msi_init_domains(priv, node, parent_domain); + ret = pch_msi_init_domains(priv, parent_domain, domain_handle); if (ret) goto err_map; @@ -244,7 +219,74 @@ static int pch_msi_init(struct device_node *node, kfree(priv->msi_map); err_priv: kfree(priv); - return ret; + + return -EINVAL; +} + +#ifdef CONFIG_OF + +int pch_msi_of_init(struct device_node *node, struct device_node *parent) +{ + int err; + int irq_base, irq_count; + struct resource res; + struct irq_domain *parent_domain; + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("Failed to find the parent domain\n"); + return -ENXIO; + } + + if (of_address_to_resource(node, 0, &res)) { + pr_err("Failed to allocate resource\n"); + return -EINVAL; + } + + if (of_property_read_u32(node, "loongson,msi-base-vec", &irq_base)) { + pr_err("Unable to parse MSI vec base\n"); + return -EINVAL; + } + + if (of_property_read_u32(node, "loongson,msi-num-vecs", &irq_count)) { + pr_err("Unable to parse MSI vec number\n"); + return -EINVAL; + } + + err = pch_msi_init(res.start, irq_base, irq_count, parent_domain, of_node_to_fwnode(node)); + if (err < 0) + return err; + + return 0; +} + +IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_of_init); + +#endif + +#ifdef CONFIG_ACPI + +struct fwnode_handle *pch_msi_acpi_init(struct fwnode_handle *parent, + struct acpi_madt_msi_pic *acpi_pchmsi) +{ + int ret; + struct irq_domain *parent_domain; + struct fwnode_handle *domain_handle; + + parent_domain = irq_find_matching_fwnode(parent, DOMAIN_BUS_ANY); + if (!parent_domain) { + pr_err("Failed to find the parent domain\n"); + return NULL; + } + + domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchmsi); + + ret = pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start, + acpi_pchmsi->count, parent_domain, domain_handle); + if (ret < 0) + return NULL; + + return domain_handle; } -IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_init); +#endif -- 2.27.0
next prev parent reply other threads:[~2021-08-16 7:56 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-16 7:52 [PATCH V2 00/10] irqchip: Add LoongArch-related irqchip drivers Huacai Chen 2021-08-16 7:52 ` [PATCH V2 01/10] irqchip: Adjust Kconfig for Loongson Huacai Chen 2021-08-16 7:52 ` [PATCH V2 02/10] irqchip/loongson-pch-pic: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 03/10] irqchip/loongson-pch-pic: Add suspend/resume support Huacai Chen 2021-08-16 7:52 ` Huacai Chen [this message] 2021-08-16 7:52 ` [PATCH V2 05/10] irqchip/loongson-htvec: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 06/10] irqchip/loongson-htvec: Add suspend/resume support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 07/10] irqchip/loongson-liointc: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 08/10] irqchip: Add LoongArch CPU interrupt controller support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 09/10] irqchip: Add Loongson Extended I/O " Huacai Chen 2021-08-16 7:52 ` [PATCH V2 10/10] irqchip: Add Loongson PCH LPC " Huacai Chen
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