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From: Huacai Chen <chenhuacai@loongson.cn> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org> Cc: linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>, Huacai Chen <chenhuacai@gmail.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Huacai Chen <chenhuacai@loongson.cn> Subject: [PATCH V2 05/10] irqchip/loongson-htvec: Add ACPI init support Date: Mon, 16 Aug 2021 15:52:47 +0800 [thread overview] Message-ID: <20210816075252.4003406-6-chenhuacai@loongson.cn> (raw) In-Reply-To: <20210816075252.4003406-1-chenhuacai@loongson.cn> We are preparing to add new Loongson (based on LoongArch, not MIPS) support. LoongArch use ACPI other than DT as its boot protocol, so add ACPI init support. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> --- drivers/irqchip/irq-loongson-htvec.c | 120 +++++++++++++++++++-------- 1 file changed, 86 insertions(+), 34 deletions(-) diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c index 60a335d7e64e..e969e4588600 100644 --- a/drivers/irqchip/irq-loongson-htvec.c +++ b/drivers/irqchip/irq-loongson-htvec.c @@ -20,7 +20,6 @@ /* Registers */ #define HTVEC_EN_OFF 0x20 #define HTVEC_MAX_PARENT_IRQ 8 - #define VEC_COUNT_PER_REG 32 #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG) #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG) @@ -30,8 +29,11 @@ struct htvec { void __iomem *base; struct irq_domain *htvec_domain; raw_spinlock_t htvec_lock; + struct fwnode_handle *domain_handle; }; +struct htvec *htvec_priv; + static void htvec_irq_dispatch(struct irq_desc *desc) { int i; @@ -155,64 +157,114 @@ static void htvec_reset(struct htvec *priv) } } -static int htvec_of_init(struct device_node *node, - struct device_node *parent) +static int htvec_init(phys_addr_t addr, unsigned long size, + int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) { + int i; struct htvec *priv; - int err, parent_irq[8], i; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; + priv->num_parents = num_parents; + priv->base = ioremap(addr, size); + priv->domain_handle = domain_handle; raw_spin_lock_init(&priv->htvec_lock); - priv->base = of_iomap(node, 0); - if (!priv->base) { - err = -ENOMEM; - goto free_priv; - } - - /* Interrupt may come from any of the 8 interrupt lines */ - for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) { - parent_irq[i] = irq_of_parse_and_map(node, i); - if (parent_irq[i] <= 0) - break; - - priv->num_parents++; - } - if (!priv->num_parents) { - pr_err("Failed to get parent irqs\n"); - err = -ENODEV; - goto iounmap_base; - } - - priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node), + /* Setup IRQ domain */ + priv->htvec_domain = irq_domain_create_linear(priv->domain_handle, (VEC_COUNT_PER_REG * priv->num_parents), &htvec_domain_ops, priv); if (!priv->htvec_domain) { - pr_err("Failed to create IRQ domain\n"); - err = -ENOMEM; - goto irq_dispose; + pr_err("loongson-htvec: cannot add IRQ domain\n"); + goto iounmap_base; } htvec_reset(priv); - for (i = 0; i < priv->num_parents; i++) + for (i = 0; i < priv->num_parents; i++) { irq_set_chained_handler_and_data(parent_irq[i], htvec_irq_dispatch, priv); + } + + htvec_priv = priv; return 0; -irq_dispose: - for (; i > 0; i--) - irq_dispose_mapping(parent_irq[i - 1]); iounmap_base: iounmap(priv->base); -free_priv: + priv->domain_handle = NULL; kfree(priv); - return err; + return -EINVAL; +} + +#ifdef CONFIG_OF + +static int htvec_of_init(struct device_node *node, + struct device_node *parent) +{ + int i, err; + int num_parents, parent_irq[8]; + struct resource res; + + if (of_address_to_resource(node, 0, &res)) + return -EINVAL; + + /* Interrupt may come from any of the 8 interrupt lines */ + for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) { + parent_irq[i] = irq_of_parse_and_map(node, i); + if (parent_irq[i] <= 0) + break; + + num_parents++; + } + + err = htvec_init(res.start, resource_size(&res), + num_parents, parent_irq, of_node_to_fwnode(node)); + if (err < 0) + return err; + + return 0; } IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init); + +#endif + +#ifdef CONFIG_ACPI + +struct fwnode_handle *htvec_acpi_init(struct fwnode_handle *parent, + struct acpi_madt_ht_pic *acpi_htvec) +{ + int i, ret; + int num_parents, parent_irq[8]; + struct irq_fwspec fwspec; + struct fwnode_handle *domain_handle; + + num_parents = HTVEC_MAX_PARENT_IRQ; + + /* Interrupt may come from any of the 8 interrupt lines */ + for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) { + fwspec.fwnode = parent; + fwspec.param[0] = acpi_htvec->cascade[i]; + fwspec.param_count = 1; + parent_irq[i] = irq_create_fwspec_mapping(&fwspec); + } + + domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_htvec); + if (!domain_handle) { + pr_err("Unable to allocate domain handle\n"); + return NULL; + } + + ret = htvec_init(acpi_htvec->address, acpi_htvec->size, + num_parents, parent_irq, domain_handle); + if (ret < 0) + return NULL; + + return domain_handle; +} + +#endif -- 2.27.0
next prev parent reply other threads:[~2021-08-16 7:57 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-16 7:52 [PATCH V2 00/10] irqchip: Add LoongArch-related irqchip drivers Huacai Chen 2021-08-16 7:52 ` [PATCH V2 01/10] irqchip: Adjust Kconfig for Loongson Huacai Chen 2021-08-16 7:52 ` [PATCH V2 02/10] irqchip/loongson-pch-pic: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 03/10] irqchip/loongson-pch-pic: Add suspend/resume support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 04/10] irqchip/loongson-pch-msi: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` Huacai Chen [this message] 2021-08-16 7:52 ` [PATCH V2 06/10] irqchip/loongson-htvec: Add suspend/resume support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 07/10] irqchip/loongson-liointc: Add ACPI init support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 08/10] irqchip: Add LoongArch CPU interrupt controller support Huacai Chen 2021-08-16 7:52 ` [PATCH V2 09/10] irqchip: Add Loongson Extended I/O " Huacai Chen 2021-08-16 7:52 ` [PATCH V2 10/10] irqchip: Add Loongson PCH LPC " Huacai Chen
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