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From: Bjorn Helgaas <helgaas@kernel.org> To: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh+dt@kernel.org>, Tom Joseph <tjoseph@cadence.com>, Jingoo Han <jingoohan1@gmail.com>, Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Marek Vasut <marek.vasut+renesas@gmail.com>, Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>, Shawn Lin <shawn.lin@rock-chips.com>, Heiko Stuebner <heiko@sntech.de>, Jonathan Corbet <corbet@lwn.net>, Arnd Bergmann <arnd@arndb.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lokesh Vutla <lokeshvutla@ti.com> Subject: Re: [PATCH v8 5/8] PCI: cadence: Simplify code to get register base address for configuring BAR Date: Tue, 17 Aug 2021 10:24:12 -0500 [thread overview] Message-ID: <20210817152412.GA3016169@bjorn-Precision-5520> (raw) In-Reply-To: <20210811064656.15399-6-kishon@ti.com> On Wed, Aug 11, 2021 at 12:16:53PM +0530, Kishon Vijay Abraham I wrote: > No functional change. Simplify code to get register base address for > configuring PCI BAR. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../pci/controller/cadence/pcie-cadence-ep.c | 18 ++++-------------- > drivers/pci/controller/cadence/pcie-cadence.h | 2 ++ > 2 files changed, 6 insertions(+), 14 deletions(-) > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c > index 912a15be8bfd..f337f0842400 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c > @@ -97,13 +97,8 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, > cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), > addr1); > > - if (bar < BAR_4) { > - reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); > - b = bar; > - } else { > - reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); > - b = bar - BAR_4; > - } > + reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn); > + b = (bar < BAR_4) ? bar : bar - BAR_4; > > cfg = cdns_pcie_readl(pcie, reg); > cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | > @@ -126,13 +121,8 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, > enum pci_barno bar = epf_bar->barno; > u32 reg, cfg, b, ctrl; > > - if (bar < BAR_4) { > - reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); > - b = bar; > - } else { > - reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); > - b = bar - BAR_4; > - } > + reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn); > + b = (bar < BAR_4) ? bar : bar - BAR_4; > > ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED; > cfg = cdns_pcie_readl(pcie, reg); > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h > index 30db2d68c17a..d5b1fcf2c39d 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence.h > +++ b/drivers/pci/controller/cadence/pcie-cadence.h > @@ -46,6 +46,8 @@ > #define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 > > /* Endpoint Function f BAR b Configuration Registers */ > +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ > + (((bar) < 4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) Why do we use "BAR_4" above and "4" here? Shouldn't they look the same? > #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ > (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) > #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ > -- > 2.17.1 >
next prev parent reply other threads:[~2021-08-17 15:24 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-11 6:46 [PATCH v8 0/8] Add SR-IOV support in PCIe Endpoint Core Kishon Vijay Abraham I 2021-08-11 6:46 ` [PATCH v8 1/8] dt-bindings: PCI: pci-ep: Add binding to specify virtual function Kishon Vijay Abraham I 2021-08-11 6:46 ` [PATCH v8 2/8] PCI: endpoint: Add support to add virtual function in endpoint core Kishon Vijay Abraham I 2021-08-11 6:46 ` [PATCH v8 3/8] PCI: endpoint: Add support to link a physical function to a virtual function Kishon Vijay Abraham I 2021-08-11 6:46 ` [PATCH v8 4/8] PCI: endpoint: Add virtual function number in pci_epc ops Kishon Vijay Abraham I 2021-08-11 6:46 ` [PATCH v8 5/8] PCI: cadence: Simplify code to get register base address for configuring BAR Kishon Vijay Abraham I 2021-08-17 15:24 ` Bjorn Helgaas [this message] 2021-08-11 6:46 ` [PATCH v8 6/8] PCI: cadence: Add support to configure virtual functions Kishon Vijay Abraham I 2021-08-17 15:38 ` Bjorn Helgaas 2021-08-18 13:55 ` Kishon Vijay Abraham I 2021-08-11 6:46 ` [PATCH v8 7/8] misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device Kishon Vijay Abraham I 2021-08-11 6:46 ` [PATCH v8 8/8] Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV Kishon Vijay Abraham I 2021-08-16 17:01 ` [PATCH v8 0/8] Add SR-IOV support in PCIe Endpoint Core Lorenzo Pieralisi
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