LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: "David E. Box" <david.e.box@linux.intel.com>
To: lee.jones@linaro.org, hdegoede@redhat.com,
	mgross@linux.intel.com, bhelgaas@google.com,
	srinivas.pandruvada@intel.com, andy.shevchenko@gmail.com
Cc: "David E. Box" <david.e.box@linux.intel.com>,
	linux-kernel@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH v2 1/5] PCI: Add #defines for accessing PCIE DVSEC fields
Date: Tue, 17 Aug 2021 15:40:14 -0700	[thread overview]
Message-ID: <20210817224018.1013192-2-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20210817224018.1013192-1-david.e.box@linux.intel.com>

Add #defines for accessing Vendor ID, Revision, Length, and ID offsets
in the Designated Vendor Specific Extended Capability (DVSEC). Defined
in PCIe r5.0, sec 7.9.6.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---

V2:	Unchanged

 include/uapi/linux/pci_regs.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e709ae8235e7..57ee51f19283 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1080,7 +1080,11 @@
 
 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
 #define PCI_DVSEC_HEADER1		0x4 /* Designated Vendor-Specific Header1 */
+#define  PCI_DVSEC_HEADER1_VID(x)	((x) & 0xffff)
+#define  PCI_DVSEC_HEADER1_REV(x)	(((x) >> 16) & 0xf)
+#define  PCI_DVSEC_HEADER1_LEN(x)	(((x) >> 20) & 0xfff)
 #define PCI_DVSEC_HEADER2		0x8 /* Designated Vendor-Specific Header2 */
+#define  PCI_DVSEC_HEADER2_ID(x)		((x) & 0xffff)
 
 /* Data Link Feature */
 #define PCI_DLF_CAP		0x04	/* Capabilities Register */
-- 
2.25.1


  reply	other threads:[~2021-08-17 22:42 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-17 22:40 [PATCH v2 0/5] MFD: intel_pmt: Add general DVSEC/VSEC support David E. Box
2021-08-17 22:40 ` David E. Box [this message]
2021-08-17 22:40 ` [PATCH v2 2/5] MFD: intel_pmt: Support non-PMT capabilities David E. Box
2021-08-17 22:40 ` [PATCH v2 3/5] MFD: intel_pmt: Add support for PCIe VSEC structures David E. Box
2021-08-17 22:40 ` [PATCH v2 4/5] platform/x86: intel_pmt_telemetry: Ignore zero sized entries David E. Box
2021-08-18  7:52   ` Hans de Goede
2021-08-17 22:40 ` [PATCH v2 5/5] MFD: intel_pmt: Add DG2 support David E. Box
2021-08-18  7:51 ` [PATCH v2 0/5] MFD: intel_pmt: Add general DVSEC/VSEC support Hans de Goede
2021-08-19  9:36   ` Lee Jones

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210817224018.1013192-2-david.e.box@linux.intel.com \
    --to=david.e.box@linux.intel.com \
    --cc=andy.shevchenko@gmail.com \
    --cc=bhelgaas@google.com \
    --cc=hdegoede@redhat.com \
    --cc=lee.jones@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=mgross@linux.intel.com \
    --cc=platform-driver-x86@vger.kernel.org \
    --cc=srinivas.pandruvada@intel.com \
    --subject='Re: [PATCH v2 1/5] PCI: Add #defines for accessing PCIE DVSEC fields' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).