LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
* [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
@ 2021-08-19  0:43 Deepak Sharma
  2021-08-25 18:07 ` Rafael J. Wysocki
  2021-08-26 23:04 ` Thomas Gleixner
  0 siblings, 2 replies; 9+ messages in thread
From: Deepak Sharma @ 2021-08-19  0:43 UTC (permalink / raw)
  To: deepak.sharma
  Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Thomas Gleixner,
	Ingo Molnar, Borislav Petkov,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

AMD CPU which support C3 shares cache. Its not necessary to flush the
caches in software before entering C3. This will cause performance drop
for the cores which share some caches. ARB_DIS is not used with current
AMD C state implementation. So set related flags correctly.

Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
---
 arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 7de599eba7f0..62a5986d625a 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 		 */
 		flags->bm_control = 0;
 	}
+	if (c->x86_vendor == X86_VENDOR_AMD) {
+		/*
+		 * For all AMD CPUs that support C3, caches should not be
+		 * flushed by software while entering C3 type state. Set
+		 * bm->check to 1 so that kernel doesn't need to execute
+		 * cache flush operation.
+		 */
+		flags->bm_check = 1;
+		/*
+		 * In current AMD C state implementation ARB_DIS is no longer
+		 * used. So set bm_control to zero to indicate ARB_DIS is not
+		 * required while entering C3 type state.
+		 */
+		flags->bm_control = 0;
+	}
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-08-19  0:43 [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs Deepak Sharma
@ 2021-08-25 18:07 ` Rafael J. Wysocki
  2021-09-01  2:14   ` Deepak Sharma
  2021-08-26 23:04 ` Thomas Gleixner
  1 sibling, 1 reply; 9+ messages in thread
From: Rafael J. Wysocki @ 2021-08-25 18:07 UTC (permalink / raw)
  To: Deepak Sharma
  Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Thomas Gleixner,
	Ingo Molnar, Borislav Petkov,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>
> AMD CPU which support C3 shares cache. Its not necessary to flush the
> caches in software before entering C3. This will cause performance drop
> for the cores which share some caches. ARB_DIS is not used with current
> AMD C state implementation. So set related flags correctly.
>
> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>

Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!

> ---
>  arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index 7de599eba7f0..62a5986d625a 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>                  */
>                 flags->bm_control = 0;
>         }
> +       if (c->x86_vendor == X86_VENDOR_AMD) {
> +               /*
> +                * For all AMD CPUs that support C3, caches should not be
> +                * flushed by software while entering C3 type state. Set
> +                * bm->check to 1 so that kernel doesn't need to execute
> +                * cache flush operation.
> +                */
> +               flags->bm_check = 1;
> +               /*
> +                * In current AMD C state implementation ARB_DIS is no longer
> +                * used. So set bm_control to zero to indicate ARB_DIS is not
> +                * required while entering C3 type state.
> +                */
> +               flags->bm_control = 0;
> +       }
>  }
>  EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-08-19  0:43 [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs Deepak Sharma
  2021-08-25 18:07 ` Rafael J. Wysocki
@ 2021-08-26 23:04 ` Thomas Gleixner
  2021-09-01  2:10   ` Deepak Sharma
  1 sibling, 1 reply; 9+ messages in thread
From: Thomas Gleixner @ 2021-08-26 23:04 UTC (permalink / raw)
  To: Deepak Sharma, deepak.sharma
  Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Ingo Molnar,
	Borislav Petkov, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Wed, Aug 18 2021 at 17:43, Deepak Sharma wrote:

> AMD CPU which support C3 shares cache. Its not necessary to flush the
> caches in software before entering C3. This will cause performance drop
> for the cores which share some caches. ARB_DIS is not used with current
> AMD C state implementation. So set related flags correctly.
>
> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> ---
>  arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index 7de599eba7f0..62a5986d625a 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>  		 */
>  		flags->bm_control = 0;
>  	}
> +	if (c->x86_vendor == X86_VENDOR_AMD) {
> +		/*
> +		 * For all AMD CPUs that support C3, caches should not be
> +		 * flushed by software while entering C3 type state. Set
> +		 * bm->check to 1 so that kernel doesn't need to execute
> +		 * cache flush operation.
> +		 */
> +		flags->bm_check = 1;
> +		/*
> +		 * In current AMD C state implementation ARB_DIS is no longer

Fine for current implementations, but what about older implementations?

Thanks,

        tglx

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-08-26 23:04 ` Thomas Gleixner
@ 2021-09-01  2:10   ` Deepak Sharma
  0 siblings, 0 replies; 9+ messages in thread
From: Deepak Sharma @ 2021-09-01  2:10 UTC (permalink / raw)
  To: Thomas Gleixner, Deepak Sharma
  Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Ingo Molnar,
	Borislav Petkov, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)


On 8/26/21 4:04 PM, Thomas Gleixner wrote:
> On Wed, Aug 18 2021 at 17:43, Deepak Sharma wrote:
>
>> AMD CPU which support C3 shares cache. Its not necessary to flush the
>> caches in software before entering C3. This will cause performance drop
>> for the cores which share some caches. ARB_DIS is not used with current
>> AMD C state implementation. So set related flags correctly.
>>
>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
>> ---
>>   arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
>> index 7de599eba7f0..62a5986d625a 100644
>> --- a/arch/x86/kernel/acpi/cstate.c
>> +++ b/arch/x86/kernel/acpi/cstate.c
>> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>>   		 */
>>   		flags->bm_control = 0;
>>   	}
>> +	if (c->x86_vendor == X86_VENDOR_AMD) {
>> +		/*
>> +		 * For all AMD CPUs that support C3, caches should not be
>> +		 * flushed by software while entering C3 type state. Set
>> +		 * bm->check to 1 so that kernel doesn't need to execute
>> +		 * cache flush operation.
>> +		 */
>> +		flags->bm_check = 1;
>> +		/*
>> +		 * In current AMD C state implementation ARB_DIS is no longer
> Fine for current implementations, but what about older implementations?
We are internally discussing about its validity on much older 
implementations. Will send subsequent patch based on the conclusion.


Thanks,

Deepak


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-08-25 18:07 ` Rafael J. Wysocki
@ 2021-09-01  2:14   ` Deepak Sharma
  2021-09-01 12:45     ` Rafael J. Wysocki
  0 siblings, 1 reply; 9+ messages in thread
From: Deepak Sharma @ 2021-09-01  2:14 UTC (permalink / raw)
  To: Rafael J. Wysocki, Deepak Sharma
  Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Thomas Gleixner,
	Ingo Molnar, Borislav Petkov,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)


On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
> On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>> AMD CPU which support C3 shares cache. Its not necessary to flush the
>> caches in software before entering C3. This will cause performance drop
>> for the cores which share some caches. ARB_DIS is not used with current
>> AMD C state implementation. So set related flags correctly.
>>
>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
> Optimize C3 entry on AMD CPUs", thanks!

I might need to send subsequent patch for this. Can you please point me 
to git and branch where this has been merged.

>> ---
>>   arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
>> index 7de599eba7f0..62a5986d625a 100644
>> --- a/arch/x86/kernel/acpi/cstate.c
>> +++ b/arch/x86/kernel/acpi/cstate.c
>> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>>                   */
>>                  flags->bm_control = 0;
>>          }
>> +       if (c->x86_vendor == X86_VENDOR_AMD) {
>> +               /*
>> +                * For all AMD CPUs that support C3, caches should not be
>> +                * flushed by software while entering C3 type state. Set
>> +                * bm->check to 1 so that kernel doesn't need to execute
>> +                * cache flush operation.
>> +                */
>> +               flags->bm_check = 1;
>> +               /*
>> +                * In current AMD C state implementation ARB_DIS is no longer
>> +                * used. So set bm_control to zero to indicate ARB_DIS is not
>> +                * required while entering C3 type state.
>> +                */
>> +               flags->bm_control = 0;
>> +       }
>>   }
>>   EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>>
>> --
>> 2.25.1
>>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-09-01  2:14   ` Deepak Sharma
@ 2021-09-01 12:45     ` Rafael J. Wysocki
  2021-09-22  3:50       ` Sharma, Deepak
  0 siblings, 1 reply; 9+ messages in thread
From: Rafael J. Wysocki @ 2021-09-01 12:45 UTC (permalink / raw)
  To: Deepak Sharma
  Cc: Rafael J. Wysocki, Deepak Sharma, Rafael J. Wysocki, Len Brown,
	Pavel Machek, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Wed, Sep 1, 2021 at 4:14 AM Deepak Sharma <deesharm@amd.com> wrote:
>
>
> On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
> > On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
> >> AMD CPU which support C3 shares cache. Its not necessary to flush the
> >> caches in software before entering C3. This will cause performance drop
> >> for the cores which share some caches. ARB_DIS is not used with current
> >> AMD C state implementation. So set related flags correctly.
> >>
> >> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> > Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
> > Optimize C3 entry on AMD CPUs", thanks!
>
> I might need to send subsequent patch for this. Can you please point me
> to git and branch where this has been merged.

git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next

> >> ---
> >>   arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
> >>   1 file changed, 15 insertions(+)
> >>
> >> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> >> index 7de599eba7f0..62a5986d625a 100644
> >> --- a/arch/x86/kernel/acpi/cstate.c
> >> +++ b/arch/x86/kernel/acpi/cstate.c
> >> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> >>                   */
> >>                  flags->bm_control = 0;
> >>          }
> >> +       if (c->x86_vendor == X86_VENDOR_AMD) {
> >> +               /*
> >> +                * For all AMD CPUs that support C3, caches should not be
> >> +                * flushed by software while entering C3 type state. Set
> >> +                * bm->check to 1 so that kernel doesn't need to execute
> >> +                * cache flush operation.
> >> +                */
> >> +               flags->bm_check = 1;
> >> +               /*
> >> +                * In current AMD C state implementation ARB_DIS is no longer
> >> +                * used. So set bm_control to zero to indicate ARB_DIS is not
> >> +                * required while entering C3 type state.
> >> +                */
> >> +               flags->bm_control = 0;
> >> +       }
> >>   }
> >>   EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
> >>
> >> --
> >> 2.25.1
> >>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-09-01 12:45     ` Rafael J. Wysocki
@ 2021-09-22  3:50       ` Sharma, Deepak
  2021-09-22 12:47         ` Rafael J. Wysocki
  0 siblings, 1 reply; 9+ messages in thread
From: Sharma, Deepak @ 2021-09-22  3:50 UTC (permalink / raw)
  To: Rafael J. Wysocki
  Cc: Deepak Sharma, Rafael J. Wysocki, Len Brown, Pavel Machek,
	Thomas Gleixner, Ingo Molnar, Borislav Petkov,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

Hi Rafael,

On 9/1/2021 5:45 AM, Rafael J. Wysocki wrote:
> On Wed, Sep 1, 2021 at 4:14 AM Deepak Sharma <deesharm@amd.com> wrote:
>>
>> On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
>>> On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>>>> AMD CPU which support C3 shares cache. Its not necessary to flush the
>>>> caches in software before entering C3. This will cause performance drop
>>>> for the cores which share some caches. ARB_DIS is not used with current
>>>> AMD C state implementation. So set related flags correctly.
>>>>
>>>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
>>> Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
>>> Optimize C3 entry on AMD CPUs", thanks!
>> I might need to send subsequent patch for this. Can you please point me
>> to git and branch where this has been merged.
> git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next

Still I am not able to see this patch merged on linux-next branch.

Thanks,

Deepak

>>>> ---
>>>>    arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
>>>>    1 file changed, 15 insertions(+)
>>>>
>>>> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
>>>> index 7de599eba7f0..62a5986d625a 100644
>>>> --- a/arch/x86/kernel/acpi/cstate.c
>>>> +++ b/arch/x86/kernel/acpi/cstate.c
>>>> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>>>>                    */
>>>>                   flags->bm_control = 0;
>>>>           }
>>>> +       if (c->x86_vendor == X86_VENDOR_AMD) {
>>>> +               /*
>>>> +                * For all AMD CPUs that support C3, caches should not be
>>>> +                * flushed by software while entering C3 type state. Set
>>>> +                * bm->check to 1 so that kernel doesn't need to execute
>>>> +                * cache flush operation.
>>>> +                */
>>>> +               flags->bm_check = 1;
>>>> +               /*
>>>> +                * In current AMD C state implementation ARB_DIS is no longer
>>>> +                * used. So set bm_control to zero to indicate ARB_DIS is not
>>>> +                * required while entering C3 type state.
>>>> +                */
>>>> +               flags->bm_control = 0;
>>>> +       }
>>>>    }
>>>>    EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>>>>
>>>> --
>>>> 2.25.1
>>>>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-09-22  3:50       ` Sharma, Deepak
@ 2021-09-22 12:47         ` Rafael J. Wysocki
  2021-09-24  5:42           ` Sharma, Deepak
  0 siblings, 1 reply; 9+ messages in thread
From: Rafael J. Wysocki @ 2021-09-22 12:47 UTC (permalink / raw)
  To: Sharma, Deepak
  Cc: Rafael J. Wysocki, Deepak Sharma, Rafael J. Wysocki, Len Brown,
	Pavel Machek, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Wed, Sep 22, 2021 at 5:50 AM Sharma, Deepak <deesharm@amd.com> wrote:
>
> Hi Rafael,
>
> On 9/1/2021 5:45 AM, Rafael J. Wysocki wrote:
> > On Wed, Sep 1, 2021 at 4:14 AM Deepak Sharma <deesharm@amd.com> wrote:
> >>
> >> On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
> >>> On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
> >>>> AMD CPU which support C3 shares cache. Its not necessary to flush the
> >>>> caches in software before entering C3. This will cause performance drop
> >>>> for the cores which share some caches. ARB_DIS is not used with current
> >>>> AMD C state implementation. So set related flags correctly.
> >>>>
> >>>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> >>> Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
> >>> Optimize C3 entry on AMD CPUs", thanks!
> >> I might need to send subsequent patch for this. Can you please point me
> >> to git and branch where this has been merged.
> > git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next
>
> Still I am not able to see this patch merged on linux-next branch.

It was there, but got dropped before the merge window due to the
unclear next steps.

I'd rather see this resent along with the subsequent patch you were
talking about.

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
  2021-09-22 12:47         ` Rafael J. Wysocki
@ 2021-09-24  5:42           ` Sharma, Deepak
  0 siblings, 0 replies; 9+ messages in thread
From: Sharma, Deepak @ 2021-09-24  5:42 UTC (permalink / raw)
  To: Rafael J. Wysocki
  Cc: Deepak Sharma, Rafael J. Wysocki, Len Brown, Pavel Machek,
	Thomas Gleixner, Ingo Molnar, Borislav Petkov,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	H. Peter Anvin, open list:SUSPEND TO RAM,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)


On 9/22/2021 5:47 AM, Rafael J. Wysocki wrote:
> On Wed, Sep 22, 2021 at 5:50 AM Sharma, Deepak <deesharm@amd.com> wrote:
>> Hi Rafael,
>>
>> On 9/1/2021 5:45 AM, Rafael J. Wysocki wrote:
>>> On Wed, Sep 1, 2021 at 4:14 AM Deepak Sharma <deesharm@amd.com> wrote:
>>>> On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
>>>>> On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>>>>>> AMD CPU which support C3 shares cache. Its not necessary to flush the
>>>>>> caches in software before entering C3. This will cause performance drop
>>>>>> for the cores which share some caches. ARB_DIS is not used with current
>>>>>> AMD C state implementation. So set related flags correctly.
>>>>>>
>>>>>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
>>>>> Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
>>>>> Optimize C3 entry on AMD CPUs", thanks!
>>>> I might need to send subsequent patch for this. Can you please point me
>>>> to git and branch where this has been merged.
>>> git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next
>> Still I am not able to see this patch merged on linux-next branch.
> It was there, but got dropped before the merge window due to the
> unclear next steps.
>
> I'd rather see this resent along with the subsequent patch you were
> talking about.
Thanks for the clarification. I will resend patch with subsequent 
changes which will have support for zen onward CPU's.

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2021-09-24  5:42 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-19  0:43 [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs Deepak Sharma
2021-08-25 18:07 ` Rafael J. Wysocki
2021-09-01  2:14   ` Deepak Sharma
2021-09-01 12:45     ` Rafael J. Wysocki
2021-09-22  3:50       ` Sharma, Deepak
2021-09-22 12:47         ` Rafael J. Wysocki
2021-09-24  5:42           ` Sharma, Deepak
2021-08-26 23:04 ` Thomas Gleixner
2021-09-01  2:10   ` Deepak Sharma

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).