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* [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
@ 2021-08-25 13:04 Krzysztof Kozlowski
  2021-08-25 13:04 ` [PATCH v2 2/5] riscv: dts: sifive: fix Unleashed board compatible Krzysztof Kozlowski
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-25 13:04 UTC (permalink / raw)
  To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Krzysztof Kozlowski, Atish Patra, Sagar Shrikant Kadam,
	devicetree, linux-riscv, linux-kernel

The compatible "issi,is25wp256" is undocumented and instead only a
generic jedec,spi-nor should be used (if appropriate).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. New patch
---
 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 2 +-
 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 60846e88ae4b..633b31b6e25c 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -63,7 +63,7 @@ &i2c0 {
 &qspi0 {
 	status = "okay";
 	flash@0 {
-		compatible = "issi,is25wp256", "jedec,spi-nor";
+		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <50000000>;
 		m25p,fast-read;
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
index 2e4ea84f27e7..9b0b9b85040e 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -211,7 +211,7 @@ vdd_ldo11: ldo11 {
 &qspi0 {
 	status = "okay";
 	flash@0 {
-		compatible = "issi,is25wp256", "jedec,spi-nor";
+		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <50000000>;
 		m25p,fast-read;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 2/5] riscv: dts: sifive: fix Unleashed board compatible
  2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
@ 2021-08-25 13:04 ` Krzysztof Kozlowski
  2021-08-25 13:04 ` [PATCH v2 3/5] riscv: dts: sifive: drop duplicated nodes and properties in sifive Krzysztof Kozlowski
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-25 13:04 UTC (permalink / raw)
  To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Krzysztof Kozlowski, Atish Patra, Sagar Shrikant Kadam,
	devicetree, linux-riscv, linux-kernel

Add missing sifive,fu540 compatible to fix dtbs_check warnings:

  arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: /: compatible: 'oneOf' conditional failed, one must be fixed:
  ['sifive,hifive-unleashed-a00', 'sifive,fu540-c000'] is too short
  'sifive,hifive-unleashed-a00' is not one of ['sifive,hifive-unmatched-a00']
  'sifive,fu740-c000' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. None
---
 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 633b31b6e25c..2b4af7b4cc2f 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -11,7 +11,8 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 	model = "SiFive HiFive Unleashed A00";
-	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
+		     "sifive,fu540";
 
 	chosen {
 		stdout-path = "serial0";
-- 
2.30.2


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 3/5] riscv: dts: sifive: drop duplicated nodes and properties in sifive
  2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
  2021-08-25 13:04 ` [PATCH v2 2/5] riscv: dts: sifive: fix Unleashed board compatible Krzysztof Kozlowski
@ 2021-08-25 13:04 ` Krzysztof Kozlowski
  2021-08-25 13:06 ` Krzysztof Kozlowski
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-25 13:04 UTC (permalink / raw)
  To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Krzysztof Kozlowski, Atish Patra, Sagar Shrikant Kadam,
	devicetree, linux-riscv, linux-kernel

The DTSI file defines soc node and address/size cells, so there is no
point in duplicating it in DTS file.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. None
---
 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 5 -----
 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 5 -----
 2 files changed, 10 deletions(-)

diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 2b4af7b4cc2f..ba304d4c455c 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -8,8 +8,6 @@
 #define RTCCLK_FREQ		1000000
 
 / {
-	#address-cells = <2>;
-	#size-cells = <2>;
 	model = "SiFive HiFive Unleashed A00";
 	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
 		     "sifive,fu540";
@@ -27,9 +25,6 @@ memory@80000000 {
 		reg = <0x0 0x80000000 0x2 0x00000000>;
 	};
 
-	soc {
-	};
-
 	hfclk: hfclk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
index 9b0b9b85040e..4f66919215f6 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -8,8 +8,6 @@
 #define RTCCLK_FREQ		1000000
 
 / {
-	#address-cells = <2>;
-	#size-cells = <2>;
 	model = "SiFive HiFive Unmatched A00";
 	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
 		     "sifive,fu740";
@@ -27,9 +25,6 @@ memory@80000000 {
 		reg = <0x0 0x80000000 0x4 0x00000000>;
 	};
 
-	soc {
-	};
-
 	hfclk: hfclk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
-- 
2.30.2


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 3/5] riscv: dts: sifive: drop duplicated nodes and properties in sifive
  2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
  2021-08-25 13:04 ` [PATCH v2 2/5] riscv: dts: sifive: fix Unleashed board compatible Krzysztof Kozlowski
  2021-08-25 13:04 ` [PATCH v2 3/5] riscv: dts: sifive: drop duplicated nodes and properties in sifive Krzysztof Kozlowski
@ 2021-08-25 13:06 ` Krzysztof Kozlowski
  2021-08-25 13:06 ` [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic Krzysztof Kozlowski
  2021-08-25 13:07 ` [PATCH v2 5/5] riscv: dts: sifive: add missing compatible for plic Krzysztof Kozlowski
  4 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-25 13:06 UTC (permalink / raw)
  To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Krzysztof Kozlowski, Atish Patra, Sagar Shrikant Kadam,
	devicetree, linux-riscv, linux-kernel

The DTSI file defines soc node and address/size cells, so there is no
point in duplicating it in DTS file.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. None
---
 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 5 -----
 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 5 -----
 2 files changed, 10 deletions(-)

diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 2b4af7b4cc2f..ba304d4c455c 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -8,8 +8,6 @@
 #define RTCCLK_FREQ		1000000
 
 / {
-	#address-cells = <2>;
-	#size-cells = <2>;
 	model = "SiFive HiFive Unleashed A00";
 	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
 		     "sifive,fu540";
@@ -27,9 +25,6 @@ memory@80000000 {
 		reg = <0x0 0x80000000 0x2 0x00000000>;
 	};
 
-	soc {
-	};
-
 	hfclk: hfclk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
index 9b0b9b85040e..4f66919215f6 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -8,8 +8,6 @@
 #define RTCCLK_FREQ		1000000
 
 / {
-	#address-cells = <2>;
-	#size-cells = <2>;
 	model = "SiFive HiFive Unmatched A00";
 	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
 		     "sifive,fu740";
@@ -27,9 +25,6 @@ memory@80000000 {
 		reg = <0x0 0x80000000 0x4 0x00000000>;
 	};
 
-	soc {
-	};
-
 	hfclk: hfclk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
-- 
2.30.2


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic
  2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
                   ` (2 preceding siblings ...)
  2021-08-25 13:06 ` Krzysztof Kozlowski
@ 2021-08-25 13:06 ` Krzysztof Kozlowski
  2021-08-31 11:27   ` Conor.Dooley
  2021-08-25 13:07 ` [PATCH v2 5/5] riscv: dts: sifive: add missing compatible for plic Krzysztof Kozlowski
  4 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-25 13:06 UTC (permalink / raw)
  To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Krzysztof Kozlowski, Atish Patra, Sagar Shrikant Kadam,
	devicetree, linux-riscv, linux-kernel

The Microchip Icicle kit uses SiFive E51 and U54 cores, so it looks that
also Core Local Interruptor and Platform-Level Interrupt Controller are
coming from SiFive.  Add proper compatibles to silence dtbs_check
warnings:

  clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'canaan,k210-clint']
  interrupt-controller@c000000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic']

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. None
---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index d9f7ee747d0d..6f843afacfad 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -161,7 +161,7 @@ cache-controller@2010000 {
 		};
 
 		clint@2000000 {
-			compatible = "sifive,clint0";
+			compatible = "sifive,fu540-c000-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0xC000>;
 			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
 						&cpu1_intc 3 &cpu1_intc 7
@@ -172,7 +172,7 @@ &cpu3_intc 3 &cpu3_intc 7
 
 		plic: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;
-			compatible = "sifive,plic-1.0.0";
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
 			riscv,ndev = <186>;
 			interrupt-controller;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 5/5] riscv: dts: sifive: add missing compatible for plic
  2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
                   ` (3 preceding siblings ...)
  2021-08-25 13:06 ` [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic Krzysztof Kozlowski
@ 2021-08-25 13:07 ` Krzysztof Kozlowski
  4 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-25 13:07 UTC (permalink / raw)
  To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Krzysztof Kozlowski, Atish Patra, Sagar Shrikant Kadam,
	devicetree, linux-riscv, linux-kernel

Add proper compatible for Platform-Level Interrupt Controller to silence
dtbs_check warnings:

  interrupt-controller@c000000: compatible: ['sifive,plic-1.0.0'] is too short

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. None
---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db861053483..0655b5c4201d 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -141,7 +141,7 @@ soc {
 		ranges;
 		plic0: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;
-			compatible = "sifive,plic-1.0.0";
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
 			riscv,ndev = <53>;
 			interrupt-controller;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic
  2021-08-25 13:06 ` [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic Krzysztof Kozlowski
@ 2021-08-31 11:27   ` Conor.Dooley
  0 siblings, 0 replies; 7+ messages in thread
From: Conor.Dooley @ 2021-08-31 11:27 UTC (permalink / raw)
  To: krzysztof.kozlowski, robh+dt, paul.walmsley, palmer, aou,
	atish.patra, sagar.kadam, devicetree, linux-riscv, linux-kernel

On 25/08/2021 14:06, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The Microchip Icicle kit uses SiFive E51 and U54 cores, so it looks that
> also Core Local Interruptor and Platform-Level Interrupt Controller are
> coming from SiFive.  Add proper compatibles to silence dtbs_check
> warnings:
>
>    clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'canaan,k210-clint']
>    interrupt-controller@c000000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic']
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
> ---
>
> Changes since v1:
> 1. None
> ---
>   arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index d9f7ee747d0d..6f843afacfad 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -161,7 +161,7 @@ cache-controller@2010000 {
>                  };
>
>                  clint@2000000 {
> -                       compatible = "sifive,clint0";
> +                       compatible = "sifive,fu540-c000-clint", "sifive,clint0";
>                          reg = <0x0 0x2000000 0x0 0xC000>;
>                          interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>                                                  &cpu1_intc 3 &cpu1_intc 7
> @@ -172,7 +172,7 @@ &cpu3_intc 3 &cpu3_intc 7
>
>                  plic: interrupt-controller@c000000 {
>                          #interrupt-cells = <1>;
> -                       compatible = "sifive,plic-1.0.0";
> +                       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
>                          reg = <0x0 0xc000000 0x0 0x4000000>;
>                          riscv,ndev = <186>;
>                          interrupt-controller;
> --
> 2.30.2
>
Looks good, we've switched to using this one ourselves also.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2021-08-31 11:27 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
2021-08-25 13:04 ` [PATCH v2 2/5] riscv: dts: sifive: fix Unleashed board compatible Krzysztof Kozlowski
2021-08-25 13:04 ` [PATCH v2 3/5] riscv: dts: sifive: drop duplicated nodes and properties in sifive Krzysztof Kozlowski
2021-08-25 13:06 ` Krzysztof Kozlowski
2021-08-25 13:06 ` [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic Krzysztof Kozlowski
2021-08-31 11:27   ` Conor.Dooley
2021-08-25 13:07 ` [PATCH v2 5/5] riscv: dts: sifive: add missing compatible for plic Krzysztof Kozlowski

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