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From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
To: Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Atish Patra <atish.patra@wdc.com>,
	Sagar Shrikant Kadam <sagar.kadam@sifive.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic
Date: Wed, 25 Aug 2021 15:06:39 +0200	[thread overview]
Message-ID: <20210825130639.203657-1-krzysztof.kozlowski@canonical.com> (raw)
In-Reply-To: <20210825130452.203407-1-krzysztof.kozlowski@canonical.com>

The Microchip Icicle kit uses SiFive E51 and U54 cores, so it looks that
also Core Local Interruptor and Platform-Level Interrupt Controller are
coming from SiFive.  Add proper compatibles to silence dtbs_check
warnings:

  clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'canaan,k210-clint']
  interrupt-controller@c000000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic']

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

---

Changes since v1:
1. None
---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index d9f7ee747d0d..6f843afacfad 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -161,7 +161,7 @@ cache-controller@2010000 {
 		};
 
 		clint@2000000 {
-			compatible = "sifive,clint0";
+			compatible = "sifive,fu540-c000-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0xC000>;
 			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
 						&cpu1_intc 3 &cpu1_intc 7
@@ -172,7 +172,7 @@ &cpu3_intc 3 &cpu3_intc 7
 
 		plic: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;
-			compatible = "sifive,plic-1.0.0";
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
 			riscv,ndev = <186>;
 			interrupt-controller;
-- 
2.30.2


  parent reply	other threads:[~2021-08-25 13:07 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
2021-08-25 13:04 ` [PATCH v2 2/5] riscv: dts: sifive: fix Unleashed board compatible Krzysztof Kozlowski
2021-08-25 13:04 ` [PATCH v2 3/5] riscv: dts: sifive: drop duplicated nodes and properties in sifive Krzysztof Kozlowski
2021-08-25 13:06 ` Krzysztof Kozlowski
2021-08-25 13:06 ` Krzysztof Kozlowski [this message]
2021-08-31 11:27   ` [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic Conor.Dooley
2021-08-25 13:07 ` [PATCH v2 5/5] riscv: dts: sifive: add missing compatible for plic Krzysztof Kozlowski

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