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From: Prathamesh Shete <pshete@nvidia.com>
To: <linus.walleij@linaro.org>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <ldewangan@nvidia.com>,
	<linux-gpio@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <smangipudi@nvidia.com>, <pshete@nvidia.com>
Subject: [PATCH 2/2] pinctrl: tegra: Implement pinmux register save and restore
Date: Tue, 31 Aug 2021 10:58:34 +0530	[thread overview]
Message-ID: <20210831052834.4136-3-pshete@nvidia.com> (raw)
In-Reply-To: <20210831052834.4136-1-pshete@nvidia.com>

From: Laxman Dewangan <ldewangan@nvidia.com>

Implement the pinmux register save and restore for the GPIO
configuration of pins. This helps in changing the pins
configuration for suspend state only.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: pshete <pshete@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c | 66 +++++++++++++++++++++++++++
 drivers/pinctrl/tegra/pinctrl-tegra.h |  1 +
 2 files changed, 67 insertions(+)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 195cfe557511..7f947c952e09 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -275,6 +275,66 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+static int tegra_pinctrl_gpio_save_config(struct pinctrl_dev *pctldev,
+					  struct pinctrl_gpio_range *range,
+					  unsigned offset)
+{
+	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+	const struct tegra_pingroup *g;
+	unsigned group, num_pins;
+	const unsigned *pins;
+	int ret;
+
+	for (group = 0; group < pmx->soc->ngroups; ++group) {
+		ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins);
+		if (ret < 0 || num_pins != 1)
+			continue;
+		if (offset ==  pins[0])
+			break;
+	}
+
+	if (group == pmx->soc->ngroups) {
+		dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);
+		return -EINVAL;
+	}
+
+	g = &pmx->soc->groups[group];
+	if (g->mux_reg >= 0)
+		pmx->gpio_conf[offset] = pmx_readl(pmx, g->mux_bank, g->mux_reg);
+
+	return 0;
+}
+
+static int tegra_pinctrl_gpio_restore_config(struct pinctrl_dev *pctldev,
+					     struct pinctrl_gpio_range *range,
+					     unsigned offset)
+{
+	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+	const struct tegra_pingroup *g;
+	unsigned group, num_pins;
+	const unsigned *pins;
+	int ret;
+
+	for (group = 0; group < pmx->soc->ngroups; ++group) {
+		ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins);
+		if (ret < 0 || num_pins != 1)
+			continue;
+		if (offset == pins[0])
+			break;
+	}
+
+	if (group == pmx->soc->ngroups) {
+		dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);
+		return -EINVAL;
+	}
+
+	g = &pmx->soc->groups[group];
+	if (g->mux_reg >= 0)
+		pmx_writel(pmx, pmx->gpio_conf[offset], g->mux_bank, g->mux_reg);
+
+	return 0;
+}
+
 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
 					     struct pinctrl_gpio_range *range,
 					     unsigned int offset)
@@ -326,6 +386,8 @@ static const struct pinmux_ops tegra_pinmux_ops = {
 	.set_mux = tegra_pinctrl_set_mux,
 	.gpio_request_enable = tegra_pinctrl_gpio_request_enable,
 	.gpio_disable_free = tegra_pinctrl_gpio_disable_free,
+	.gpio_save_config = tegra_pinctrl_gpio_save_config,
+	.gpio_restore_config = tegra_pinctrl_gpio_restore_config,
 };
 
 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
@@ -826,6 +888,10 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 	if (!pmx->backup_regs)
 		return -ENOMEM;
 
+	pmx->gpio_conf = devm_kzalloc(&pdev->dev, backup_regs_size, GFP_KERNEL);
+	if (!pmx->gpio_conf)
+		return -ENOMEM;
+
 	for (i = 0; i < pmx->nbanks; i++) {
 		pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
 		if (IS_ERR(pmx->regs[i]))
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index fcad7f74c5a2..c08c676bfa03 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -18,6 +18,7 @@ struct tegra_pmx {
 	int nbanks;
 	void __iomem **regs;
 	u32 *backup_regs;
+	u32 *gpio_conf;
 };
 
 enum tegra_pinconf_param {
-- 
2.17.1


      parent reply	other threads:[~2021-08-31  5:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-31  5:28 [PATCH 0/2] pinctrl: support to save and restore GPIO conf Prathamesh Shete
2021-08-31  5:28 ` [PATCH 1/2] pinctrl: pimux: Add support to save and restore HW register Prathamesh Shete
2021-08-31  8:13   ` Mikko Perttunen
2021-08-31 14:28   ` kernel test robot
2021-08-31  5:28 ` Prathamesh Shete [this message]

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