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From: "H. Peter Anvin (Intel)" <hpa@zytor.com> To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@alien8.de> Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, "H. Peter Anvin (Intel)" <hpa@zytor.com> Subject: [PATCH] x86/asm: pessimize the pre-initialization case in static_cpu_has() Date: Wed, 8 Sep 2021 10:17:16 -0700 [thread overview] Message-ID: <20210908171716.3340120-1-hpa@zytor.com> (raw) gcc will sometimes manifest the address of boot_cpu_data in a register as part of constant propagation. When multiple static_cpu_has() are used this may foul the mainline code with a register load which will only be used on the fallback path, which is unused after initialization. Explicitly force gcc to use immediate (rip-relative) addressing for the fallback path, thus removing any possible register use from static_cpu_has(). Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com> --- arch/x86/include/asm/cpufeature.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 16a51e7288d5..ff18906b60d8 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -173,20 +173,25 @@ extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit); * means that the boot_cpu_has() variant is already fast enough for the * majority of cases and you should stick to using it as it is generally * only two instructions: a RIP-relative MOV and a TEST. + * + * Do not use an "m" constraint for [cap_byte] here: gcc doesn't know + * that this is only used on a fallback path and will sometimes cause + * it to manifest the address of boot_cpu_data in a register, fouling + * the mainline (post-initialization) code. */ static __always_inline bool _static_cpu_has(u16 bit) { asm_volatile_goto( ALTERNATIVE_TERNARY("jmp 6f", %P[feature], "", "jmp %l[t_no]") - ".section .altinstr_aux,\"ax\"\n" + ".pushsection .altinstr_aux,\"ax\"\n" "6:\n" - " testb %[bitnum],%[cap_byte]\n" + " testb %[bitnum],%P[cap_byte]\n" " jnz %l[t_yes]\n" " jmp %l[t_no]\n" - ".previous\n" + ".popsection\n" : : [feature] "i" (bit), [bitnum] "i" (1 << (bit & 7)), - [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3]) + [cap_byte] "i" (&((const char *)boot_cpu_data.x86_capability)[bit >> 3]) : : t_yes, t_no); t_yes: return true; -- 2.31.1
next reply other threads:[~2021-09-08 17:17 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-08 17:17 H. Peter Anvin (Intel) [this message] 2021-09-09 17:01 ` [PATCH] x86/asm: pessimize the pre-initialization case in static_cpu_has() Borislav Petkov 2021-09-09 21:28 ` H. Peter Anvin 2021-09-09 21:53 ` Borislav Petkov 2021-09-09 22:17 ` H. Peter Anvin 2021-09-10 9:14 ` Borislav Petkov 2021-09-10 19:25 ` H. Peter Anvin 2021-09-09 22:08 ` [PATCH v2 0/2] x86/asm: avoid register pressure from static_cpu_has() H. Peter Anvin (Intel) 2021-09-09 22:08 ` [PATCH v2 1/2] x86/asm: add _ASM_RIP() macro for x86-64 (%rip) suffix H. Peter Anvin (Intel) 2021-09-09 22:08 ` [PATCH v2 2/2] x86/asm: pessimize the pre-initialization case in static_cpu_has() H. Peter Anvin (Intel) 2021-09-10 9:16 ` [PATCH v2 0/2] x86/asm: avoid register pressure from static_cpu_has() Borislav Petkov 2021-09-10 13:24 ` Borislav Petkov 2021-09-10 19:59 ` [PATCH v3 0/2] x86/asm: avoid register pressure from the init case in static_cpu_has() H. Peter Anvin (Intel) 2021-09-10 19:59 ` [PATCH] drm/bochs: add Bochs PCI ID for Simics model H. Peter Anvin (Intel) 2021-09-10 19:59 ` [PATCH v3 1/2] x86/asm: add _ASM_RIP() macro for x86-64 (%rip) suffix H. Peter Anvin (Intel) 2021-09-13 19:39 ` [tip: x86/cpu] x86/asm: Add " tip-bot2 for H. Peter Anvin (Intel) 2021-09-10 19:59 ` [PATCH v3 2/2] x86/asm: avoid adding register pressure for the init case in static_cpu_has() H. Peter Anvin (Intel) 2021-09-13 19:39 ` [tip: x86/cpu] x86/asm: Avoid " tip-bot2 for H. Peter Anvin
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