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* [PATCH] x86/asm: pessimize the pre-initialization case in static_cpu_has()
@ 2021-09-08 17:17 H. Peter Anvin (Intel)
  2021-09-09 17:01 ` Borislav Petkov
                   ` (2 more replies)
  0 siblings, 3 replies; 20+ messages in thread
From: H. Peter Anvin (Intel) @ 2021-09-08 17:17 UTC (permalink / raw)
  To: Thomas Gleixner, Ingo Molnar, Andy Lutomirski, Borislav Petkov
  Cc: Linux Kernel Mailing List, H. Peter Anvin (Intel)

gcc will sometimes manifest the address of boot_cpu_data in a register
as part of constant propagation. When multiple static_cpu_has() are
used this may foul the mainline code with a register load which will
only be used on the fallback path, which is unused after
initialization.

Explicitly force gcc to use immediate (rip-relative) addressing for
the fallback path, thus removing any possible register use from
static_cpu_has().

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
---
 arch/x86/include/asm/cpufeature.h | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 16a51e7288d5..ff18906b60d8 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -173,20 +173,25 @@ extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit);
  * means that the boot_cpu_has() variant is already fast enough for the
  * majority of cases and you should stick to using it as it is generally
  * only two instructions: a RIP-relative MOV and a TEST.
+ *
+ * Do not use an "m" constraint for [cap_byte] here: gcc doesn't know
+ * that this is only used on a fallback path and will sometimes cause
+ * it to manifest the address of boot_cpu_data in a register, fouling
+ * the mainline (post-initialization) code.
  */
 static __always_inline bool _static_cpu_has(u16 bit)
 {
 	asm_volatile_goto(
 		ALTERNATIVE_TERNARY("jmp 6f", %P[feature], "", "jmp %l[t_no]")
-		".section .altinstr_aux,\"ax\"\n"
+		".pushsection .altinstr_aux,\"ax\"\n"
 		"6:\n"
-		" testb %[bitnum],%[cap_byte]\n"
+		" testb %[bitnum],%P[cap_byte]\n"
 		" jnz %l[t_yes]\n"
 		" jmp %l[t_no]\n"
-		".previous\n"
+		".popsection\n"
 		 : : [feature]  "i" (bit),
 		     [bitnum]   "i" (1 << (bit & 7)),
-		     [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3])
+		     [cap_byte] "i" (&((const char *)boot_cpu_data.x86_capability)[bit >> 3])
 		 : : t_yes, t_no);
 t_yes:
 	return true;
-- 
2.31.1


^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH] drm/bochs: add Bochs PCI ID for Simics model
@ 2021-09-10  1:06 H. Peter Anvin (Intel)
  2021-09-15  6:29 ` Gerd Hoffmann
  0 siblings, 1 reply; 20+ messages in thread
From: H. Peter Anvin (Intel) @ 2021-09-10  1:06 UTC (permalink / raw)
  To: Gerd Hoffmann, David Airlie, Daniel Vetter
  Cc: virtualization, dri-devel, linux-kernel, H. Peter Anvin (Intel)

Current (and older) Simics models for the Bochs VGA used the wrong PCI
vendor ID (0x4321 instead of 0x1234).  Although this can hopefully be
fixed in the future, it is a problem for users of the current version,
not the least because to update the device ID the BIOS has to be
rebuilt in order to see BIOS output.

Add support for the 4321:1111 device number in addition to the
1234:1111 one.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
---
 drivers/gpu/drm/tiny/bochs.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/tiny/bochs.c b/drivers/gpu/drm/tiny/bochs.c
index 73415fa9ae0f..2ce3bd903b70 100644
--- a/drivers/gpu/drm/tiny/bochs.c
+++ b/drivers/gpu/drm/tiny/bochs.c
@@ -63,6 +63,7 @@ MODULE_PARM_DESC(defy, "default y resolution");
 
 enum bochs_types {
 	BOCHS_QEMU_STDVGA,
+	BOCHS_SIMICS,
 	BOCHS_UNKNOWN,
 };
 
@@ -695,6 +696,13 @@ static const struct pci_device_id bochs_pci_tbl[] = {
 		.subdevice   = PCI_ANY_ID,
 		.driver_data = BOCHS_UNKNOWN,
 	},
+	{
+		.vendor      = 0x4321,
+		.device      = 0x1111,
+		.subvendor   = PCI_ANY_ID,
+		.subdevice   = PCI_ANY_ID,
+		.driver_data = BOCHS_SIMICS,
+	},
 	{ /* end of list */ }
 };
 
-- 
2.31.1


^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2021-09-15  6:29 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-08 17:17 [PATCH] x86/asm: pessimize the pre-initialization case in static_cpu_has() H. Peter Anvin (Intel)
2021-09-09 17:01 ` Borislav Petkov
2021-09-09 21:28   ` H. Peter Anvin
2021-09-09 21:53     ` Borislav Petkov
2021-09-09 22:17     ` H. Peter Anvin
2021-09-10  9:14       ` Borislav Petkov
2021-09-10 19:25         ` H. Peter Anvin
2021-09-09 22:08 ` [PATCH v2 0/2] x86/asm: avoid register pressure from static_cpu_has() H. Peter Anvin (Intel)
2021-09-09 22:08   ` [PATCH v2 1/2] x86/asm: add _ASM_RIP() macro for x86-64 (%rip) suffix H. Peter Anvin (Intel)
2021-09-09 22:08   ` [PATCH v2 2/2] x86/asm: pessimize the pre-initialization case in static_cpu_has() H. Peter Anvin (Intel)
2021-09-10  9:16   ` [PATCH v2 0/2] x86/asm: avoid register pressure from static_cpu_has() Borislav Petkov
2021-09-10 13:24     ` Borislav Petkov
2021-09-10 19:59 ` [PATCH v3 0/2] x86/asm: avoid register pressure from the init case in static_cpu_has() H. Peter Anvin (Intel)
2021-09-10 19:59   ` [PATCH] drm/bochs: add Bochs PCI ID for Simics model H. Peter Anvin (Intel)
2021-09-10 19:59   ` [PATCH v3 1/2] x86/asm: add _ASM_RIP() macro for x86-64 (%rip) suffix H. Peter Anvin (Intel)
2021-09-13 19:39     ` [tip: x86/cpu] x86/asm: Add " tip-bot2 for H. Peter Anvin (Intel)
2021-09-10 19:59   ` [PATCH v3 2/2] x86/asm: avoid adding register pressure for the init case in static_cpu_has() H. Peter Anvin (Intel)
2021-09-13 19:39     ` [tip: x86/cpu] x86/asm: Avoid " tip-bot2 for H. Peter Anvin
2021-09-10  1:06 [PATCH] drm/bochs: add Bochs PCI ID for Simics model H. Peter Anvin (Intel)
2021-09-15  6:29 ` Gerd Hoffmann

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