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From: Dian zheng <paniaguaholt597336@gmail.com>
To: jiaxun.yang@flygoat.com
Cc: cand@gmx.com, chenhuacai@kernel.org, daniel.lezcano@linaro.org,
drjones@redhat.com, fancer.lancer@gmail.com, huangll@lemote.com,
john.garry@huawei.com, linux-kernel@vger.kernel.org,
linux-mips@vger.kernel.org, marcan@marcan.st,
mgorman@techsingularity.net, ndesaulniers@google.com,
paul@crapouillou.net, romain.naour@gmail.com,
sudipm.mukherjee@gmail.com, sumanthk@linux.ibm.com,
tanj@lemote.com, tglx@linutronix.de, tmricht@linux.ibm.com,
tom.zanussi@linux.intel.com, tsbogend@alpha.franken.de,
will@kernel.org, yangtiezhu@loongson.cn,
zhangshaokun@hisilicon.com, zhengd@lemote.com,
zhouyanjie@wanyeetech.com
Subject: [PATCH v1 2/3] MIPS: time: Add plat_have_sched_clock That variable That variable would allow platform to register their own sched_clock instead of csrc-r4k.
Date: Sat, 18 Sep 2021 15:21:59 +0800 [thread overview]
Message-ID: <20210918072200.95304-2-zhengd@lemote.com> (raw)
In-Reply-To: <20210918072200.95304-1-zhengd@lemote.com>
From: Dian Zheng <zhengd@lemote.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Dian Zheng <zhengd@lemote.com>
---
arch/mips/include/asm/time.h | 3 +++
arch/mips/kernel/csrc-r4k.c | 5 ++---
arch/mips/kernel/time.c | 3 +++
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index e855a3611d92..e235b8a27768 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -28,6 +28,9 @@ extern void plat_time_init(void);
*/
extern unsigned int mips_hpt_frequency;
+/* True if platform registered sched_clock by itself */
+extern bool plat_have_sched_clock __initdata;
+
/*
* The performance counter IRQ on MIPS is a close relative to the timer IRQ
* so it lives here.
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index edc4afc080fa..b50a24da6528 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -122,9 +122,8 @@ int __init init_r4k_clocksource(void)
clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
-#ifndef CONFIG_CPU_FREQ
- sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
-#endif
+ if (!IS_ENABLED(CONFIG_CPU_FREQ) && !plat_have_sched_clock)
+ sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
return 0;
}
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index caa01457dce6..baf33da8c79d 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -123,6 +123,9 @@ EXPORT_SYMBOL(perf_irq);
unsigned int mips_hpt_frequency;
EXPORT_SYMBOL_GPL(mips_hpt_frequency);
+/* True if platform registered sched_clock by itself */
+bool plat_have_sched_clock __initdata;
+
static __init int cpu_has_mfc0_count_bug(void)
{
switch (current_cpu_type()) {
--
2.18.1
next prev parent reply other threads:[~2021-09-18 7:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210910071835.21801-1-zhengd@lemote.com>
2021-09-10 7:34 ` [PATCH] clocksource: Loongson constant timer support Jiaxun Yang
2021-09-18 7:21 ` [PATCH v1 1/3] MIPS: cevt-r4k: Enable intimer for Loongson CPUs with extimer Loongson64C and Loongson64G have extimer feature, which is sharing Cause.TI with intimer (which is cevt-r4k) Dian zheng
2021-09-18 7:21 ` Dian zheng [this message]
2021-09-18 7:55 ` Dian zheng
2021-09-18 7:57 ` [PATCH v1 3/3] clocksource: Loongson constant timer support Loongson constant timer is found in Loongson-3A4000 processor. It has a counter which is globally accessiable via rdhwr instruction, also each core has a clock event generator connected to this clock source sharing interrupt with MIPS cont & comapre cevt Dian zheng
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