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[222.92.8.138]) by smtp.gmail.com with ESMTPSA id a71sm8451097pfd.86.2021.09.18.00.55.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Sep 2021 00:55:52 -0700 (PDT) From: Dian zheng X-Google-Original-From: Dian zheng To: jiaxun.yang@flygoat.com Cc: cand@gmx.com, chenhuacai@kernel.org, daniel.lezcano@linaro.org, drjones@redhat.com, fancer.lancer@gmail.com, huangll@lemote.com, john.garry@huawei.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, marcan@marcan.st, mgorman@techsingularity.net, ndesaulniers@google.com, paul@crapouillou.net, romain.naour@gmail.com, sudipm.mukherjee@gmail.com, sumanthk@linux.ibm.com, tanj@lemote.com, tglx@linutronix.de, tmricht@linux.ibm.com, tom.zanussi@linux.intel.com, tsbogend@alpha.franken.de, will@kernel.org, yangtiezhu@loongson.cn, zhangshaokun@hisilicon.com, zhengd@lemote.com, zhouyanjie@wanyeetech.com Subject: [PATCH v1 1/3] MIPS: cevt-r4k: Enable intimer for Loongson CPUs with extimer Loongson64C and Loongson64G have extimer feature, which is sharing Cause.TI with intimer (which is cevt-r4k). Date: Sat, 18 Sep 2021 15:55:18 +0800 Message-Id: <20210918075520.95927-1-zhengd@lemote.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dian Zheng To ensure the cevt-r4k's usability, we need to add a callback for clock device to ensure intimer is enabled when cevt-r4k is enabled. Signed-off-by: Jiaxun Yang Signed-off-by: Dian Zheng --- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/kernel/cevt-r4k.c | 25 +++++++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 6 +++++- 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 3d71081afc55..787bd53be900 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -573,6 +573,10 @@ # define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) #endif +#ifndef cpu_has_extimer +# define cpu_has_extimer __opt(MIPS_CPU_EXTIMER) +#endif + #ifdef CONFIG_SMP /* * Some systems share FTLB RAMs between threads within a core (siblings in diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index d45a52f65b7a..8d221b4c3fa3 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -428,6 +428,7 @@ enum cpu_type_enum { #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */ #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */ #define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */ +#define MIPS_CPU_EXTIMER BIT_ULL(63) /* CPU has External Timer (Loongson) */ /* * CPU ASE encodings diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 32ec67c9ab67..91fc62001149 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -15,6 +15,8 @@ #include #include +#include +#include static int mips_next_event(unsigned long delta, struct clock_event_device *evt) @@ -290,6 +292,24 @@ core_initcall(r4k_register_cpufreq_notifier); #endif /* !CONFIG_CPU_FREQ */ +#ifdef CONFIG_CPU_LOONGSON64 +static int c0_compare_int_enable(struct clock_event_device *cd) +{ + if (cpu_has_extimer) + set_c0_config6(LOONGSON_CONF6_INTIMER); + + return 0; +} + +static int c0_compare_int_disable(struct clock_event_device *cd) +{ + if (cpu_has_extimer) + clear_c0_config6(LOONGSON_CONF6_INTIMER); + + return 0; +} +#endif + int r4k_clockevent_init(void) { unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; @@ -325,6 +345,11 @@ int r4k_clockevent_init(void) cd->set_next_event = mips_next_event; cd->event_handler = mips_event_handler; +#ifdef CONFIG_CPU_LOONGSON64 + cd->set_state_oneshot = c0_compare_int_enable; + cd->set_state_shutdown = c0_compare_int_disable; +#endif + clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff); if (cp0_timer_irq_installed) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 630fcb4cb30e..8a9b028a1df7 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1723,6 +1723,9 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c) if (cfg2 & LOONGSON_CFG2_LEXT2) c->ases |= MIPS_ASE_LOONGSON_EXT2; + if (cfg2 & LOONGSON_CFG2_LLFTP) + c->options |= MIPS_CPU_EXTIMER; + if (cfg2 & LOONGSON_CFG2_LSPW) { c->options |= MIPS_CPU_LDPTE; c->guest.options |= MIPS_CPU_LDPTE; @@ -1780,7 +1783,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) * Also some early Loongson-3A2000 had wrong TLB type in Config * register, we correct it here. */ - c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE | + MIPS_CPU_EXTIMER; c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ -- 2.18.1