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From: Nikita Shubin <nikita.shubin@maquefel.me>
To: Atish Patra <atish.patra@wdc.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Anup Patel <anup.patel@wdc.com>, Ard Biesheuvel <ardb@kernel.org>,
	"Darrick J. Wong" <djwong@kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Guo Ren <guoren@linux.alibaba.com>,
	Heinrich Schuchardt <xypron.glpk@gmx.de>,
	Jiri Olsa <jolsa@redhat.com>, John Garry <john.garry@huawei.com>,
	Jonathan Corbet <corbet@lwn.net>,
	"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	"linux-perf-users@vger.kernel.org"
	<linux-perf-users@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	Nick Kossifidis <mick@ics.forth.gr>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [v3 01/10] RISC-V: Remove the current perf implementation
Date: Wed, 22 Sep 2021 08:25:43 +0300	[thread overview]
Message-ID: <20210922082543.71fc5619@redslave.neermore.group> (raw)
In-Reply-To: <238571632287002@mail.yandex.ru>

On Wed, 22 Sep 2021 08:11:44 +0300
nikita.shubin@maquefel.me wrote:

> Hello Atish.
>  
> 10.09.2021, 22:28, "Atish Patra" <atish.patra@wdc.com>:
> 
> > The current perf implementation in RISC-V is not very useful as it
> > can not count any events other than cycle/instructions. Moreover,
> > perf record can not be used or the events can not be started or
> > stopped.
> > 
> > Remove the implementation now for a better platform driver in future
> > that will implement most of the missing functionality.
> Your v3 version still breaks the build with CONFIG_BPF_SYSCALL
> enabled: 
> kernel/events/core.c: In function 'bpf_overflow_handler':
> kernel/events/core.c:9914:18: error: assignment to
> 'bpf_user_pt_regs_t *' {aka 'struct user_regs_struct *'} from
> incompatible pointer type 'struct pt_regs *'
> [-Werror=incompatible-pointer-types] 9914 |         ctx.regs =
> perf_arch_bpf_user_pt_regs(regs); |                  ^ 

Sorry for the noise.

Everything complies fine - i mistaken and applied older version again. 

> Yours,
> Nikita Shubin.
> 


  parent reply	other threads:[~2021-09-22  5:25 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-10 19:27 [v3 00/10] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Atish Patra
2021-09-10 19:27 ` [v3 01/10] RISC-V: Remove the current perf implementation Atish Patra
     [not found]   ` <238571632287002@mail.yandex.ru>
2021-09-22  5:25     ` Nikita Shubin [this message]
2021-09-10 19:27 ` [v3 02/10] RISC-V: Add CSR encodings for all HPMCOUNTERS Atish Patra
2021-09-10 19:27 ` [v3 03/10] RISC-V: Add a perf core library for pmu drivers Atish Patra
2021-09-10 19:27 ` [v3 04/10] RISC-V: Add a simple platform driver for RISC-V legacy perf Atish Patra
2021-09-10 19:27 ` [v3 05/10] RISC-V: Add RISC-V SBI PMU extension definitions Atish Patra
2021-09-10 19:27 ` [v3 06/10] dt-binding: pmu: Add RISC-V PMU DT bindings Atish Patra
2021-09-13 12:18   ` Rob Herring
2021-09-14 15:50   ` Rob Herring
2021-09-10 19:27 ` [v3 07/10] RISC-V: Add perf platform driver based on SBI PMU extension Atish Patra
2021-09-10 19:27 ` [v3 08/10] RISC-V: Add interrupt support for perf Atish Patra
2021-09-10 19:27 ` [v3 09/10] Documentation: riscv: Remove the old documentation Atish Patra
2021-09-10 19:27 ` [v3 10/10] MAINTAINERS: Add entry for RISC-V PMU drivers Atish Patra
2021-10-04 18:20 ` [v3 00/10] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Palmer Dabbelt
2021-10-06 18:27   ` Atish Patra
2021-10-05  9:17 ` Nikita Shubin
2021-10-06 18:28   ` Atish Patra

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